2 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
4 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/tty.h>
11 #include <linux/tty_flip.h>
12 #include <linux/major.h>
13 #include <linux/circ_buf.h>
14 #include <linux/serial.h>
15 #include <linux/sysrq.h>
16 #include <linux/console.h>
17 #include <linux/spinlock.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/irq.h>
25 #if defined(CONFIG_MAGIC_SYSRQ)
29 #include <linux/serial_core.h>
31 #define SC26XX_MAJOR 204
32 #define SC26XX_MINOR_START 205
35 struct uart_sc26xx_port {
36 struct uart_port port[2];
46 /* register common to both ports */
53 #define WR_OPR_SET 0x38
54 #define WR_OPR_CLR 0x3C
56 /* access common register */
57 #define READ_SC(p, r) readb((p)->membase + RD_##r)
58 #define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
60 /* register per port */
61 #define RD_PORT_MRx 0x00
62 #define RD_PORT_SR 0x04
63 #define RD_PORT_RHR 0x0c
65 #define WR_PORT_MRx 0x00
66 #define WR_PORT_CSR 0x04
67 #define WR_PORT_CR 0x08
68 #define WR_PORT_THR 0x0c
71 #define SR_BREAK (1 << 7)
72 #define SR_FRAME (1 << 6)
73 #define SR_PARITY (1 << 5)
74 #define SR_OVERRUN (1 << 4)
75 #define SR_TXRDY (1 << 2)
76 #define SR_RXRDY (1 << 0)
78 #define CR_RES_MR (1 << 4)
79 #define CR_RES_RX (2 << 4)
80 #define CR_RES_TX (3 << 4)
81 #define CR_STRT_BRK (6 << 4)
82 #define CR_STOP_BRK (7 << 4)
83 #define CR_DIS_TX (1 << 3)
84 #define CR_ENA_TX (1 << 2)
85 #define CR_DIS_RX (1 << 1)
86 #define CR_ENA_RX (1 << 0)
89 #define ISR_RXRDYB (1 << 5)
90 #define ISR_TXRDYB (1 << 4)
91 #define ISR_RXRDYA (1 << 1)
92 #define ISR_TXRDYA (1 << 0)
95 #define IMR_RXRDY (1 << 1)
96 #define IMR_TXRDY (1 << 0)
98 /* access port register */
99 static inline u8 read_sc_port(struct uart_port *p, u8 reg)
101 return readb(p->membase + p->line * 0x20 + reg);
104 static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
106 writeb(val, p->membase + p->line * 0x20 + reg);
109 #define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
110 #define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
112 static void sc26xx_enable_irq(struct uart_port *port, int mask)
114 struct uart_sc26xx_port *up;
115 int line = port->line;
118 up = container_of(port, struct uart_sc26xx_port, port[0]);
120 up->imr |= mask << (line * 4);
121 WRITE_SC(port, IMR, up->imr);
124 static void sc26xx_disable_irq(struct uart_port *port, int mask)
126 struct uart_sc26xx_port *up;
127 int line = port->line;
130 up = container_of(port, struct uart_sc26xx_port, port[0]);
132 up->imr &= ~(mask << (line * 4));
133 WRITE_SC(port, IMR, up->imr);
136 static struct tty_struct *receive_chars(struct uart_port *port)
138 struct tty_struct *tty = NULL;
144 if (port->state != NULL) /* Unopened serial console */
145 tty = port->state->port.tty;
147 while (limit-- > 0) {
148 status = READ_SC_PORT(port, SR);
149 if (!(status & SR_RXRDY))
151 ch = READ_SC_PORT(port, RHR);
156 if (unlikely(status & (SR_BREAK | SR_FRAME |
157 SR_PARITY | SR_OVERRUN))) {
158 if (status & SR_BREAK) {
159 status &= ~(SR_PARITY | SR_FRAME);
161 if (uart_handle_break(port))
163 } else if (status & SR_PARITY)
164 port->icount.parity++;
165 else if (status & SR_FRAME)
166 port->icount.frame++;
167 if (status & SR_OVERRUN)
168 port->icount.overrun++;
170 status &= port->read_status_mask;
171 if (status & SR_BREAK)
173 else if (status & SR_PARITY)
175 else if (status & SR_FRAME)
179 if (uart_handle_sysrq_char(port, ch))
182 if (status & port->ignore_status_mask)
185 tty_insert_flip_char(tty, ch, flag);
190 static void transmit_chars(struct uart_port *port)
192 struct circ_buf *xmit;
197 xmit = &port->state->xmit;
198 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
199 sc26xx_disable_irq(port, IMR_TXRDY);
202 while (!uart_circ_empty(xmit)) {
203 if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
206 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
207 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
210 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
211 uart_write_wakeup(port);
214 static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
216 struct uart_sc26xx_port *up = dev_id;
217 struct tty_struct *tty;
221 spin_lock_irqsave(&up->port[0].lock, flags);
224 isr = READ_SC(&up->port[0], ISR);
225 if (isr & ISR_TXRDYA)
226 transmit_chars(&up->port[0]);
227 if (isr & ISR_RXRDYA)
228 tty = receive_chars(&up->port[0]);
230 spin_unlock(&up->port[0].lock);
233 tty_flip_buffer_push(tty);
235 spin_lock(&up->port[1].lock);
238 if (isr & ISR_TXRDYB)
239 transmit_chars(&up->port[1]);
240 if (isr & ISR_RXRDYB)
241 tty = receive_chars(&up->port[1]);
243 spin_unlock_irqrestore(&up->port[1].lock, flags);
246 tty_flip_buffer_push(tty);
251 /* port->lock is not held. */
252 static unsigned int sc26xx_tx_empty(struct uart_port *port)
254 return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
257 /* port->lock held by caller. */
258 static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
260 struct uart_sc26xx_port *up;
261 int line = port->line;
264 up = container_of(port, struct uart_sc26xx_port, port[0]);
266 if (up->dtr_mask[line]) {
267 if (mctrl & TIOCM_DTR)
268 WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
270 WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
272 if (up->rts_mask[line]) {
273 if (mctrl & TIOCM_RTS)
274 WRITE_SC(port, OPR_SET, up->rts_mask[line]);
276 WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
280 /* port->lock is held by caller and interrupts are disabled. */
281 static unsigned int sc26xx_get_mctrl(struct uart_port *port)
283 struct uart_sc26xx_port *up;
284 int line = port->line;
285 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
289 up = container_of(port, struct uart_sc26xx_port, port[0]);
290 ipr = READ_SC(port, IPR) ^ 0xff;
292 if (up->dsr_mask[line]) {
294 mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
296 if (up->cts_mask[line]) {
298 mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
300 if (up->dcd_mask[line]) {
302 mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
304 if (up->ri_mask[line]) {
306 mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
311 /* port->lock held by caller. */
312 static void sc26xx_stop_tx(struct uart_port *port)
317 /* port->lock held by caller. */
318 static void sc26xx_start_tx(struct uart_port *port)
320 struct circ_buf *xmit = &port->state->xmit;
322 while (!uart_circ_empty(xmit)) {
323 if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
324 sc26xx_enable_irq(port, IMR_TXRDY);
327 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
328 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
333 /* port->lock held by caller. */
334 static void sc26xx_stop_rx(struct uart_port *port)
338 /* port->lock held by caller. */
339 static void sc26xx_enable_ms(struct uart_port *port)
343 /* port->lock is not held. */
344 static void sc26xx_break_ctl(struct uart_port *port, int break_state)
346 if (break_state == -1)
347 WRITE_SC_PORT(port, CR, CR_STRT_BRK);
349 WRITE_SC_PORT(port, CR, CR_STOP_BRK);
352 /* port->lock is not held. */
353 static int sc26xx_startup(struct uart_port *port)
355 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
356 WRITE_SC(port, OPCR, 0);
358 /* reset tx and rx */
359 WRITE_SC_PORT(port, CR, CR_RES_RX);
360 WRITE_SC_PORT(port, CR, CR_RES_TX);
363 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
366 sc26xx_enable_irq(port, IMR_RXRDY);
370 /* port->lock is not held. */
371 static void sc26xx_shutdown(struct uart_port *port)
373 /* disable interrupst */
374 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
377 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
380 /* port->lock is not held. */
381 static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
382 struct ktermios *old)
384 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
385 unsigned int quot = uart_get_divisor(port, baud);
386 unsigned int iflag, cflag;
390 spin_lock_irqsave(&port->lock, flags);
392 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
395 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
397 iflag = termios->c_iflag;
398 cflag = termios->c_cflag;
400 port->read_status_mask = SR_OVERRUN;
402 port->read_status_mask |= SR_PARITY | SR_FRAME;
403 if (iflag & (BRKINT | PARMRK))
404 port->read_status_mask |= SR_BREAK;
406 port->ignore_status_mask = 0;
408 port->ignore_status_mask |= SR_BREAK;
409 if ((cflag & CREAD) == 0)
410 port->ignore_status_mask |= SR_BREAK | SR_FRAME |
411 SR_PARITY | SR_OVERRUN;
413 switch (cflag & CSIZE) {
431 if (cflag & PARENB) {
474 WRITE_SC_PORT(port, CR, CR_RES_MR);
475 WRITE_SC_PORT(port, MRx, mr1);
476 WRITE_SC_PORT(port, MRx, mr2);
478 WRITE_SC(port, ACR, 0x80);
479 WRITE_SC_PORT(port, CSR, csr);
481 /* reset tx and rx */
482 WRITE_SC_PORT(port, CR, CR_RES_RX);
483 WRITE_SC_PORT(port, CR, CR_RES_TX);
485 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
486 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
490 uart_update_timeout(port, cflag,
491 (port->uartclk / (16 * quot)));
493 spin_unlock_irqrestore(&port->lock, flags);
496 static const char *sc26xx_type(struct uart_port *port)
501 static void sc26xx_release_port(struct uart_port *port)
505 static int sc26xx_request_port(struct uart_port *port)
510 static void sc26xx_config_port(struct uart_port *port, int flags)
514 static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
519 static struct uart_ops sc26xx_ops = {
520 .tx_empty = sc26xx_tx_empty,
521 .set_mctrl = sc26xx_set_mctrl,
522 .get_mctrl = sc26xx_get_mctrl,
523 .stop_tx = sc26xx_stop_tx,
524 .start_tx = sc26xx_start_tx,
525 .stop_rx = sc26xx_stop_rx,
526 .enable_ms = sc26xx_enable_ms,
527 .break_ctl = sc26xx_break_ctl,
528 .startup = sc26xx_startup,
529 .shutdown = sc26xx_shutdown,
530 .set_termios = sc26xx_set_termios,
532 .release_port = sc26xx_release_port,
533 .request_port = sc26xx_request_port,
534 .config_port = sc26xx_config_port,
535 .verify_port = sc26xx_verify_port,
538 static struct uart_port *sc26xx_port;
540 #ifdef CONFIG_SERIAL_SC26XX_CONSOLE
541 static void sc26xx_console_putchar(struct uart_port *port, char c)
546 spin_lock_irqsave(&port->lock, flags);
548 while (limit-- > 0) {
549 if (READ_SC_PORT(port, SR) & SR_TXRDY) {
550 WRITE_SC_PORT(port, THR, c);
556 spin_unlock_irqrestore(&port->lock, flags);
559 static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
561 struct uart_port *port = sc26xx_port;
564 for (i = 0; i < n; i++) {
566 sc26xx_console_putchar(port, '\r');
567 sc26xx_console_putchar(port, *s++);
571 static int __init sc26xx_console_setup(struct console *con, char *options)
573 struct uart_port *port = sc26xx_port;
579 if (port->type != PORT_SC26XX)
582 printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
584 uart_parse_options(options, &baud, &parity, &bits, &flow);
586 return uart_set_options(port, con, baud, parity, bits, flow);
589 static struct uart_driver sc26xx_reg;
590 static struct console sc26xx_console = {
592 .write = sc26xx_console_write,
593 .device = uart_console_device,
594 .setup = sc26xx_console_setup,
595 .flags = CON_PRINTBUFFER,
599 #define SC26XX_CONSOLE &sc26xx_console
601 #define SC26XX_CONSOLE NULL
604 static struct uart_driver sc26xx_reg = {
605 .owner = THIS_MODULE,
606 .driver_name = "SC26xx",
608 .major = SC26XX_MAJOR,
609 .minor = SC26XX_MINOR_START,
611 .cons = SC26XX_CONSOLE,
614 static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
616 unsigned int bit = (flags >> bitpos) & 15;
618 return bit ? (1 << (bit - 1)) : 0;
621 static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
622 int line, unsigned int data)
624 up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
625 up->rts_mask[line] = sc26xx_flags2mask(data, 4);
626 up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
627 up->cts_mask[line] = sc26xx_flags2mask(data, 12);
628 up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
629 up->ri_mask[line] = sc26xx_flags2mask(data, 20);
632 static int __devinit sc26xx_probe(struct platform_device *dev)
634 struct resource *res;
635 struct uart_sc26xx_port *up;
636 unsigned int *sc26xx_data = dev->dev.platform_data;
639 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
643 up = kzalloc(sizeof *up, GFP_KERNEL);
647 up->port[0].line = 0;
648 up->port[0].ops = &sc26xx_ops;
649 up->port[0].type = PORT_SC26XX;
650 up->port[0].uartclk = (29491200 / 16); /* arbitrary */
652 up->port[0].mapbase = res->start;
653 up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
654 up->port[0].iotype = UPIO_MEM;
655 up->port[0].irq = platform_get_irq(dev, 0);
657 up->port[0].dev = &dev->dev;
659 sc26xx_init_masks(up, 0, sc26xx_data[0]);
661 sc26xx_port = &up->port[0];
663 up->port[1].line = 1;
664 up->port[1].ops = &sc26xx_ops;
665 up->port[1].type = PORT_SC26XX;
666 up->port[1].uartclk = (29491200 / 16); /* arbitrary */
668 up->port[1].mapbase = up->port[0].mapbase;
669 up->port[1].membase = up->port[0].membase;
670 up->port[1].iotype = UPIO_MEM;
671 up->port[1].irq = up->port[0].irq;
673 up->port[1].dev = &dev->dev;
675 sc26xx_init_masks(up, 1, sc26xx_data[1]);
677 err = uart_register_driver(&sc26xx_reg);
681 sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
683 err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
685 goto out_unregister_driver;
687 err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
689 goto out_remove_port0;
691 err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
693 goto out_remove_ports;
695 dev_set_drvdata(&dev->dev, up);
699 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
701 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
703 out_unregister_driver:
704 uart_unregister_driver(&sc26xx_reg);
713 static int __exit sc26xx_driver_remove(struct platform_device *dev)
715 struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
717 free_irq(up->port[0].irq, up);
719 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
720 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
722 uart_unregister_driver(&sc26xx_reg);
727 dev_set_drvdata(&dev->dev, NULL);
731 static struct platform_driver sc26xx_driver = {
732 .probe = sc26xx_probe,
733 .remove = __devexit_p(sc26xx_driver_remove),
736 .owner = THIS_MODULE,
740 module_platform_driver(sc26xx_driver);
742 MODULE_AUTHOR("Thomas Bogendörfer");
743 MODULE_DESCRIPTION("SC681/SC2692 serial driver");
744 MODULE_VERSION("1.0");
745 MODULE_LICENSE("GPL");
746 MODULE_ALIAS("platform:SC26xx");