drivers/usb/host/imx21-hcd.c

   1 /*
   2  * USB Host Controller Driver for IMX21
   3  *
   4  * Copyright (C) 2006 Loping Dog Embedded Systems
   5  * Copyright (C) 2009 Martin Fuzzey
   6  * Originally written by Jay Monkman <jtm@lopingdog.com>
   7  * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  * for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software Foundation,
  21  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24
  25  /*
  26   * The i.MX21 USB hardware contains
  27   *    * 32 transfer descriptors (called ETDs)
  28   *    * 4Kb of Data memory
  29   *
  30   * The data memory is shared between the host and function controllers
  31   * (but this driver only supports the host controller)
  32   *
  33   * So setting up a transfer involves:
  34   *    * Allocating a ETD
  35   *    * Fill in ETD with appropriate information
  36   *    * Allocating data memory (and putting the offset in the ETD)
  37   *    * Activate the ETD
  38   *    * Get interrupt when done.
  39   *
  40   * An ETD is assigned to each active endpoint.
  41   *
  42   * Low resource (ETD and Data memory) situations are handled differently for
  43   * isochronous and non insosynchronous transactions :
  44   *
  45   * Non ISOC transfers are queued if either ETDs or Data memory are unavailable
  46   *
  47   * ISOC transfers use 2 ETDs per endpoint to achieve double buffering.
  48   * They allocate both ETDs and Data memory during URB submission
  49   * (and fail if unavailable).
  50   */
  51
  52 #include <linux/clk.h>
  53 #include <linux/io.h>
  54 #include <linux/kernel.h>
  55 #include <linux/list.h>
  56 #include <linux/platform_device.h>
  57 #include <linux/slab.h>
  58 #include <linux/usb.h>
  59 #include <linux/usb/hcd.h>
  60 #include <linux/dma-mapping.h>
  61 #include <linux/module.h>
  62
  63 #include "imx21-hcd.h"
  64
  65 #ifdef DEBUG
  66 #define DEBUG_LOG_FRAME(imx21, etd, event) \
  67         (etd)->event##_frame = readl((imx21)->regs + USBH_FRMNUB)
  68 #else
  69 #define DEBUG_LOG_FRAME(imx21, etd, event) do { } while (0)
  70 #endif
  71
  72 static const char hcd_name[] = "imx21-hcd";
  73
  74 static inline struct imx21 *hcd_to_imx21(struct usb_hcd *hcd)
  75 {
  76         return (struct imx21 *)hcd->hcd_priv;
  77 }
  78
  79
  80 /* =========================================== */
  81 /* Hardware access helpers                      */
  82 /* =========================================== */
  83
  84 static inline void set_register_bits(struct imx21 *imx21, u32 offset, u32 mask)
  85 {
  86         void __iomem *reg = imx21->regs + offset;
  87         writel(readl(reg) | mask, reg);
  88 }
  89
  90 static inline void clear_register_bits(struct imx21 *imx21,
  91         u32 offset, u32 mask)
  92 {
  93         void __iomem *reg = imx21->regs + offset;
  94         writel(readl(reg) & ~mask, reg);
  95 }
  96
  97 static inline void clear_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
  98 {
  99         void __iomem *reg = imx21->regs + offset;
 100
 101         if (readl(reg) & mask)
 102                 writel(mask, reg);
 103 }
 104
 105 static inline void set_toggle_bit(struct imx21 *imx21, u32 offset, u32 mask)
 106 {
 107         void __iomem *reg = imx21->regs + offset;
 108
 109         if (!(readl(reg) & mask))
 110                 writel(mask, reg);
 111 }
 112
 113 static void etd_writel(struct imx21 *imx21, int etd_num, int dword, u32 value)
 114 {
 115         writel(value, imx21->regs + USB_ETD_DWORD(etd_num, dword));
 116 }
 117
 118 static u32 etd_readl(struct imx21 *imx21, int etd_num, int dword)
 119 {
 120         return readl(imx21->regs + USB_ETD_DWORD(etd_num, dword));
 121 }
 122
 123 static inline int wrap_frame(int counter)
 124 {
 125         return counter & 0xFFFF;
 126 }
 127
 128 static inline int frame_after(int frame, int after)
 129 {
 130         /* handle wrapping like jiffies time_afer */
 131         return (s16)((s16)after - (s16)frame) < 0;
 132 }
 133
 134 static int imx21_hc_get_frame(struct usb_hcd *hcd)
 135 {
 136         struct imx21 *imx21 = hcd_to_imx21(hcd);
 137
 138         return wrap_frame(readl(imx21->regs + USBH_FRMNUB));
 139 }
 140
 141 static inline bool unsuitable_for_dma(dma_addr_t addr)
 142 {
 143         return (addr & 3) != 0;
 144 }
 145
 146 #include "imx21-dbg.c"
 147
 148 static void nonisoc_urb_completed_for_etd(
 149         struct imx21 *imx21, struct etd_priv *etd, int status);
 150 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb);
 151 static void free_dmem(struct imx21 *imx21, struct etd_priv *etd);
 152
 153 /* =========================================== */
 154 /* ETD management                               */
 155 /* ===========================================  */
 156
 157 static int alloc_etd(struct imx21 *imx21)
 158 {
 159         int i;
 160         struct etd_priv *etd = imx21->etd;
 161
 162         for (i = 0; i < USB_NUM_ETD; i++, etd++) {
 163                 if (etd->alloc == 0) {
 164                         memset(etd, 0, sizeof(imx21->etd[0]));
 165                         etd->alloc = 1;
 166                         debug_etd_allocated(imx21);
 167                         return i;
 168                 }
 169         }
 170         return -1;
 171 }
 172
 173 static void disactivate_etd(struct imx21 *imx21, int num)
 174 {
 175         int etd_mask = (1 << num);
 176         struct etd_priv *etd = &imx21->etd[num];
 177
 178         writel(etd_mask, imx21->regs + USBH_ETDENCLR);
 179         clear_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
 180         writel(etd_mask, imx21->regs + USB_ETDDMACHANLCLR);
 181         clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
 182
 183         etd->active_count = 0;
 184
 185         DEBUG_LOG_FRAME(imx21, etd, disactivated);
 186 }
 187
 188 static void reset_etd(struct imx21 *imx21, int num)
 189 {
 190         struct etd_priv *etd = imx21->etd + num;
 191         int i;
 192
 193         disactivate_etd(imx21, num);
 194
 195         for (i = 0; i < 4; i++)
 196                 etd_writel(imx21, num, i, 0);
 197         etd->urb = NULL;
 198         etd->ep = NULL;
 199         etd->td = NULL;
 200         etd->bounce_buffer = NULL;
 201 }
 202
 203 static void free_etd(struct imx21 *imx21, int num)
 204 {
 205         if (num < 0)
 206                 return;
 207
 208         if (num >= USB_NUM_ETD) {
 209                 dev_err(imx21->dev, "BAD etd=%d!\n", num);
 210                 return;
 211         }
 212         if (imx21->etd[num].alloc == 0) {
 213                 dev_err(imx21->dev, "ETD %d already free!\n", num);
 214                 return;
 215         }
 216
 217         debug_etd_freed(imx21);
 218         reset_etd(imx21, num);
 219         memset(&imx21->etd[num], 0, sizeof(imx21->etd[0]));
 220 }
 221
 222
 223 static void setup_etd_dword0(struct imx21 *imx21,
 224         int etd_num, struct urb *urb,  u8 dir, u16 maxpacket)
 225 {
 226         etd_writel(imx21, etd_num, 0,
 227                 ((u32) usb_pipedevice(urb->pipe)) <<  DW0_ADDRESS |
 228                 ((u32) usb_pipeendpoint(urb->pipe) << DW0_ENDPNT) |
 229                 ((u32) dir << DW0_DIRECT) |
 230                 ((u32) ((urb->dev->speed == USB_SPEED_LOW) ?
 231                         1 : 0) << DW0_SPEED) |
 232                 ((u32) fmt_urb_to_etd[usb_pipetype(urb->pipe)] << DW0_FORMAT) |
 233                 ((u32) maxpacket << DW0_MAXPKTSIZ));
 234 }
 235
 236 /**
 237  * Copy buffer to data controller data memory.
 238  * We cannot use memcpy_toio() because the hardware requires 32bit writes
 239  */
 240 static void copy_to_dmem(
 241         struct imx21 *imx21, int dmem_offset, void *src, int count)
 242 {
 243         void __iomem *dmem = imx21->regs + USBOTG_DMEM + dmem_offset;
 244         u32 word = 0;
 245         u8 *p = src;
 246         int byte = 0;
 247         int i;
 248
 249         for (i = 0; i < count; i++) {
 250                 byte = i % 4;
 251                 word += (*p++ << (byte * 8));
 252                 if (byte == 3) {
 253                         writel(word, dmem);
 254                         dmem += 4;
 255                         word = 0;
 256                 }
 257         }
 258
 259         if (count && byte != 3)
 260                 writel(word, dmem);
 261 }
 262
 263 static void activate_etd(struct imx21 *imx21, int etd_num, u8 dir)
 264 {
 265         u32 etd_mask = 1 << etd_num;
 266         struct etd_priv *etd = &imx21->etd[etd_num];
 267
 268         if (etd->dma_handle && unsuitable_for_dma(etd->dma_handle)) {
 269                 /* For non aligned isoc the condition below is always true */
 270                 if (etd->len <= etd->dmem_size) {
 271                         /* Fits into data memory, use PIO */
 272                         if (dir != TD_DIR_IN) {
 273                                 copy_to_dmem(imx21,
 274                                                 etd->dmem_offset,
 275                                                 etd->cpu_buffer, etd->len);
 276                         }
 277                         etd->dma_handle = 0;
 278
 279                 } else {
 280                         /* Too big for data memory, use bounce buffer */
 281                         enum dma_data_direction dmadir;
 282
 283                         if (dir == TD_DIR_IN) {
 284                                 dmadir = DMA_FROM_DEVICE;
 285                                 etd->bounce_buffer = kmalloc(etd->len,
 286                                                                 GFP_ATOMIC);
 287                         } else {
 288                                 dmadir = DMA_TO_DEVICE;
 289                                 etd->bounce_buffer = kmemdup(etd->cpu_buffer,
 290                                                                 etd->len,
 291                                                                 GFP_ATOMIC);
 292                         }
 293                         if (!etd->bounce_buffer) {
 294                                 dev_err(imx21->dev, "failed bounce alloc\n");
 295                                 goto err_bounce_alloc;
 296                         }
 297
 298                         etd->dma_handle =
 299                                 dma_map_single(imx21->dev,
 300                                                 etd->bounce_buffer,
 301                                                 etd->len,
 302                                                 dmadir);
 303                         if (dma_mapping_error(imx21->dev, etd->dma_handle)) {
 304                                 dev_err(imx21->dev, "failed bounce map\n");
 305                                 goto err_bounce_map;
 306                         }
 307                 }
 308         }
 309
 310         clear_toggle_bit(imx21, USBH_ETDDONESTAT, etd_mask);
 311         set_register_bits(imx21, USBH_ETDDONEEN, etd_mask);
 312         clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
 313         clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
 314
 315         if (etd->dma_handle) {
 316                 set_register_bits(imx21, USB_ETDDMACHANLCLR, etd_mask);
 317                 clear_toggle_bit(imx21, USBH_XBUFSTAT, etd_mask);
 318                 clear_toggle_bit(imx21, USBH_YBUFSTAT, etd_mask);
 319                 writel(etd->dma_handle, imx21->regs + USB_ETDSMSA(etd_num));
 320                 set_register_bits(imx21, USB_ETDDMAEN, etd_mask);
 321         } else {
 322                 if (dir != TD_DIR_IN) {
 323                         /* need to set for ZLP and PIO */
 324                         set_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
 325                         set_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
 326                 }
 327         }
 328
 329         DEBUG_LOG_FRAME(imx21, etd, activated);
 330
 331 #ifdef DEBUG
 332         if (!etd->active_count) {
 333                 int i;
 334                 etd->activated_frame = readl(imx21->regs + USBH_FRMNUB);
 335                 etd->disactivated_frame = -1;
 336                 etd->last_int_frame = -1;
 337                 etd->last_req_frame = -1;
 338
 339                 for (i = 0; i < 4; i++)
 340                         etd->submitted_dwords[i] = etd_readl(imx21, etd_num, i);
 341         }
 342 #endif
 343
 344         etd->active_count = 1;
 345         writel(etd_mask, imx21->regs + USBH_ETDENSET);
 346         return;
 347
 348 err_bounce_map:
 349         kfree(etd->bounce_buffer);
 350
 351 err_bounce_alloc:
 352         free_dmem(imx21, etd);
 353         nonisoc_urb_completed_for_etd(imx21, etd, -ENOMEM);
 354 }
 355
 356 /* ===========================================  */
 357 /* Data memory management                       */
 358 /* ===========================================  */
 359
 360 static int alloc_dmem(struct imx21 *imx21, unsigned int size,
 361                       struct usb_host_endpoint *ep)
 362 {
 363         unsigned int offset = 0;
 364         struct imx21_dmem_area *area;
 365         struct imx21_dmem_area *tmp;
 366
 367         size += (~size + 1) & 0x3; /* Round to 4 byte multiple */
 368
 369         if (size > DMEM_SIZE) {
 370                 dev_err(imx21->dev, "size=%d > DMEM_SIZE(%d)\n",
 371                         size, DMEM_SIZE);
 372                 return -EINVAL;
 373         }
 374
 375         list_for_each_entry(tmp, &imx21->dmem_list, list) {
 376                 if ((size + offset) < offset)
 377                         goto fail;
 378                 if ((size + offset) <= tmp->offset)
 379                         break;
 380                 offset = tmp->size + tmp->offset;
 381                 if ((offset + size) > DMEM_SIZE)
 382                         goto fail;
 383         }
 384
 385         area = kmalloc(sizeof(struct imx21_dmem_area), GFP_ATOMIC);
 386         if (area == NULL)
 387                 return -ENOMEM;
 388
 389         area->ep = ep;
 390         area->offset = offset;
 391         area->size = size;
 392         list_add_tail(&area->list, &tmp->list);
 393         debug_dmem_allocated(imx21, size);
 394         return offset;
 395
 396 fail:
 397         return -ENOMEM;
 398 }
 399
 400 /* Memory now available for a queued ETD - activate it */
 401 static void activate_queued_etd(struct imx21 *imx21,
 402         struct etd_priv *etd, u32 dmem_offset)
 403 {
 404         struct urb_priv *urb_priv = etd->urb->hcpriv;
 405         int etd_num = etd - &imx21->etd[0];
 406         u32 maxpacket = etd_readl(imx21, etd_num, 1) >> DW1_YBUFSRTAD;
 407         u8 dir = (etd_readl(imx21, etd_num, 2) >> DW2_DIRPID) & 0x03;
 408
 409         dev_dbg(imx21->dev, "activating queued ETD %d now DMEM available\n",
 410                 etd_num);
 411         etd_writel(imx21, etd_num, 1,
 412             ((dmem_offset + maxpacket) << DW1_YBUFSRTAD) | dmem_offset);
 413
 414         etd->dmem_offset = dmem_offset;
 415         urb_priv->active = 1;
 416         activate_etd(imx21, etd_num, dir);
 417 }
 418
 419 static void free_dmem(struct imx21 *imx21, struct etd_priv *etd)
 420 {
 421         struct imx21_dmem_area *area;
 422         struct etd_priv *tmp;
 423         int found = 0;
 424         int offset;
 425
 426         if (!etd->dmem_size)
 427                 return;
 428         etd->dmem_size = 0;
 429
 430         offset = etd->dmem_offset;
 431         list_for_each_entry(area, &imx21->dmem_list, list) {
 432                 if (area->offset == offset) {
 433                         debug_dmem_freed(imx21, area->size);
 434                         list_del(&area->list);
 435                         kfree(area);
 436                         found = 1;
 437                         break;
 438                 }
 439         }
 440
 441         if (!found)  {
 442                 dev_err(imx21->dev,
 443                         "Trying to free unallocated DMEM %d\n", offset);
 444                 return;
 445         }
 446
 447         /* Try again to allocate memory for anything we've queued */
 448         list_for_each_entry_safe(etd, tmp, &imx21->queue_for_dmem, queue) {
 449                 offset = alloc_dmem(imx21, etd->dmem_size, etd->ep);
 450                 if (offset >= 0) {
 451                         list_del(&etd->queue);
 452                         activate_queued_etd(imx21, etd, (u32)offset);
 453                 }
 454         }
 455 }
 456
 457 static void free_epdmem(struct imx21 *imx21, struct usb_host_endpoint *ep)
 458 {
 459         struct imx21_dmem_area *area, *tmp;
 460
 461         list_for_each_entry_safe(area, tmp, &imx21->dmem_list, list) {
 462                 if (area->ep == ep) {
 463                         dev_err(imx21->dev,
 464                                 "Active DMEM %d for disabled ep=%p\n",
 465                                 area->offset, ep);
 466                         list_del(&area->list);
 467                         kfree(area);
 468                 }
 469         }
 470 }
 471
 472
 473 /* ===========================================  */
 474 /* End handling                                 */
 475 /* ===========================================  */
 476
 477 /* Endpoint now idle - release its ETD(s) or assign to queued request */
 478 static void ep_idle(struct imx21 *imx21, struct ep_priv *ep_priv)
 479 {
 480         int i;
 481
 482         for (i = 0; i < NUM_ISO_ETDS; i++) {
 483                 int etd_num = ep_priv->etd[i];
 484                 struct etd_priv *etd;
 485                 if (etd_num < 0)
 486                         continue;
 487
 488                 etd = &imx21->etd[etd_num];
 489                 ep_priv->etd[i] = -1;
 490
 491                 free_dmem(imx21, etd); /* for isoc */
 492
 493                 if (list_empty(&imx21->queue_for_etd)) {
 494                         free_etd(imx21, etd_num);
 495                         continue;
 496                 }
 497
 498                 dev_dbg(imx21->dev,
 499                         "assigning idle etd %d for queued request\n", etd_num);
 500                 ep_priv = list_first_entry(&imx21->queue_for_etd,
 501                         struct ep_priv, queue);
 502                 list_del(&ep_priv->queue);
 503                 reset_etd(imx21, etd_num);
 504                 ep_priv->waiting_etd = 0;
 505                 ep_priv->etd[i] = etd_num;
 506
 507                 if (list_empty(&ep_priv->ep->urb_list)) {
 508                         dev_err(imx21->dev, "No urb for queued ep!\n");
 509                         continue;
 510                 }
 511                 schedule_nonisoc_etd(imx21, list_first_entry(
 512                         &ep_priv->ep->urb_list, struct urb, urb_list));
 513         }
 514 }
 515
 516 static void urb_done(struct usb_hcd *hcd, struct urb *urb, int status)
 517 __releases(imx21->lock)
 518 __acquires(imx21->lock)
 519 {
 520         struct imx21 *imx21 = hcd_to_imx21(hcd);
 521         struct ep_priv *ep_priv = urb->ep->hcpriv;
 522         struct urb_priv *urb_priv = urb->hcpriv;
 523
 524         debug_urb_completed(imx21, urb, status);
 525         dev_vdbg(imx21->dev, "urb %p done %d\n", urb, status);
 526
 527         kfree(urb_priv->isoc_td);
 528         kfree(urb->hcpriv);
 529         urb->hcpriv = NULL;
 530         usb_hcd_unlink_urb_from_ep(hcd, urb);
 531         spin_unlock(&imx21->lock);
 532         usb_hcd_giveback_urb(hcd, urb, status);
 533         spin_lock(&imx21->lock);
 534         if (list_empty(&ep_priv->ep->urb_list))
 535                 ep_idle(imx21, ep_priv);
 536 }
 537
 538 static void nonisoc_urb_completed_for_etd(
 539         struct imx21 *imx21, struct etd_priv *etd, int status)
 540 {
 541         struct usb_host_endpoint *ep = etd->ep;
 542
 543         urb_done(imx21->hcd, etd->urb, status);
 544         etd->urb = NULL;
 545
 546         if (!list_empty(&ep->urb_list)) {
 547                 struct urb *urb = list_first_entry(
 548                                         &ep->urb_list, struct urb, urb_list);
 549
 550                 dev_vdbg(imx21->dev, "next URB %p\n", urb);
 551                 schedule_nonisoc_etd(imx21, urb);
 552         }
 553 }
 554
 555
 556 /* ===========================================  */
 557 /* ISOC Handling ...                            */
 558 /* ===========================================  */
 559
 560 static void schedule_isoc_etds(struct usb_hcd *hcd,
 561         struct usb_host_endpoint *ep)
 562 {
 563         struct imx21 *imx21 = hcd_to_imx21(hcd);
 564         struct ep_priv *ep_priv = ep->hcpriv;
 565         struct etd_priv *etd;
 566         struct urb_priv *urb_priv;
 567         struct td *td;
 568         int etd_num;
 569         int i;
 570         int cur_frame;
 571         u8 dir;
 572
 573         for (i = 0; i < NUM_ISO_ETDS; i++) {
 574 too_late:
 575                 if (list_empty(&ep_priv->td_list))
 576                         break;
 577
 578                 etd_num = ep_priv->etd[i];
 579                 if (etd_num < 0)
 580                         break;
 581
 582                 etd = &imx21->etd[etd_num];
 583                 if (etd->urb)
 584                         continue;
 585
 586                 td = list_entry(ep_priv->td_list.next, struct td, list);
 587                 list_del(&td->list);
 588                 urb_priv = td->urb->hcpriv;
 589
 590                 cur_frame = imx21_hc_get_frame(hcd);
 591                 if (frame_after(cur_frame, td->frame)) {
 592                         dev_dbg(imx21->dev, "isoc too late frame %d > %d\n",
 593                                 cur_frame, td->frame);
 594                         urb_priv->isoc_status = -EXDEV;
 595                         td->urb->iso_frame_desc[
 596                                 td->isoc_index].actual_length = 0;
 597                         td->urb->iso_frame_desc[td->isoc_index].status = -EXDEV;
 598                         if (--urb_priv->isoc_remaining == 0)
 599                                 urb_done(hcd, td->urb, urb_priv->isoc_status);
 600                         goto too_late;
 601                 }
 602
 603                 urb_priv->active = 1;
 604                 etd->td = td;
 605                 etd->ep = td->ep;
 606                 etd->urb = td->urb;
 607                 etd->len = td->len;
 608                 etd->dma_handle = td->dma_handle;
 609                 etd->cpu_buffer = td->cpu_buffer;
 610
 611                 debug_isoc_submitted(imx21, cur_frame, td);
 612
 613                 dir = usb_pipeout(td->urb->pipe) ? TD_DIR_OUT : TD_DIR_IN;
 614                 setup_etd_dword0(imx21, etd_num, td->urb, dir, etd->dmem_size);
 615                 etd_writel(imx21, etd_num, 1, etd->dmem_offset);
 616                 etd_writel(imx21, etd_num, 2,
 617                         (TD_NOTACCESSED << DW2_COMPCODE) |
 618                         ((td->frame & 0xFFFF) << DW2_STARTFRM));
 619                 etd_writel(imx21, etd_num, 3,
 620                         (TD_NOTACCESSED << DW3_COMPCODE0) |
 621                         (td->len << DW3_PKTLEN0));
 622
 623                 activate_etd(imx21, etd_num, dir);
 624         }
 625 }
 626
 627 static void isoc_etd_done(struct usb_hcd *hcd, int etd_num)
 628 {
 629         struct imx21 *imx21 = hcd_to_imx21(hcd);
 630         int etd_mask = 1 << etd_num;
 631         struct etd_priv *etd = imx21->etd + etd_num;
 632         struct urb *urb = etd->urb;
 633         struct urb_priv *urb_priv = urb->hcpriv;
 634         struct td *td = etd->td;
 635         struct usb_host_endpoint *ep = etd->ep;
 636         int isoc_index = td->isoc_index;
 637         unsigned int pipe = urb->pipe;
 638         int dir_in = usb_pipein(pipe);
 639         int cc;
 640         int bytes_xfrd;
 641
 642         disactivate_etd(imx21, etd_num);
 643
 644         cc = (etd_readl(imx21, etd_num, 3) >> DW3_COMPCODE0) & 0xf;
 645         bytes_xfrd = etd_readl(imx21, etd_num, 3) & 0x3ff;
 646
 647         /* Input doesn't always fill the buffer, don't generate an error
 648          * when this happens.
 649          */
 650         if (dir_in && (cc == TD_DATAUNDERRUN))
 651                 cc = TD_CC_NOERROR;
 652
 653         if (cc == TD_NOTACCESSED)
 654                 bytes_xfrd = 0;
 655
 656         debug_isoc_completed(imx21,
 657                 imx21_hc_get_frame(hcd), td, cc, bytes_xfrd);
 658         if (cc) {
 659                 urb_priv->isoc_status = -EXDEV;
 660                 dev_dbg(imx21->dev,
 661                         "bad iso cc=0x%X frame=%d sched frame=%d "
 662                         "cnt=%d len=%d urb=%p etd=%d index=%d\n",
 663                         cc,  imx21_hc_get_frame(hcd), td->frame,
 664                         bytes_xfrd, td->len, urb, etd_num, isoc_index);
 665         }
 666
 667         if (dir_in) {
 668                 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
 669                 if (!etd->dma_handle)
 670                         memcpy_fromio(etd->cpu_buffer,
 671                                 imx21->regs + USBOTG_DMEM + etd->dmem_offset,
 672                                 bytes_xfrd);
 673         }
 674
 675         urb->actual_length += bytes_xfrd;
 676         urb->iso_frame_desc[isoc_index].actual_length = bytes_xfrd;
 677         urb->iso_frame_desc[isoc_index].status = cc_to_error[cc];
 678
 679         etd->td = NULL;
 680         etd->urb = NULL;
 681         etd->ep = NULL;
 682
 683         if (--urb_priv->isoc_remaining == 0)
 684                 urb_done(hcd, urb, urb_priv->isoc_status);
 685
 686         schedule_isoc_etds(hcd, ep);
 687 }
 688
 689 static struct ep_priv *alloc_isoc_ep(
 690         struct imx21 *imx21, struct usb_host_endpoint *ep)
 691 {
 692         struct ep_priv *ep_priv;
 693         int i;
 694
 695         ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
 696         if (!ep_priv)
 697                 return NULL;
 698
 699         for (i = 0; i < NUM_ISO_ETDS; i++)
 700                 ep_priv->etd[i] = -1;
 701
 702         INIT_LIST_HEAD(&ep_priv->td_list);
 703         ep_priv->ep = ep;
 704         ep->hcpriv = ep_priv;
 705         return ep_priv;
 706 }
 707
 708 static int alloc_isoc_etds(struct imx21 *imx21, struct ep_priv *ep_priv)
 709 {
 710         int i, j;
 711         int etd_num;
 712
 713         /* Allocate the ETDs if required */
 714         for (i = 0; i < NUM_ISO_ETDS; i++) {
 715                 if (ep_priv->etd[i] < 0) {
 716                         etd_num = alloc_etd(imx21);
 717                         if (etd_num < 0)
 718                                 goto alloc_etd_failed;
 719
 720                         ep_priv->etd[i] = etd_num;
 721                         imx21->etd[etd_num].ep = ep_priv->ep;
 722                 }
 723         }
 724         return 0;
 725
 726 alloc_etd_failed:
 727         dev_err(imx21->dev, "isoc: Couldn't allocate etd\n");
 728         for (j = 0; j < i; j++) {
 729                 free_etd(imx21, ep_priv->etd[j]);
 730                 ep_priv->etd[j] = -1;
 731         }
 732         return -ENOMEM;
 733 }
 734
 735 static int imx21_hc_urb_enqueue_isoc(struct usb_hcd *hcd,
 736                                      struct usb_host_endpoint *ep,
 737                                      struct urb *urb, gfp_t mem_flags)
 738 {
 739         struct imx21 *imx21 = hcd_to_imx21(hcd);
 740         struct urb_priv *urb_priv;
 741         unsigned long flags;
 742         struct ep_priv *ep_priv;
 743         struct td *td = NULL;
 744         int i;
 745         int ret;
 746         int cur_frame;
 747         u16 maxpacket;
 748
 749         urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
 750         if (urb_priv == NULL)
 751                 return -ENOMEM;
 752
 753         urb_priv->isoc_td = kzalloc(
 754                 sizeof(struct td) * urb->number_of_packets, mem_flags);
 755         if (urb_priv->isoc_td == NULL) {
 756                 ret = -ENOMEM;
 757                 goto alloc_td_failed;
 758         }
 759
 760         spin_lock_irqsave(&imx21->lock, flags);
 761
 762         if (ep->hcpriv == NULL) {
 763                 ep_priv = alloc_isoc_ep(imx21, ep);
 764                 if (ep_priv == NULL) {
 765                         ret = -ENOMEM;
 766                         goto alloc_ep_failed;
 767                 }
 768         } else {
 769                 ep_priv = ep->hcpriv;
 770         }
 771
 772         ret = alloc_isoc_etds(imx21, ep_priv);
 773         if (ret)
 774                 goto alloc_etd_failed;
 775
 776         ret = usb_hcd_link_urb_to_ep(hcd, urb);
 777         if (ret)
 778                 goto link_failed;
 779
 780         urb->status = -EINPROGRESS;
 781         urb->actual_length = 0;
 782         urb->error_count = 0;
 783         urb->hcpriv = urb_priv;
 784         urb_priv->ep = ep;
 785
 786         /* allocate data memory for largest packets if not already done */
 787         maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
 788         for (i = 0; i < NUM_ISO_ETDS; i++) {
 789                 struct etd_priv *etd = &imx21->etd[ep_priv->etd[i]];
 790
 791                 if (etd->dmem_size > 0 && etd->dmem_size < maxpacket) {
 792                         /* not sure if this can really occur.... */
 793                         dev_err(imx21->dev, "increasing isoc buffer %d->%d\n",
 794                                 etd->dmem_size, maxpacket);
 795                         ret = -EMSGSIZE;
 796                         goto alloc_dmem_failed;
 797                 }
 798
 799                 if (etd->dmem_size == 0) {
 800                         etd->dmem_offset = alloc_dmem(imx21, maxpacket, ep);
 801                         if (etd->dmem_offset < 0) {
 802                                 dev_dbg(imx21->dev, "failed alloc isoc dmem\n");
 803                                 ret = -EAGAIN;
 804                                 goto alloc_dmem_failed;
 805                         }
 806                         etd->dmem_size = maxpacket;
 807                 }
 808         }
 809
 810         /* calculate frame */
 811         cur_frame = imx21_hc_get_frame(hcd);
 812         if (urb->transfer_flags & URB_ISO_ASAP) {
 813                 if (list_empty(&ep_priv->td_list))
 814                         urb->start_frame = cur_frame + 5;
 815                 else
 816                         urb->start_frame = list_entry(
 817                                 ep_priv->td_list.prev,
 818                                 struct td, list)->frame + urb->interval;
 819         }
 820         urb->start_frame = wrap_frame(urb->start_frame);
 821         if (frame_after(cur_frame, urb->start_frame)) {
 822                 dev_dbg(imx21->dev,
 823                         "enqueue: adjusting iso start %d (cur=%d) asap=%d\n",
 824                         urb->start_frame, cur_frame,
 825                         (urb->transfer_flags & URB_ISO_ASAP) != 0);
 826                 urb->start_frame = wrap_frame(cur_frame + 1);
 827         }
 828
 829         /* set up transfers */
 830         td = urb_priv->isoc_td;
 831         for (i = 0; i < urb->number_of_packets; i++, td++) {
 832                 unsigned int offset = urb->iso_frame_desc[i].offset;
 833                 td->ep = ep;
 834                 td->urb = urb;
 835                 td->len = urb->iso_frame_desc[i].length;
 836                 td->isoc_index = i;
 837                 td->frame = wrap_frame(urb->start_frame + urb->interval * i);
 838                 td->dma_handle = urb->transfer_dma + offset;
 839                 td->cpu_buffer = urb->transfer_buffer + offset;
 840                 list_add_tail(&td->list, &ep_priv->td_list);
 841         }
 842
 843         urb_priv->isoc_remaining = urb->number_of_packets;
 844         dev_vdbg(imx21->dev, "setup %d packets for iso frame %d->%d\n",
 845                 urb->number_of_packets, urb->start_frame, td->frame);
 846
 847         debug_urb_submitted(imx21, urb);
 848         schedule_isoc_etds(hcd, ep);
 849
 850         spin_unlock_irqrestore(&imx21->lock, flags);
 851         return 0;
 852
 853 alloc_dmem_failed:
 854         usb_hcd_unlink_urb_from_ep(hcd, urb);
 855
 856 link_failed:
 857 alloc_etd_failed:
 858 alloc_ep_failed:
 859         spin_unlock_irqrestore(&imx21->lock, flags);
 860         kfree(urb_priv->isoc_td);
 861
 862 alloc_td_failed:
 863         kfree(urb_priv);
 864         return ret;
 865 }
 866
 867 static void dequeue_isoc_urb(struct imx21 *imx21,
 868         struct urb *urb, struct ep_priv *ep_priv)
 869 {
 870         struct urb_priv *urb_priv = urb->hcpriv;
 871         struct td *td, *tmp;
 872         int i;
 873
 874         if (urb_priv->active) {
 875                 for (i = 0; i < NUM_ISO_ETDS; i++) {
 876                         int etd_num = ep_priv->etd[i];
 877                         if (etd_num != -1 && imx21->etd[etd_num].urb == urb) {
 878                                 struct etd_priv *etd = imx21->etd + etd_num;
 879
 880                                 reset_etd(imx21, etd_num);
 881                                 free_dmem(imx21, etd);
 882                         }
 883                 }
 884         }
 885
 886         list_for_each_entry_safe(td, tmp, &ep_priv->td_list, list) {
 887                 if (td->urb == urb) {
 888                         dev_vdbg(imx21->dev, "removing td %p\n", td);
 889                         list_del(&td->list);
 890                 }
 891         }
 892 }
 893
 894 /* =========================================== */
 895 /* NON ISOC Handling ...                        */
 896 /* =========================================== */
 897
 898 static void schedule_nonisoc_etd(struct imx21 *imx21, struct urb *urb)
 899 {
 900         unsigned int pipe = urb->pipe;
 901         struct urb_priv *urb_priv = urb->hcpriv;
 902         struct ep_priv *ep_priv = urb_priv->ep->hcpriv;
 903         int state = urb_priv->state;
 904         int etd_num = ep_priv->etd[0];
 905         struct etd_priv *etd;
 906         u32 count;
 907         u16 etd_buf_size;
 908         u16 maxpacket;
 909         u8 dir;
 910         u8 bufround;
 911         u8 datatoggle;
 912         u8 interval = 0;
 913         u8 relpolpos = 0;
 914
 915         if (etd_num < 0) {
 916                 dev_err(imx21->dev, "No valid ETD\n");
 917                 return;
 918         }
 919         if (readl(imx21->regs + USBH_ETDENSET) & (1 << etd_num))
 920                 dev_err(imx21->dev, "submitting to active ETD %d\n", etd_num);
 921
 922         etd = &imx21->etd[etd_num];
 923         maxpacket = usb_maxpacket(urb->dev, pipe, usb_pipeout(pipe));
 924         if (!maxpacket)
 925                 maxpacket = 8;
 926
 927         if (usb_pipecontrol(pipe) && (state != US_CTRL_DATA)) {
 928                 if (state == US_CTRL_SETUP) {
 929                         dir = TD_DIR_SETUP;
 930                         if (unsuitable_for_dma(urb->setup_dma))
 931                                 usb_hcd_unmap_urb_setup_for_dma(imx21->hcd,
 932                                         urb);
 933                         etd->dma_handle = urb->setup_dma;
 934                         etd->cpu_buffer = urb->setup_packet;
 935                         bufround = 0;
 936                         count = 8;
 937                         datatoggle = TD_TOGGLE_DATA0;
 938                 } else {        /* US_CTRL_ACK */
 939                         dir = usb_pipeout(pipe) ? TD_DIR_IN : TD_DIR_OUT;
 940                         bufround = 0;
 941                         count = 0;
 942                         datatoggle = TD_TOGGLE_DATA1;
 943                 }
 944         } else {
 945                 dir = usb_pipeout(pipe) ? TD_DIR_OUT : TD_DIR_IN;
 946                 bufround = (dir == TD_DIR_IN) ? 1 : 0;
 947                 if (unsuitable_for_dma(urb->transfer_dma))
 948                         usb_hcd_unmap_urb_for_dma(imx21->hcd, urb);
 949
 950                 etd->dma_handle = urb->transfer_dma;
 951                 etd->cpu_buffer = urb->transfer_buffer;
 952                 if (usb_pipebulk(pipe) && (state == US_BULK0))
 953                         count = 0;
 954                 else
 955                         count = urb->transfer_buffer_length;
 956
 957                 if (usb_pipecontrol(pipe)) {
 958                         datatoggle = TD_TOGGLE_DATA1;
 959                 } else {
 960                         if (usb_gettoggle(
 961                                         urb->dev,
 962                                         usb_pipeendpoint(urb->pipe),
 963                                         usb_pipeout(urb->pipe)))
 964                                 datatoggle = TD_TOGGLE_DATA1;
 965                         else
 966                                 datatoggle = TD_TOGGLE_DATA0;
 967                 }
 968         }
 969
 970         etd->urb = urb;
 971         etd->ep = urb_priv->ep;
 972         etd->len = count;
 973
 974         if (usb_pipeint(pipe)) {
 975                 interval = urb->interval;
 976                 relpolpos = (readl(imx21->regs + USBH_FRMNUB) + 1) & 0xff;
 977         }
 978
 979         /* Write ETD to device memory */
 980         setup_etd_dword0(imx21, etd_num, urb, dir, maxpacket);
 981
 982         etd_writel(imx21, etd_num, 2,
 983                 (u32) interval << DW2_POLINTERV |
 984                 ((u32) relpolpos << DW2_RELPOLPOS) |
 985                 ((u32) dir << DW2_DIRPID) |
 986                 ((u32) bufround << DW2_BUFROUND) |
 987                 ((u32) datatoggle << DW2_DATATOG) |
 988                 ((u32) TD_NOTACCESSED << DW2_COMPCODE));
 989
 990         /* DMA will always transfer buffer size even if TOBYCNT in DWORD3
 991            is smaller. Make sure we don't overrun the buffer!
 992          */
 993         if (count && count < maxpacket)
 994                 etd_buf_size = count;
 995         else
 996                 etd_buf_size = maxpacket;
 997
 998         etd_writel(imx21, etd_num, 3,
 999                 ((u32) (etd_buf_size - 1) << DW3_BUFSIZE) | (u32) count);
1000
1001         if (!count)
1002                 etd->dma_handle = 0;
1003
1004         /* allocate x and y buffer space at once */
1005         etd->dmem_size = (count > maxpacket) ? maxpacket * 2 : maxpacket;
1006         etd->dmem_offset = alloc_dmem(imx21, etd->dmem_size, urb_priv->ep);
1007         if (etd->dmem_offset < 0) {
1008                 /* Setup everything we can in HW and update when we get DMEM */
1009                 etd_writel(imx21, etd_num, 1, (u32)maxpacket << 16);
1010
1011                 dev_dbg(imx21->dev, "Queuing etd %d for DMEM\n", etd_num);
1012                 debug_urb_queued_for_dmem(imx21, urb);
1013                 list_add_tail(&etd->queue, &imx21->queue_for_dmem);
1014                 return;
1015         }
1016
1017         etd_writel(imx21, etd_num, 1,
1018                 (((u32) etd->dmem_offset + (u32) maxpacket) << DW1_YBUFSRTAD) |
1019                 (u32) etd->dmem_offset);
1020
1021         urb_priv->active = 1;
1022
1023         /* enable the ETD to kick off transfer */
1024         dev_vdbg(imx21->dev, "Activating etd %d for %d bytes %s\n",
1025                 etd_num, count, dir != TD_DIR_IN ? "out" : "in");
1026         activate_etd(imx21, etd_num, dir);
1027
1028 }
1029
1030 static void nonisoc_etd_done(struct usb_hcd *hcd, int etd_num)
1031 {
1032         struct imx21 *imx21 = hcd_to_imx21(hcd);
1033         struct etd_priv *etd = &imx21->etd[etd_num];
1034         struct urb *urb = etd->urb;
1035         u32 etd_mask = 1 << etd_num;
1036         struct urb_priv *urb_priv = urb->hcpriv;
1037         int dir;
1038         int cc;
1039         u32 bytes_xfrd;
1040         int etd_done;
1041
1042         disactivate_etd(imx21, etd_num);
1043
1044         dir = (etd_readl(imx21, etd_num, 0) >> DW0_DIRECT) & 0x3;
1045         cc = (etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE) & 0xf;
1046         bytes_xfrd = etd->len - (etd_readl(imx21, etd_num, 3) & 0x1fffff);
1047
1048         /* save toggle carry */
1049         usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1050                       usb_pipeout(urb->pipe),
1051                       (etd_readl(imx21, etd_num, 0) >> DW0_TOGCRY) & 0x1);
1052
1053         if (dir == TD_DIR_IN) {
1054                 clear_toggle_bit(imx21, USBH_XFILLSTAT, etd_mask);
1055                 clear_toggle_bit(imx21, USBH_YFILLSTAT, etd_mask);
1056
1057                 if (etd->bounce_buffer) {
1058                         memcpy(etd->cpu_buffer, etd->bounce_buffer, bytes_xfrd);
1059                         dma_unmap_single(imx21->dev,
1060                                 etd->dma_handle, etd->len, DMA_FROM_DEVICE);
1061                 } else if (!etd->dma_handle && bytes_xfrd) {/* PIO */
1062                         memcpy_fromio(etd->cpu_buffer,
1063                                 imx21->regs + USBOTG_DMEM + etd->dmem_offset,
1064                                 bytes_xfrd);
1065                 }
1066         }
1067
1068         kfree(etd->bounce_buffer);
1069         etd->bounce_buffer = NULL;
1070         free_dmem(imx21, etd);
1071
1072         urb->error_count = 0;
1073         if (!(urb->transfer_flags & URB_SHORT_NOT_OK)
1074                         && (cc == TD_DATAUNDERRUN))
1075                 cc = TD_CC_NOERROR;
1076
1077         if (cc != 0)
1078                 dev_vdbg(imx21->dev, "cc is 0x%x\n", cc);
1079
1080         etd_done = (cc_to_error[cc] != 0);      /* stop if error */
1081
1082         switch (usb_pipetype(urb->pipe)) {
1083         case PIPE_CONTROL:
1084                 switch (urb_priv->state) {
1085                 case US_CTRL_SETUP:
1086                         if (urb->transfer_buffer_length > 0)
1087                                 urb_priv->state = US_CTRL_DATA;
1088                         else
1089                                 urb_priv->state = US_CTRL_ACK;
1090                         break;
1091                 case US_CTRL_DATA:
1092                         urb->actual_length += bytes_xfrd;
1093                         urb_priv->state = US_CTRL_ACK;
1094                         break;
1095                 case US_CTRL_ACK:
1096                         etd_done = 1;
1097                         break;
1098                 default:
1099                         dev_err(imx21->dev,
1100                                 "Invalid pipe state %d\n", urb_priv->state);
1101                         etd_done = 1;
1102                         break;
1103                 }
1104                 break;
1105
1106         case PIPE_BULK:
1107                 urb->actual_length += bytes_xfrd;
1108                 if ((urb_priv->state == US_BULK)
1109                     && (urb->transfer_flags & URB_ZERO_PACKET)
1110                     && urb->transfer_buffer_length > 0
1111                     && ((urb->transfer_buffer_length %
1112                          usb_maxpacket(urb->dev, urb->pipe,
1113                                        usb_pipeout(urb->pipe))) == 0)) {
1114                         /* need a 0-packet */
1115                         urb_priv->state = US_BULK0;
1116                 } else {
1117                         etd_done = 1;
1118                 }
1119                 break;
1120
1121         case PIPE_INTERRUPT:
1122                 urb->actual_length += bytes_xfrd;
1123                 etd_done = 1;
1124                 break;
1125         }
1126
1127         if (etd_done)
1128                 nonisoc_urb_completed_for_etd(imx21, etd, cc_to_error[cc]);
1129         else {
1130                 dev_vdbg(imx21->dev, "next state=%d\n", urb_priv->state);
1131                 schedule_nonisoc_etd(imx21, urb);
1132         }
1133 }
1134
1135
1136 static struct ep_priv *alloc_ep(void)
1137 {
1138         int i;
1139         struct ep_priv *ep_priv;
1140
1141         ep_priv = kzalloc(sizeof(struct ep_priv), GFP_ATOMIC);
1142         if (!ep_priv)
1143                 return NULL;
1144
1145         for (i = 0; i < NUM_ISO_ETDS; ++i)
1146                 ep_priv->etd[i] = -1;
1147
1148         return ep_priv;
1149 }
1150
1151 static int imx21_hc_urb_enqueue(struct usb_hcd *hcd,
1152                                 struct urb *urb, gfp_t mem_flags)
1153 {
1154         struct imx21 *imx21 = hcd_to_imx21(hcd);
1155         struct usb_host_endpoint *ep = urb->ep;
1156         struct urb_priv *urb_priv;
1157         struct ep_priv *ep_priv;
1158         struct etd_priv *etd;
1159         int ret;
1160         unsigned long flags;
1161
1162         dev_vdbg(imx21->dev,
1163                 "enqueue urb=%p ep=%p len=%d "
1164                 "buffer=%p dma=%08X setupBuf=%p setupDma=%08X\n",
1165                 urb, ep,
1166                 urb->transfer_buffer_length,
1167                 urb->transfer_buffer, urb->transfer_dma,
1168                 urb->setup_packet, urb->setup_dma);
1169
1170         if (usb_pipeisoc(urb->pipe))
1171                 return imx21_hc_urb_enqueue_isoc(hcd, ep, urb, mem_flags);
1172
1173         urb_priv = kzalloc(sizeof(struct urb_priv), mem_flags);
1174         if (!urb_priv)
1175                 return -ENOMEM;
1176
1177         spin_lock_irqsave(&imx21->lock, flags);
1178
1179         ep_priv = ep->hcpriv;
1180         if (ep_priv == NULL) {
1181                 ep_priv = alloc_ep();
1182                 if (!ep_priv) {
1183                         ret = -ENOMEM;
1184                         goto failed_alloc_ep;
1185                 }
1186                 ep->hcpriv = ep_priv;
1187                 ep_priv->ep = ep;
1188         }
1189
1190         ret = usb_hcd_link_urb_to_ep(hcd, urb);
1191         if (ret)
1192                 goto failed_link;
1193
1194         urb->status = -EINPROGRESS;
1195         urb->actual_length = 0;
1196         urb->error_count = 0;
1197         urb->hcpriv = urb_priv;
1198         urb_priv->ep = ep;
1199
1200         switch (usb_pipetype(urb->pipe)) {
1201         case PIPE_CONTROL:
1202                 urb_priv->state = US_CTRL_SETUP;
1203                 break;
1204         case PIPE_BULK:
1205                 urb_priv->state = US_BULK;
1206                 break;
1207         }
1208
1209         debug_urb_submitted(imx21, urb);
1210         if (ep_priv->etd[0] < 0) {
1211                 if (ep_priv->waiting_etd) {
1212                         dev_dbg(imx21->dev,
1213                                 "no ETD available already queued %p\n",
1214                                 ep_priv);
1215                         debug_urb_queued_for_etd(imx21, urb);
1216                         goto out;
1217                 }
1218                 ep_priv->etd[0] = alloc_etd(imx21);
1219                 if (ep_priv->etd[0] < 0) {
1220                         dev_dbg(imx21->dev,
1221                                 "no ETD available queueing %p\n", ep_priv);
1222                         debug_urb_queued_for_etd(imx21, urb);
1223                         list_add_tail(&ep_priv->queue, &imx21->queue_for_etd);
1224                         ep_priv->waiting_etd = 1;
1225                         goto out;
1226                 }
1227         }
1228
1229         /* Schedule if no URB already active for this endpoint */
1230         etd = &imx21->etd[ep_priv->etd[0]];
1231         if (etd->urb == NULL) {
1232                 DEBUG_LOG_FRAME(imx21, etd, last_req);
1233                 schedule_nonisoc_etd(imx21, urb);
1234         }
1235
1236 out:
1237         spin_unlock_irqrestore(&imx21->lock, flags);
1238         return 0;
1239
1240 failed_link:
1241 failed_alloc_ep:
1242         spin_unlock_irqrestore(&imx21->lock, flags);
1243         kfree(urb_priv);
1244         return ret;
1245 }
1246
1247 static int imx21_hc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1248                                 int status)
1249 {
1250         struct imx21 *imx21 = hcd_to_imx21(hcd);
1251         unsigned long flags;
1252         struct usb_host_endpoint *ep;
1253         struct ep_priv *ep_priv;
1254         struct urb_priv *urb_priv = urb->hcpriv;
1255         int ret = -EINVAL;
1256
1257         dev_vdbg(imx21->dev, "dequeue urb=%p iso=%d status=%d\n",
1258                 urb, usb_pipeisoc(urb->pipe), status);
1259
1260         spin_lock_irqsave(&imx21->lock, flags);
1261
1262         ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1263         if (ret)
1264                 goto fail;
1265         ep = urb_priv->ep;
1266         ep_priv = ep->hcpriv;
1267
1268         debug_urb_unlinked(imx21, urb);
1269
1270         if (usb_pipeisoc(urb->pipe)) {
1271                 dequeue_isoc_urb(imx21, urb, ep_priv);
1272                 schedule_isoc_etds(hcd, ep);
1273         } else if (urb_priv->active) {
1274                 int etd_num = ep_priv->etd[0];
1275                 if (etd_num != -1) {
1276                         struct etd_priv *etd = &imx21->etd[etd_num];
1277
1278                         disactivate_etd(imx21, etd_num);
1279                         free_dmem(imx21, etd);
1280                         etd->urb = NULL;
1281                         kfree(etd->bounce_buffer);
1282                         etd->bounce_buffer = NULL;
1283                 }
1284         }
1285
1286         urb_done(hcd, urb, status);
1287
1288         spin_unlock_irqrestore(&imx21->lock, flags);
1289         return 0;
1290
1291 fail:
1292         spin_unlock_irqrestore(&imx21->lock, flags);
1293         return ret;
1294 }
1295
1296 /* =========================================== */
1297 /* Interrupt dispatch                           */
1298 /* =========================================== */
1299
1300 static void process_etds(struct usb_hcd *hcd, struct imx21 *imx21, int sof)
1301 {
1302         int etd_num;
1303         int enable_sof_int = 0;
1304         unsigned long flags;
1305
1306         spin_lock_irqsave(&imx21->lock, flags);
1307
1308         for (etd_num = 0; etd_num < USB_NUM_ETD; etd_num++) {
1309                 u32 etd_mask = 1 << etd_num;
1310                 u32 enabled = readl(imx21->regs + USBH_ETDENSET) & etd_mask;
1311                 u32 done = readl(imx21->regs + USBH_ETDDONESTAT) & etd_mask;
1312                 struct etd_priv *etd = &imx21->etd[etd_num];
1313
1314
1315                 if (done) {
1316                         DEBUG_LOG_FRAME(imx21, etd, last_int);
1317                 } else {
1318 /*
1319  * Kludge warning!
1320  *
1321  * When multiple transfers are using the bus we sometimes get into a state
1322  * where the transfer has completed (the CC field of the ETD is != 0x0F),
1323  * the ETD has self disabled but the ETDDONESTAT flag is not set
1324  * (and hence no interrupt occurs).
1325  * This causes the transfer in question to hang.
1326  * The kludge below checks for this condition at each SOF and processes any
1327  * blocked ETDs (after an arbitrary 10 frame wait)
1328  *
1329  * With a single active transfer the usbtest test suite will run for days
1330  * without the kludge.
1331  * With other bus activity (eg mass storage) even just test1 will hang without
1332  * the kludge.
1333  */
1334                         u32 dword0;
1335                         int cc;
1336
1337                         if (etd->active_count && !enabled) /* suspicious... */
1338                                 enable_sof_int = 1;
1339
1340                         if (!sof || enabled || !etd->active_count)
1341                                 continue;
1342
1343                         cc = etd_readl(imx21, etd_num, 2) >> DW2_COMPCODE;
1344                         if (cc == TD_NOTACCESSED)
1345                                 continue;
1346
1347                         if (++etd->active_count < 10)
1348                                 continue;
1349
1350                         dword0 = etd_readl(imx21, etd_num, 0);
1351                         dev_dbg(imx21->dev,
1352                                 "unblock ETD %d dev=0x%X ep=0x%X cc=0x%02X!\n",
1353                                 etd_num, dword0 & 0x7F,
1354                                 (dword0 >> DW0_ENDPNT) & 0x0F,
1355                                 cc);
1356
1357 #ifdef DEBUG
1358                         dev_dbg(imx21->dev,
1359                                 "frame: act=%d disact=%d"
1360                                 " int=%d req=%d cur=%d\n",
1361                                 etd->activated_frame,
1362                                 etd->disactivated_frame,
1363                                 etd->last_int_frame,
1364                                 etd->last_req_frame,
1365                                 readl(imx21->regs + USBH_FRMNUB));
1366                         imx21->debug_unblocks++;
1367 #endif
1368                         etd->active_count = 0;
1369 /* End of kludge */
1370                 }
1371
1372                 if (etd->ep == NULL || etd->urb == NULL) {
1373                         dev_dbg(imx21->dev,
1374                                 "Interrupt for unexpected etd %d"
1375                                 " ep=%p urb=%p\n",
1376                                 etd_num, etd->ep, etd->urb);
1377                         disactivate_etd(imx21, etd_num);
1378                         continue;
1379                 }
1380
1381                 if (usb_pipeisoc(etd->urb->pipe))
1382                         isoc_etd_done(hcd, etd_num);
1383                 else
1384                         nonisoc_etd_done(hcd, etd_num);
1385         }
1386
1387         /* only enable SOF interrupt if it may be needed for the kludge */
1388         if (enable_sof_int)
1389                 set_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1390         else
1391                 clear_register_bits(imx21, USBH_SYSIEN, USBH_SYSIEN_SOFINT);
1392
1393
1394         spin_unlock_irqrestore(&imx21->lock, flags);
1395 }
1396
1397 static irqreturn_t imx21_irq(struct usb_hcd *hcd)
1398 {
1399         struct imx21 *imx21 = hcd_to_imx21(hcd);
1400         u32 ints = readl(imx21->regs + USBH_SYSISR);
1401
1402         if (ints & USBH_SYSIEN_HERRINT)
1403                 dev_dbg(imx21->dev, "Scheduling error\n");
1404
1405         if (ints & USBH_SYSIEN_SORINT)
1406                 dev_dbg(imx21->dev, "Scheduling overrun\n");
1407
1408         if (ints & (USBH_SYSISR_DONEINT | USBH_SYSISR_SOFINT))
1409                 process_etds(hcd, imx21, ints & USBH_SYSISR_SOFINT);
1410
1411         writel(ints, imx21->regs + USBH_SYSISR);
1412         return IRQ_HANDLED;
1413 }
1414
1415 static void imx21_hc_endpoint_disable(struct usb_hcd *hcd,
1416                                       struct usb_host_endpoint *ep)
1417 {
1418         struct imx21 *imx21 = hcd_to_imx21(hcd);
1419         unsigned long flags;
1420         struct ep_priv *ep_priv;
1421         int i;
1422
1423         if (ep == NULL)
1424                 return;
1425
1426         spin_lock_irqsave(&imx21->lock, flags);
1427         ep_priv = ep->hcpriv;
1428         dev_vdbg(imx21->dev, "disable ep=%p, ep->hcpriv=%p\n", ep, ep_priv);
1429
1430         if (!list_empty(&ep->urb_list))
1431                 dev_dbg(imx21->dev, "ep's URB list is not empty\n");
1432
1433         if (ep_priv != NULL) {
1434                 for (i = 0; i < NUM_ISO_ETDS; i++) {
1435                         if (ep_priv->etd[i] > -1)
1436                                 dev_dbg(imx21->dev, "free etd %d for disable\n",
1437                                         ep_priv->etd[i]);
1438
1439                         free_etd(imx21, ep_priv->etd[i]);
1440                 }
1441                 kfree(ep_priv);
1442                 ep->hcpriv = NULL;
1443         }
1444
1445         for (i = 0; i < USB_NUM_ETD; i++) {
1446                 if (imx21->etd[i].alloc && imx21->etd[i].ep == ep) {
1447                         dev_err(imx21->dev,
1448                                 "Active etd %d for disabled ep=%p!\n", i, ep);
1449                         free_etd(imx21, i);
1450                 }
1451         }
1452         free_epdmem(imx21, ep);
1453         spin_unlock_irqrestore(&imx21->lock, flags);
1454 }
1455
1456 /* =========================================== */
1457 /* Hub handling                                 */
1458 /* =========================================== */
1459
1460 static int get_hub_descriptor(struct usb_hcd *hcd,
1461                               struct usb_hub_descriptor *desc)
1462 {
1463         struct imx21 *imx21 = hcd_to_imx21(hcd);
1464         desc->bDescriptorType = 0x29;   /* HUB descriptor */
1465         desc->bHubContrCurrent = 0;
1466
1467         desc->bNbrPorts = readl(imx21->regs + USBH_ROOTHUBA)
1468                 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1469         desc->bDescLength = 9;
1470         desc->bPwrOn2PwrGood = 0;
1471         desc->wHubCharacteristics = (__force __u16) cpu_to_le16(
1472                 0x0002 |        /* No power switching */
1473                 0x0010 |        /* No over current protection */
1474                 0);
1475
1476         desc->u.hs.DeviceRemovable[0] = 1 << 1;
1477         desc->u.hs.DeviceRemovable[1] = ~0;
1478         return 0;
1479 }
1480
1481 static int imx21_hc_hub_status_data(struct usb_hcd *hcd, char *buf)
1482 {
1483         struct imx21 *imx21 = hcd_to_imx21(hcd);
1484         int ports;
1485         int changed = 0;
1486         int i;
1487         unsigned long flags;
1488
1489         spin_lock_irqsave(&imx21->lock, flags);
1490         ports = readl(imx21->regs + USBH_ROOTHUBA)
1491                 & USBH_ROOTHUBA_NDNSTMPRT_MASK;
1492         if (ports > 7) {
1493                 ports = 7;
1494                 dev_err(imx21->dev, "ports %d > 7\n", ports);
1495         }
1496         for (i = 0; i < ports; i++) {
1497                 if (readl(imx21->regs + USBH_PORTSTAT(i)) &
1498                         (USBH_PORTSTAT_CONNECTSC |
1499                         USBH_PORTSTAT_PRTENBLSC |
1500                         USBH_PORTSTAT_PRTSTATSC |
1501                         USBH_PORTSTAT_OVRCURIC |
1502                         USBH_PORTSTAT_PRTRSTSC)) {
1503
1504                         changed = 1;
1505                         buf[0] |= 1 << (i + 1);
1506                 }
1507         }
1508         spin_unlock_irqrestore(&imx21->lock, flags);
1509
1510         if (changed)
1511                 dev_info(imx21->dev, "Hub status changed\n");
1512         return changed;
1513 }
1514
1515 static int imx21_hc_hub_control(struct usb_hcd *hcd,
1516                                 u16 typeReq,
1517                                 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1518 {
1519         struct imx21 *imx21 = hcd_to_imx21(hcd);
1520         int rc = 0;
1521         u32 status_write = 0;
1522
1523         switch (typeReq) {
1524         case ClearHubFeature:
1525                 dev_dbg(imx21->dev, "ClearHubFeature\n");
1526                 switch (wValue) {
1527                 case C_HUB_OVER_CURRENT:
1528                         dev_dbg(imx21->dev, "    OVER_CURRENT\n");
1529                         break;
1530                 case C_HUB_LOCAL_POWER:
1531                         dev_dbg(imx21->dev, "    LOCAL_POWER\n");
1532                         break;
1533                 default:
1534                         dev_dbg(imx21->dev, "    unknown\n");
1535                         rc = -EINVAL;
1536                         break;
1537                 }
1538                 break;
1539
1540         case ClearPortFeature:
1541                 dev_dbg(imx21->dev, "ClearPortFeature\n");
1542                 switch (wValue) {
1543                 case USB_PORT_FEAT_ENABLE:
1544                         dev_dbg(imx21->dev, "    ENABLE\n");
1545                         status_write = USBH_PORTSTAT_CURCONST;
1546                         break;
1547                 case USB_PORT_FEAT_SUSPEND:
1548                         dev_dbg(imx21->dev, "    SUSPEND\n");
1549                         status_write = USBH_PORTSTAT_PRTOVRCURI;
1550                         break;
1551                 case USB_PORT_FEAT_POWER:
1552                         dev_dbg(imx21->dev, "    POWER\n");
1553                         status_write = USBH_PORTSTAT_LSDEVCON;
1554                         break;
1555                 case USB_PORT_FEAT_C_ENABLE:
1556                         dev_dbg(imx21->dev, "    C_ENABLE\n");
1557                         status_write = USBH_PORTSTAT_PRTENBLSC;
1558                         break;
1559                 case USB_PORT_FEAT_C_SUSPEND:
1560                         dev_dbg(imx21->dev, "    C_SUSPEND\n");
1561                         status_write = USBH_PORTSTAT_PRTSTATSC;
1562                         break;
1563                 case USB_PORT_FEAT_C_CONNECTION:
1564                         dev_dbg(imx21->dev, "    C_CONNECTION\n");
1565                         status_write = USBH_PORTSTAT_CONNECTSC;
1566                         break;
1567                 case USB_PORT_FEAT_C_OVER_CURRENT:
1568                         dev_dbg(imx21->dev, "    C_OVER_CURRENT\n");
1569                         status_write = USBH_PORTSTAT_OVRCURIC;
1570                         break;
1571                 case USB_PORT_FEAT_C_RESET:
1572                         dev_dbg(imx21->dev, "    C_RESET\n");
1573                         status_write = USBH_PORTSTAT_PRTRSTSC;
1574                         break;
1575                 default:
1576                         dev_dbg(imx21->dev, "    unknown\n");
1577                         rc = -EINVAL;
1578                         break;
1579                 }
1580
1581                 break;
1582
1583         case GetHubDescriptor:
1584                 dev_dbg(imx21->dev, "GetHubDescriptor\n");
1585                 rc = get_hub_descriptor(hcd, (void *)buf);
1586                 break;
1587
1588         case GetHubStatus:
1589                 dev_dbg(imx21->dev, "  GetHubStatus\n");
1590                 *(__le32 *) buf = 0;
1591                 break;
1592
1593         case GetPortStatus:
1594                 dev_dbg(imx21->dev, "GetPortStatus: port: %d, 0x%x\n",
1595                     wIndex, USBH_PORTSTAT(wIndex - 1));
1596                 *(__le32 *) buf = readl(imx21->regs +
1597                         USBH_PORTSTAT(wIndex - 1));
1598                 break;
1599
1600         case SetHubFeature:
1601                 dev_dbg(imx21->dev, "SetHubFeature\n");
1602                 switch (wValue) {
1603                 case C_HUB_OVER_CURRENT:
1604                         dev_dbg(imx21->dev, "    OVER_CURRENT\n");
1605                         break;
1606
1607                 case C_HUB_LOCAL_POWER:
1608                         dev_dbg(imx21->dev, "    LOCAL_POWER\n");
1609                         break;
1610                 default:
1611                         dev_dbg(imx21->dev, "    unknown\n");
1612                         rc = -EINVAL;
1613                         break;
1614                 }
1615
1616                 break;
1617
1618         case SetPortFeature:
1619                 dev_dbg(imx21->dev, "SetPortFeature\n");
1620                 switch (wValue) {
1621                 case USB_PORT_FEAT_SUSPEND:
1622                         dev_dbg(imx21->dev, "    SUSPEND\n");
1623                         status_write = USBH_PORTSTAT_PRTSUSPST;
1624                         break;
1625                 case USB_PORT_FEAT_POWER:
1626                         dev_dbg(imx21->dev, "    POWER\n");
1627                         status_write = USBH_PORTSTAT_PRTPWRST;
1628                         break;
1629                 case USB_PORT_FEAT_RESET:
1630                         dev_dbg(imx21->dev, "    RESET\n");
1631                         status_write = USBH_PORTSTAT_PRTRSTST;
1632                         break;
1633                 default:
1634                         dev_dbg(imx21->dev, "    unknown\n");
1635                         rc = -EINVAL;
1636                         break;
1637                 }
1638                 break;
1639
1640         default:
1641                 dev_dbg(imx21->dev, "  unknown\n");
1642                 rc = -EINVAL;
1643                 break;
1644         }
1645
1646         if (status_write)
1647                 writel(status_write, imx21->regs + USBH_PORTSTAT(wIndex - 1));
1648         return rc;
1649 }
1650
1651 /* =========================================== */
1652 /* Host controller management                   */
1653 /* =========================================== */
1654
1655 static int imx21_hc_reset(struct usb_hcd *hcd)
1656 {
1657         struct imx21 *imx21 = hcd_to_imx21(hcd);
1658         unsigned long timeout;
1659         unsigned long flags;
1660
1661         spin_lock_irqsave(&imx21->lock, flags);
1662
1663         /* Reset the Host controller modules */
1664         writel(USBOTG_RST_RSTCTRL | USBOTG_RST_RSTRH |
1665                 USBOTG_RST_RSTHSIE | USBOTG_RST_RSTHC,
1666                 imx21->regs + USBOTG_RST_CTRL);
1667
1668         /* Wait for reset to finish */
1669         timeout = jiffies + HZ;
1670         while (readl(imx21->regs + USBOTG_RST_CTRL) != 0) {
1671                 if (time_after(jiffies, timeout)) {
1672                         spin_unlock_irqrestore(&imx21->lock, flags);
1673                         dev_err(imx21->dev, "timeout waiting for reset\n");
1674                         return -ETIMEDOUT;
1675                 }
1676                 spin_unlock_irq(&imx21->lock);
1677                 schedule_timeout_uninterruptible(1);
1678                 spin_lock_irq(&imx21->lock);
1679         }
1680         spin_unlock_irqrestore(&imx21->lock, flags);
1681         return 0;
1682 }
1683
1684 static int imx21_hc_start(struct usb_hcd *hcd)
1685 {
1686         struct imx21 *imx21 = hcd_to_imx21(hcd);
1687         unsigned long flags;
1688         int i, j;
1689         u32 hw_mode = USBOTG_HWMODE_CRECFG_HOST;
1690         u32 usb_control = 0;
1691
1692         hw_mode |= ((imx21->pdata->host_xcvr << USBOTG_HWMODE_HOSTXCVR_SHIFT) &
1693                         USBOTG_HWMODE_HOSTXCVR_MASK);
1694         hw_mode |= ((imx21->pdata->otg_xcvr << USBOTG_HWMODE_OTGXCVR_SHIFT) &
1695                         USBOTG_HWMODE_OTGXCVR_MASK);
1696
1697         if (imx21->pdata->host1_txenoe)
1698                 usb_control |= USBCTRL_HOST1_TXEN_OE;
1699
1700         if (!imx21->pdata->host1_xcverless)
1701                 usb_control |= USBCTRL_HOST1_BYP_TLL;
1702
1703         if (imx21->pdata->otg_ext_xcvr)
1704                 usb_control |= USBCTRL_OTC_RCV_RXDP;
1705
1706
1707         spin_lock_irqsave(&imx21->lock, flags);
1708
1709         writel((USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN),
1710                 imx21->regs + USBOTG_CLK_CTRL);
1711         writel(hw_mode, imx21->regs + USBOTG_HWMODE);
1712         writel(usb_control, imx21->regs + USBCTRL);
1713         writel(USB_MISCCONTROL_SKPRTRY  | USB_MISCCONTROL_ARBMODE,
1714                 imx21->regs + USB_MISCCONTROL);
1715
1716         /* Clear the ETDs */
1717         for (i = 0; i < USB_NUM_ETD; i++)
1718                 for (j = 0; j < 4; j++)
1719                         etd_writel(imx21, i, j, 0);
1720
1721         /* Take the HC out of reset */
1722         writel(USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL | USBH_HOST_CTRL_CTLBLKSR_1,
1723                 imx21->regs + USBH_HOST_CTRL);
1724
1725         /* Enable ports */
1726         if (imx21->pdata->enable_otg_host)
1727                 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1728                         imx21->regs + USBH_PORTSTAT(0));
1729
1730         if (imx21->pdata->enable_host1)
1731                 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1732                         imx21->regs + USBH_PORTSTAT(1));
1733
1734         if (imx21->pdata->enable_host2)
1735                 writel(USBH_PORTSTAT_PRTPWRST | USBH_PORTSTAT_PRTENABST,
1736                         imx21->regs + USBH_PORTSTAT(2));
1737
1738
1739         hcd->state = HC_STATE_RUNNING;
1740
1741         /* Enable host controller interrupts */
1742         set_register_bits(imx21, USBH_SYSIEN,
1743                 USBH_SYSIEN_HERRINT |
1744                 USBH_SYSIEN_DONEINT | USBH_SYSIEN_SORINT);
1745         set_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1746
1747         spin_unlock_irqrestore(&imx21->lock, flags);
1748
1749         return 0;
1750 }
1751
1752 static void imx21_hc_stop(struct usb_hcd *hcd)
1753 {
1754         struct imx21 *imx21 = hcd_to_imx21(hcd);
1755         unsigned long flags;
1756
1757         spin_lock_irqsave(&imx21->lock, flags);
1758
1759         writel(0, imx21->regs + USBH_SYSIEN);
1760         clear_register_bits(imx21, USBOTG_CINT_STEN, USBOTG_HCINT);
1761         clear_register_bits(imx21, USBOTG_CLK_CTRL_HST | USBOTG_CLK_CTRL_MAIN,
1762                                         USBOTG_CLK_CTRL);
1763         spin_unlock_irqrestore(&imx21->lock, flags);
1764 }
1765
1766 /* =========================================== */
1767 /* Driver glue                                  */
1768 /* =========================================== */
1769
1770 static struct hc_driver imx21_hc_driver = {
1771         .description = hcd_name,
1772         .product_desc = "IMX21 USB Host Controller",
1773         .hcd_priv_size = sizeof(struct imx21),
1774
1775         .flags = HCD_USB11,
1776         .irq = imx21_irq,
1777
1778         .reset = imx21_hc_reset,
1779         .start = imx21_hc_start,
1780         .stop = imx21_hc_stop,
1781
1782         /* I/O requests */
1783         .urb_enqueue = imx21_hc_urb_enqueue,
1784         .urb_dequeue = imx21_hc_urb_dequeue,
1785         .endpoint_disable = imx21_hc_endpoint_disable,
1786
1787         /* scheduling support */
1788         .get_frame_number = imx21_hc_get_frame,
1789
1790         /* Root hub support */
1791         .hub_status_data = imx21_hc_hub_status_data,
1792         .hub_control = imx21_hc_hub_control,
1793
1794 };
1795
1796 static struct mx21_usbh_platform_data default_pdata = {
1797         .host_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1798         .otg_xcvr = MX21_USBXCVR_TXDIF_RXDIF,
1799         .enable_host1 = 1,
1800         .enable_host2 = 1,
1801         .enable_otg_host = 1,
1802
1803 };
1804
1805 static int imx21_remove(struct platform_device *pdev)
1806 {
1807         struct usb_hcd *hcd = platform_get_drvdata(pdev);
1808         struct imx21 *imx21 = hcd_to_imx21(hcd);
1809         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1810
1811         remove_debug_files(imx21);
1812         usb_remove_hcd(hcd);
1813
1814         if (res != NULL) {
1815                 clk_disable_unprepare(imx21->clk);
1816                 clk_put(imx21->clk);
1817                 iounmap(imx21->regs);
1818                 release_mem_region(res->start, resource_size(res));
1819         }
1820
1821         kfree(hcd);
1822         return 0;
1823 }
1824
1825
1826 static int imx21_probe(struct platform_device *pdev)
1827 {
1828         struct usb_hcd *hcd;
1829         struct imx21 *imx21;
1830         struct resource *res;
1831         int ret;
1832         int irq;
1833
1834         printk(KERN_INFO "%s\n", imx21_hc_driver.product_desc);
1835
1836         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1837         if (!res)
1838                 return -ENODEV;
1839         irq = platform_get_irq(pdev, 0);
1840         if (irq < 0)
1841                 return -ENXIO;
1842
1843         hcd = usb_create_hcd(&imx21_hc_driver,
1844                 &pdev->dev, dev_name(&pdev->dev));
1845         if (hcd == NULL) {
1846                 dev_err(&pdev->dev, "Cannot create hcd (%s)\n",
1847                     dev_name(&pdev->dev));
1848                 return -ENOMEM;
1849         }
1850
1851         imx21 = hcd_to_imx21(hcd);
1852         imx21->hcd = hcd;
1853         imx21->dev = &pdev->dev;
1854         imx21->pdata = pdev->dev.platform_data;
1855         if (!imx21->pdata)
1856                 imx21->pdata = &default_pdata;
1857
1858         spin_lock_init(&imx21->lock);
1859         INIT_LIST_HEAD(&imx21->dmem_list);
1860         INIT_LIST_HEAD(&imx21->queue_for_etd);
1861         INIT_LIST_HEAD(&imx21->queue_for_dmem);
1862         create_debug_files(imx21);
1863
1864         res = request_mem_region(res->start, resource_size(res), hcd_name);
1865         if (!res) {
1866                 ret = -EBUSY;
1867                 goto failed_request_mem;
1868         }
1869
1870         imx21->regs = ioremap(res->start, resource_size(res));
1871         if (imx21->regs == NULL) {
1872                 dev_err(imx21->dev, "Cannot map registers\n");
1873                 ret = -ENOMEM;
1874                 goto failed_ioremap;
1875         }
1876
1877         /* Enable clocks source */
1878         imx21->clk = clk_get(imx21->dev, NULL);
1879         if (IS_ERR(imx21->clk)) {
1880                 dev_err(imx21->dev, "no clock found\n");
1881                 ret = PTR_ERR(imx21->clk);
1882                 goto failed_clock_get;
1883         }
1884
1885         ret = clk_set_rate(imx21->clk, clk_round_rate(imx21->clk, 48000000));
1886         if (ret)
1887                 goto failed_clock_set;
1888         ret = clk_prepare_enable(imx21->clk);
1889         if (ret)
1890                 goto failed_clock_enable;
1891
1892         dev_info(imx21->dev, "Hardware HC revision: 0x%02X\n",
1893                 (readl(imx21->regs + USBOTG_HWMODE) >> 16) & 0xFF);
1894
1895         ret = usb_add_hcd(hcd, irq, 0);
1896         if (ret != 0) {
1897                 dev_err(imx21->dev, "usb_add_hcd() returned %d\n", ret);
1898                 goto failed_add_hcd;
1899         }
1900
1901         return 0;
1902
1903 failed_add_hcd:
1904         clk_disable_unprepare(imx21->clk);
1905 failed_clock_enable:
1906 failed_clock_set:
1907         clk_put(imx21->clk);
1908 failed_clock_get:
1909         iounmap(imx21->regs);
1910 failed_ioremap:
1911         release_mem_region(res->start, resource_size(res));
1912 failed_request_mem:
1913         remove_debug_files(imx21);
1914         usb_put_hcd(hcd);
1915         return ret;
1916 }
1917
1918 static struct platform_driver imx21_hcd_driver = {
1919         .driver = {
1920                    .name = (char *)hcd_name,
1921                    },
1922         .probe = imx21_probe,
1923         .remove = imx21_remove,
1924         .suspend = NULL,
1925         .resume = NULL,
1926 };
1927
1928 module_platform_driver(imx21_hcd_driver);
1929
1930 MODULE_DESCRIPTION("i.MX21 USB Host controller");
1931 MODULE_AUTHOR("Martin Fuzzey");
1932 MODULE_LICENSE("GPL");
1933 MODULE_ALIAS("platform:imx21-hcd");