ARM: sunxi: dt: Convert to the new SID compatibles

[karo-tx-linux.git] / arch / arm / boot / dts / sun4i-a10.dtsi

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 319cc6b509da8e29ee657730497d87f1215745a8..7b10f85ef988b6797d06fe38b8693640765e1e61 100644 (file)
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -15,6 +15,12 @@
 / {
        interrupt-parent = <&intc>;
 
+       aliases {
+               ethernet0 = &emac;
+               serial0 = &uart0;
+               serial1 = &uart1;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -66,6 +72,29 @@
                        clocks = <&osc24M>;
                };
 
+               pll4: pll4@01c20018 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-pll1-clk";
+                       reg = <0x01c20018 0x4>;
+                       clocks = <&osc24M>;
+               };
+
+               pll5: pll5@01c20020 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll5-clk";
+                       reg = <0x01c20020 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll5_ddr", "pll5_other";
+               };
+
+               pll6: pll6@01c20028 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun4i-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6_sata", "pll6_other", "pll6";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
@@ -131,12 +160,11 @@
                                "apb0_ir1", "apb0_keypad";
                };
 
-               /* dummy is pll62 */
                apb1_mux: apb1_mux@01c20058 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-apb1-mux-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                       clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
                };
 
                apb1: apb1@01c20058 {
@@ -158,6 +186,126 @@
                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
                                "apb1_uart7";
                };
+
+               nand_clk: clk@01c20080 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20080 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "nand";
+               };
+
+               ms_clk: clk@01c20084 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20084 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ms";
+               };
+
+               mmc0_clk: clk@01c20088 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20088 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc0";
+               };
+
+               mmc1_clk: clk@01c2008c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2008c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc1";
+               };
+
+               mmc2_clk: clk@01c20090 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20090 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc2";
+               };
+
+               mmc3_clk: clk@01c20094 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20094 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "mmc3";
+               };
+
+               ts_clk: clk@01c20098 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c20098 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ts";
+               };
+
+               ss_clk: clk@01c2009c {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c2009c 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ss";
+               };
+
+               spi0_clk: clk@01c200a0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a0 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi0";
+               };
+
+               spi1_clk: clk@01c200a4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a4 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi1";
+               };
+
+               spi2_clk: clk@01c200a8 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a8 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi2";
+               };
+
+               pata_clk: clk@01c200ac {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200ac 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "pata";
+               };
+
+               ir0_clk: clk@01c200b0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200b0 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ir0";
+               };
+
+               ir1_clk: clk@01c200b4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200b4 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "ir1";
+               };
+
+               spi3_clk: clk@01c200d4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200d4 0x4>;
+                       clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+                       clock-output-names = "spi3";
+               };
        };
 
        soc@01c00000 {
@@ -266,11 +414,23 @@
                        reg = <0x01c20c90 0x10>;
                };
 
+               rtc: rtc@01c20d00 {
+                       compatible = "allwinner,sun4i-rtc";
+                       reg = <0x01c20d00 0x20>;
+                       interrupts = <24>;
+               };
+
                sid: eeprom@01c23800 {
-                       compatible = "allwinner,sun4i-sid";
+                       compatible = "allwinner,sun4i-a10-sid";
                        reg = <0x01c23800 0x10>;
                };
 
+               rtp: rtp@01c25000 {
+                       compatible = "allwinner,sun4i-ts";
+                       reg = <0x01c25000 0x100>;
+                       interrupts = <29>;
+               };
+
                uart0: serial@01c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;