Merge tag 'omap-pm-v3.10/cleanup/pm' of git://git.kernel.org/pub/scm/linux/kernel...

[karo-tx-linux.git] / arch / arm / mach-omap2 / omap-smp.c

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 5b201653ca32f7dabced0fb34bb459a85404e9bd..98a11463a843afdaca3ef99680e0a7c785d5fc33 100644 (file)
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -65,13 +65,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
                omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
                                                        4, 0, 0, 0, 0, 0);
 
-       /*
-        * If any interrupts are already enabled for the primary
-        * core (e.g. timer irq), then they will not have been enabled
-        * for us: do so
-        */
-       gic_secondary_init(0);
-
        /*
         * Synchronise with the boot thread.
         */
@@ -83,6 +76,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 {
        static struct clockdomain *cpu1_clkdm;
        static bool booted;
+       static struct powerdomain *cpu1_pwrdm;
        void __iomem *base = omap_get_wakeupgen_base();
 
        /*
@@ -102,8 +96,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
        else
                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
-       if (!cpu1_clkdm)
+       if (!cpu1_clkdm && !cpu1_pwrdm) {
                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+               cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
+       }
 
        /*
         * The SGI(Software Generated Interrupts) are not wakeup capable
@@ -116,7 +112,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         * Section :
         *      4.3.4.2 Power States of CPU0 and CPU1
         */
-       if (booted) {
+       if (booted && cpu1_pwrdm && cpu1_clkdm) {
                /*
                 * GIC distributor control register has changed between
                 * CortexA9 r1pX and r2pX. The Control Register secure
@@ -137,7 +133,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
                        gic_dist_disable();
                }
 
+               /*
+                * Ensure that CPU power state is set to ON to avoid CPU
+                * powerdomain transition on wfi
+                */
                clkdm_wakeup(cpu1_clkdm);
+               omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
                clkdm_allow_idle(cpu1_clkdm);
 
                if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
@@ -173,7 +174,7 @@ static void __init omap4_smp_init_cpus(void)
        unsigned int i = 0, ncores = 1, cpu_id;
 
        /* Use ARM cpuid check here, as SoC detection will not work so early */
-       cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+       cpu_id = read_cpuid_id() & CPU_MASK;
        if (cpu_id == CPU_CORTEX_A9) {
                /*
                 * Currently we can't call ioremap here because