Merge remote-tracking branch 'input-current/for-linus'

[karo-tx-linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.h

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
index e45988c4dad556e9b31195f2112de3a44fcb35ab..5abd66c84d005f4d211d20bab2fd42b1a5b2a5c7 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
@@ -66,6 +66,9 @@
 #define IXGBE_SFF_1GBASET_CAPABLE              0x8
 #define IXGBE_SFF_10GBASESR_CAPABLE            0x10
 #define IXGBE_SFF_10GBASELR_CAPABLE            0x20
+#define IXGBE_SFF_SOFT_RS_SELECT_MASK          0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_10G           0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_1G            0x0
 #define IXGBE_SFF_ADDRESSING_MODE              0x4
 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE         0x1
 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE                0x8
@@ -78,9 +81,29 @@
 #define IXGBE_I2C_EEPROM_STATUS_FAIL           0x2
 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS    0x3
 #define IXGBE_CS4227                           0xBE    /* CS4227 address */
-#define IXGBE_CS4227_SPARE24_LSB               0x12B0  /* Reg to program EDC */
+#define IXGBE_CS4227_SCRATCH                   2
+#define IXGBE_CS4227_RESET_PENDING             0x1357
+#define IXGBE_CS4227_RESET_COMPLETE            0x5AA5
+#define IXGBE_CS4227_RETRIES                   15
+#define IXGBE_CS4227_EFUSE_STATUS              0x0181
+#define IXGBE_CS4227_LINE_SPARE22_MSB          0x12AD  /* Reg to set speed */
+#define IXGBE_CS4227_LINE_SPARE24_LSB          0x12B0  /* Reg to set EDC */
+#define IXGBE_CS4227_HOST_SPARE22_MSB          0x1AAD  /* Reg to set speed */
+#define IXGBE_CS4227_HOST_SPARE24_LSB          0x1AB0  /* Reg to program EDC */
+#define IXGBE_CS4227_EEPROM_STATUS             0x5001
+#define IXGBE_CS4227_EEPROM_LOAD_OK            0x0001
+#define IXGBE_CS4227_SPEED_1G                  0x8000
+#define IXGBE_CS4227_SPEED_10G                 0
 #define IXGBE_CS4227_EDC_MODE_CX1              0x0002
 #define IXGBE_CS4227_EDC_MODE_SR               0x0004
+#define IXGBE_CS4227_EDC_MODE_DIAG             0x0008
+#define IXGBE_CS4227_RESET_HOLD                        500     /* microseconds */
+#define IXGBE_CS4227_RESET_DELAY               500     /* milliseconds */
+#define IXGBE_CS4227_CHECK_DELAY               30      /* milliseconds */
+#define IXGBE_PE                               0xE0    /* Port expander addr */
+#define IXGBE_PE_OUTPUT                                1       /* Output reg offset */
+#define IXGBE_PE_CONFIG                                3       /* Config reg offset */
+#define IXGBE_PE_BIT1                          (1 << 1)
 
 /* Flow control defines */
 #define IXGBE_TAF_SYM_PAUSE                  0x400
@@ -109,6 +132,8 @@
 #define IXGBE_I2C_T_SU_STO  4
 #define IXGBE_I2C_T_BUF     5
 
+#define IXGBE_SFP_DETECT_RETRIES       2
+
 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 
@@ -154,8 +179,12 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                u8 dev_addr, u8 *data);
+s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
+                                        u8 dev_addr, u8 *data);
 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                 u8 dev_addr, u8 data);
+s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
+                                         u8 dev_addr, u8 data);
 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                  u8 *eeprom_data);
 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
@@ -164,6 +193,10 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                   u8 eeprom_data);
 s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
                                    u16 reg, u16 *val);
+s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
+                                            u16 reg, u16 *val);
 s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
                                     u16 reg, u16 val);
+s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
+                                             u16 reg, u16 val);
 #endif /* _IXGBE_PHY_H_ */