/*
* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
*/
-
#ifndef _ASM_POWERPC_PPC_ASM_H
#define _ASM_POWERPC_PPC_ASM_H
+#include <linux/stringify.h>
+#include <linux/config.h>
+
#ifdef __ASSEMBLY__
/*
#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
-/* Macros to adjust thread priority for Iseries hardware multithreading */
-#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
-#define HMT_LOW or 1,1,1
-#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
-#define HMT_MEDIUM or 2,2,2
-#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
-#define HMT_HIGH or 3,3,3
+/* Macros to adjust thread priority for hardware multithreading */
+#define HMT_VERY_LOW or 31,31,31 # very low priority
+#define HMT_LOW or 1,1,1
+#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority
+#define HMT_MEDIUM or 2,2,2
+#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority
+#define HMT_HIGH or 3,3,3
/* handle instructions that older assemblers may not know */
#define RFCI .long 0x4c000066 /* rfci instruction */
#define RFDI .long 0x4c00004e /* rfdi instruction */
#define RFMCI .long 0x4c00004c /* rfmci instruction */
+#ifdef CONFIG_PPC64
+
+#define XGLUE(a,b) a##b
+#define GLUE(a,b) XGLUE(a,b)
+
+#define _GLOBAL(name) \
+ .section ".text"; \
+ .align 2 ; \
+ .globl name; \
+ .globl GLUE(.,name); \
+ .section ".opd","aw"; \
+name: \
+ .quad GLUE(.,name); \
+ .quad .TOC.@tocbase; \
+ .quad 0; \
+ .previous; \
+ .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _KPROBE(name) \
+ .section ".kprobes.text","a"; \
+ .align 2 ; \
+ .globl name; \
+ .globl GLUE(.,name); \
+ .section ".opd","aw"; \
+name: \
+ .quad GLUE(.,name); \
+ .quad .TOC.@tocbase; \
+ .quad 0; \
+ .previous; \
+ .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#define _STATIC(name) \
+ .section ".text"; \
+ .align 2 ; \
+ .section ".opd","aw"; \
+name: \
+ .quad GLUE(.,name); \
+ .quad .TOC.@tocbase; \
+ .quad 0; \
+ .previous; \
+ .type GLUE(.,name),@function; \
+GLUE(.,name):
+
+#else /* 32-bit */
+
+#define _GLOBAL(n) \
+ .text; \
+ .stabs __stringify(n:F-1),N_FUN,0,0,n;\
+ .globl n; \
+n:
+
+#define _KPROBE(n) \
+ .section ".kprobes.text","a"; \
+ .globl n; \
+n:
+
+#endif
+
/*
* LOADADDR( rn, name )
* loads the address of 'name' into 'rn'
*
* LOADBASE( rn, name )
- * loads the address (less the low 16 bits) of 'name' into 'rn'
+ * loads the address (possibly without the low 16 bits) of 'name' into 'rn'
* suitable for base+disp addressing
*/
#ifdef __powerpc64__
oris rn,rn,name##@h; \
ori rn,rn,name##@l
-#define LOADBASE(rn,name) \
- lis rn,name@highest; \
- ori rn,rn,name@higher; \
- rldicr rn,rn,32,31; \
- oris rn,rn,name@ha
+#define LOADBASE(rn,name) \
+ ld rn,name@got(r2)
+#define OFF(name) 0
#define SET_REG_TO_CONST(reg, value) \
lis reg,(((value)>>48)&0xFFFF); \
rldicr reg,reg,32,31; \
oris reg,reg,(label)@h; \
ori reg,reg,(label)@l;
+
+/* operations for longs and pointers */
+#define LDL ld
+#define STL std
+#define CMPI cmpdi
+#define SZL 8
+
+/* offsets for stack frame layout */
+#define LRSAVE 16
+
+#else /* 32-bit */
+#define LOADADDR(rn,name) \
+ lis rn,name@ha; \
+ addi rn,rn,name@l
+
+#define LOADBASE(rn,name) \
+ lis rn,name@ha
+
+#define OFF(name) name@l
+
+/* operations for longs and pointers */
+#define LDL lwz
+#define STL stw
+#define CMPI cmpwi
+#define SZL 4
+
+/* offsets for stack frame layout */
+#define LRSAVE 4
+
#endif
/* various errata or part fixups */
#if defined(CONFIG_BOOKE)
+#define toreal(rd)
+#define fromreal(rd)
+
#define tophys(rd,rs) \
addis rd,rs,0
addis rd,rs,0
#elif defined(CONFIG_PPC64)
-/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
- * Then we can easily do this with one asm insn. -Peter
- */
+#define toreal(rd) /* we can access c000... in real mode */
+#define fromreal(rd)
+
#define tophys(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- sub rd,rs,rd
+ clrldi rd,rs,2
#define tovirt(rd,rs) \
- lis rd,((KERNELBASE>>48)&0xFFFF); \
- rldicr rd,rd,32,31; \
- add rd,rs,rd
+ rotldi rd,rs,16; \
+ ori rd,rd,((KERNELBASE>>48)&0xFFFF);\
+ rotldi rd,rd,48
#else
/*
* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
* physical base address of RAM at compile time.
*/
+#define toreal(rd) tophys(rd,rd)
+#define fromreal(rd) tovirt(rd,rd)
+
#define tophys(rd,rs) \
0: addis rd,rs,-KERNELBASE@h; \
.section ".vtop_fixup","aw"; \
.previous
#endif
-/*
- * On 64-bit cpus, we use the rfid instruction instead of rfi, but
- * we then have to make sure we preserve the top 32 bits except for
- * the 64-bit mode bit, which we clear.
- */
-#if defined(CONFIG_PPC64BRIDGE)
-#define FIX_SRR1(ra, rb) \
- mr rb,ra; \
- mfmsr ra; \
- clrldi ra,ra,1; /* turn off 64-bit mode */ \
- rldimi ra,rb,0,32
-#define RFI .long 0x4c000024 /* rfid instruction */
-#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
-#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
-#elif defined(CONFIG_PPC64)
-/* Insert the high 32 bits of the MSR into what will be the new
- MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
- bits. */
-
-#define FIX_SRR1(ra, rb) \
- mr rb,ra; \
- mfmsr ra; \
- rldimi ra,rb,0,32
-
-#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
+#ifdef CONFIG_PPC64
+#define RFI rfid
+#define MTMSRD(r) mtmsrd r
#else
#define FIX_SRR1(ra, rb)
#else
#define __ASM_CONST(x) x##UL
#define ASM_CONST(x) __ASM_CONST(x)
+
+#ifdef CONFIG_PPC64
+#define DATAL ".llong"
+#else
+#define DATAL ".long"
+#endif
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PPC_ASM_H */
projects / karo-tx-linux.git / blobdiff