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ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
authorVineet Gupta <vgupta@synopsys.com>
Fri, 3 Apr 2015 09:37:07 +0000 (12:37 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Thu, 25 Jun 2015 00:30:19 +0000 (06:00 +0530)
commit795f4558562fd5318260d5d8144a2f8612aeda7b
treeb4cb8211acf56f2f8acc7ef1429cee4e667f2834tree | snapshot
parenta5c8b52abe677977883655166796f167ef1e0084commit | diff
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)

L2 cache on ARCHS processors is called SLC (System Level Cache)
For working DMA (in absence of hardware assisted IO Coherency) we need
to manage SLC explicitly when buffers transition between cpu and
controllers.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/include/asm/cache.h diff | blob | history
arch/arc/mm/cache.c diff | blob | history
arch/arc/mm/dma.c diff | blob | history
Linux kernel for KaRo TX COM modules