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ARM: dts: BCM63xx: fix L2 cache properties
authorFlorian Fainelli <f.fainelli@gmail.com>
Wed, 11 Feb 2015 01:33:07 +0000 (17:33 -0800)
committerFlorian Fainelli <f.fainelli@gmail.com>
Mon, 16 Feb 2015 20:48:28 +0000 (12:48 -0800)
commit9df11828d9b5665ddef81e45f83dd5376a8cd620
tree7d47c740185086f20de1a9f0ceccbbac58933f2btree | snapshot
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672commit | diff
ARM: dts: BCM63xx: fix L2 cache properties

The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.

Fixes: 46d4bca0445a0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
arch/arm/boot/dts/bcm63138.dtsi diff | blob | history
Linux kernel for KaRo TX COM modules