Merge remote-tracking branch 'pm/linux-next'
authorStephen Rothwell <sfr@canb.auug.org.au>
Thu, 5 Nov 2015 00:43:41 +0000 (11:43 +1100)
committerStephen Rothwell <sfr@canb.auug.org.au>
Thu, 5 Nov 2015 00:43:44 +0000 (11:43 +1100)
23 files changed:
1  2 
Documentation/kernel-parameters.txt
arch/arm/mach-mediatek/mediatek.c
arch/arm/mach-omap2/timer.c
arch/arm/mach-sunxi/sunxi.c
arch/arm64/include/asm/acpi.h
arch/arm64/include/asm/irq.h
arch/arm64/kernel/acpi.c
drivers/acpi/nfit.c
drivers/acpi/osl.c
drivers/base/power/clock_ops.c
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
drivers/cpufreq/Kconfig.arm
drivers/cpufreq/Makefile
drivers/gpio/gpiolib-acpi.c
drivers/gpio/gpiolib.c
drivers/gpio/gpiolib.h
drivers/irqchip/irq-gic.c
drivers/pci/pci-driver.c
drivers/pci/pci.c
drivers/pci/pci.h
include/linux/acpi.h
include/linux/fwnode.h

Simple merge
   */
  #include <linux/init.h>
  #include <asm/mach/arch.h>
-       clocksource_of_init();
 +#include <linux/of.h>
 +#include <linux/clk-provider.h>
 +#include <linux/clocksource.h>
 +
 +
 +#define GPT6_CON_MT65xx 0x10008060
 +#define GPT_ENABLE      0x31
 +
 +static void __init mediatek_timer_init(void)
 +{
 +      void __iomem *gpt_base;
 +
 +      if (of_machine_is_compatible("mediatek,mt6589") ||
 +          of_machine_is_compatible("mediatek,mt8135") ||
 +          of_machine_is_compatible("mediatek,mt8127")) {
 +              /* turn on GPT6 which ungates arch timer clocks */
 +              gpt_base = ioremap(GPT6_CON_MT65xx, 0x04);
 +
 +              /* enable clock and set to free-run */
 +              writel(GPT_ENABLE, gpt_base);
 +              iounmap(gpt_base);
 +      }
 +
 +      of_clk_init(NULL);
++      clocksource_probe();
 +};
  
  static const char * const mediatek_board_dt_compat[] = {
        "mediatek,mt6589",
@@@ -469,64 -476,7 +469,64 @@@ static void __init omap2_gptimer_clocks
                        clocksource_gpt.name, clksrc.rate);
  }
  
 -#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 +static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 +              const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 +              const char *clksrc_prop, bool gptimer)
 +{
 +      omap_clk_init();
 +      omap_dmtimer_init();
 +      omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
 +
 +      /* Enable the use of clocksource="gp_timer" kernel parameter */
 +      if (use_gptimer_clksrc || gptimer)
 +              omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 +                                              clksrc_prop);
 +      else
 +              omap2_sync32k_clocksource_init();
 +}
 +
 +void __init omap_init_time(void)
 +{
 +      __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 +                      2, "timer_sys_ck", NULL, false);
 +
 +      if (of_have_populated_dt())
-               clocksource_of_init();
++              clocksource_probe();
 +}
 +
 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 +void __init omap3_secure_sync32k_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 +                      2, "timer_sys_ck", NULL, false);
 +}
 +#endif /* CONFIG_ARCH_OMAP3 */
 +
 +#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 +void __init omap3_gptimer_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 +                      1, "timer_sys_ck", "ti,timer-alwon", true);
 +}
 +#endif
 +
 +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||                \
 +      defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
 +static void __init omap4_sync32k_timer_init(void)
 +{
 +      __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 +                      2, "sys_clkin_ck", NULL, false);
 +}
 +
 +void __init omap4_local_timer_init(void)
 +{
 +      omap4_sync32k_timer_init();
-       clocksource_of_init();
++      clocksource_probe();
 +}
 +#endif
 +
 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 +
  /*
   * The realtime counter also called master counter, is a free-running
   * counter, which is related to real time. It produces the count used
Simple merge
Simple merge
@@@ -7,17 -5,7 +5,6 @@@
  
  struct pt_regs;
  
 -extern void migrate_irqs(void);
  extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
  
- static inline void acpi_irq_init(void)
- {
-       /*
-        * Hardcode ACPI IRQ chip initialization to GICv2 for now.
-        * Proper irqchip infrastructure will be implemented along with
-        * incoming  GICv2m|GICv3|ITS bits.
-        */
-       acpi_gic_init();
- }
- #define acpi_irq_init acpi_irq_init
  #endif
@@@ -210,52 -205,3 +210,27 @@@ void __init acpi_boot_table_init(void
                        disable_acpi();
        }
  }
- void __init acpi_gic_init(void)
- {
-       struct acpi_table_header *table;
-       acpi_status status;
-       acpi_size tbl_size;
-       int err;
-       if (acpi_disabled)
-               return;
-       status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size);
-       if (ACPI_FAILURE(status)) {
-               const char *msg = acpi_format_exception(status);
-               pr_err("Failed to get MADT table, %s\n", msg);
-               return;
-       }
-       err = gic_v2_acpi_init(table);
-       if (err)
-               pr_err("Failed to initialize GIC IRQ controller");
-       early_acpi_os_unmap_memory((char *)table, tbl_size);
- }
 +
 +#ifdef CONFIG_ACPI_APEI
 +pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr)
 +{
 +      /*
 +       * According to "Table 8 Map: EFI memory types to AArch64 memory
 +       * types" of UEFI 2.5 section 2.3.6.1, each EFI memory type is
 +       * mapped to a corresponding MAIR attribute encoding.
 +       * The EFI memory attribute advises all possible capabilities
 +       * of a memory region. We use the most efficient capability.
 +       */
 +
 +      u64 attr;
 +
 +      attr = efi_mem_attributes(addr);
 +      if (attr & EFI_MEMORY_WB)
 +              return PAGE_KERNEL;
 +      if (attr & EFI_MEMORY_WT)
 +              return __pgprot(PROT_NORMAL_WT);
 +      if (attr & EFI_MEMORY_WC)
 +              return __pgprot(PROT_NORMAL_NC);
 +      return __pgprot(PROT_DEVICE_nGnRnE);
 +}
 +#endif
Simple merge
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@@@ -1247,26 -1222,38 +1246,39 @@@ gic_acpi_parse_madt_cpu(struct acpi_sub
        return 0;
  }
  
- static int __init
gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
-                               const unsigned long end)
+ /* The things you have to do to just *count* something... */
static int __init acpi_dummy_func(struct acpi_subtable_header *header,
+                                 const unsigned long end)
  {
-       struct acpi_madt_generic_distributor *dist;
+       return 0;
+ }
  
-       dist = (struct acpi_madt_generic_distributor *)header;
+ static bool __init acpi_gic_redist_is_present(void)
+ {
+       return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
+                                    acpi_dummy_func, 0) > 0;
+ }
  
-       if (BAD_MADT_ENTRY(dist, end))
-               return -EINVAL;
+ static bool __init gic_validate_dist(struct acpi_subtable_header *header,
+                                    struct acpi_probe_entry *ape)
+ {
+       struct acpi_madt_generic_distributor *dist;
+       dist = (struct acpi_madt_generic_distributor *)header;
  
-       dist_phy_base = dist->base_address;
-       return 0;
+       return (dist->version == ape->driver_data &&
+               (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
+                !acpi_gic_redist_is_present()));
  }
  
- int __init
- gic_v2_acpi_init(struct acpi_table_header *table)
+ #define ACPI_GICV2_DIST_MEM_SIZE      (SZ_4K)
+ #define ACPI_GIC_CPU_IF_MEM_SIZE      (SZ_8K)
+ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
+                                  const unsigned long end)
  {
+       struct acpi_madt_generic_distributor *dist;
        void __iomem *cpu_base, *dist_base;
 +      struct fwnode_handle *domain_handle;
        int count;
  
        /* Collect CPU base addresses */
                static_key_slow_dec(&supports_deactivate);
  
        /*
 -       * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
 -       * as default IRQ domain to allow for GSI registration and GSI to IRQ
 -       * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
 +       * Initialize GIC instance zero (no multi-GIC support).
         */
 -      __gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
 -      irq_set_default_host(gic_data[0].domain);
 +      domain_handle = irq_domain_alloc_fwnode(dist_base);
 +      if (!domain_handle) {
 +              pr_err("Unable to allocate domain handle\n");
 +              iounmap(cpu_base);
 +              iounmap(dist_base);
 +              return -ENOMEM;
 +      }
 +
 +      __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
  
 -      acpi_irq_model = ACPI_IRQ_MODEL_GIC;
 +      acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
        return 0;
  }
+ IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
+                    gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
+                    gic_v2_acpi_init);
+ IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
+                    gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
+                    gic_v2_acpi_init);
  #endif
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@@@ -16,8 -16,8 +16,9 @@@ enum fwnode_type 
        FWNODE_INVALID = 0,
        FWNODE_OF,
        FWNODE_ACPI,
+       FWNODE_ACPI_DATA,
        FWNODE_PDATA,
 +      FWNODE_IRQCHIP,
  };
  
  struct fwnode_handle {