]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
Merge tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes
authorOlof Johansson <olof@lixom.net>
Tue, 18 Dec 2012 02:40:51 +0000 (18:40 -0800)
committerOlof Johansson <olof@lixom.net>
Tue, 18 Dec 2012 02:40:51 +0000 (18:40 -0800)
From Sascha Hauer:

ARM i.MX fixes for v3.8-rc

This fixes a compile failure on imx_v4_v5_defconfig and a regression
introduced with enabling the MIPI clocks on i.MX51. Also one rather
cosmetic fix for the i.MX27 dts file.

* tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: imx: Move platform-mx2-emma to arch/arm/mach-imx/devices
  ARM i.MX51 clock: Fix regression since enabling MIPI/HSP clocks
  ARM: dts: mx27: Fix the AIPI bus for FEC

arch/arm/boot/dts/imx27-3ds.dts
arch/arm/boot/dts/imx27-phytec-phycore.dts
arch/arm/boot/dts/imx27.dtsi
arch/arm/mach-imx/clk-imx51-imx53.c
arch/arm/mach-imx/devices/platform-mx2-emma.c [moved from arch/arm/plat-mxc/devices/platform-mx2-emma.c with 94% similarity]

index b01c0d745fc58165befe9f7e43cdfebffff5dc11..fa04c7b18bcb8350f47917e969c97d02028b09f0 100644 (file)
        };
 
        soc {
-               aipi@10000000 { /* aipi */
-
+               aipi@10000000 { /* aipi1 */
                        uart1: serial@1000a000 {
                                fsl,uart-has-rtscts;
                                status = "okay";
                        };
+               };
 
-                       fec@1002b000 {
+               aipi@10020000 { /* aipi2 */
+                       ethernet@1002b000 {
                                status = "okay";
                        };
                };
        };
-
 };
index af50469e34b2931306acf88a3d8ea289253388e2..53b0ec0c228eb1b2af2200f4eef0e2f12c26782f 100644 (file)
@@ -21,8 +21,7 @@
        };
 
        soc {
-               aipi@10000000 { /* aipi */
-
+               aipi@10000000 { /* aipi1 */
                        serial@1000a000 {
                                fsl,uart-has-rtscts;
                                status = "okay";
                                status = "okay";
                        };
 
-                       ethernet@1002b000 {
-                               status = "okay";
-                       };
-
                        i2c@1001d000 {
                                clock-frequency = <400000>;
                                status = "okay";
                                };
                        };
                };
+
+               aipi@10020000 { /* aipi2 */
+                       ethernet@1002b000 {
+                               status = "okay";
+                       };
+               };
        };
 
        nor_flash@c0000000 {
index b8d3905915acaf7a296e880cbcfee0023e8b1da3..5a82cb5707a84bcf3bc9cdaca039665e1bf36b08 100644 (file)
@@ -55,7 +55,7 @@
                        compatible = "fsl,aipi-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       reg = <0x10000000 0x10000000>;
+                       reg = <0x10000000 0x20000>;
                        ranges;
 
                        wdog: wdog@10002000 {
                                status = "disabled";
                        };
 
+               };
+
+               aipi@10020000 { /* AIPI2 */
+                       compatible = "fsl,aipi-bus", "simple-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x10020000 0x20000>;
+                       ranges;
+
                        fec: ethernet@1002b000 {
                                compatible = "fsl,imx27-fec";
                                reg = <0x1002b000 0x4000>;
index e8c0473c7568a276078cf8f8e35ad943bf292ad7..579023f59dc1458690c91bf5059706e4dd99c6c6 100644 (file)
@@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                        unsigned long rate_ckih1, unsigned long rate_ckih2)
 {
        int i;
+       u32 val;
        struct device_node *np;
 
        clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
@@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        imx_print_silicon_rev("i.MX51", mx51_revision());
        clk_disable_unprepare(clk[iim_gate]);
 
+       /*
+        * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
+        * longer supported. Set to one for better power saving.
+        *
+        * The effect of not setting these bits is that MIPI clocks can't be
+        * enabled without the IPU clock being enabled aswell.
+        */
+       val = readl(MXC_CCM_CCDR);
+       val |= 1 << 18;
+       writel(val, MXC_CCM_CCDR);
+
+       val = readl(MXC_CCM_CLPCR);
+       val |= 1 << 23;
+       writel(val, MXC_CCM_CLPCR);
+
        return 0;
 }
 
similarity index 94%
rename from arch/arm/plat-mxc/devices/platform-mx2-emma.c
rename to arch/arm/mach-imx/devices/platform-mx2-emma.c
index 508404ddd4ea5c8f2971cebf79abd4b94c6fd5c1..11bd01d402f29019888b4cf3a8ef02ed70b4619c 100644 (file)
@@ -6,8 +6,8 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
+#include "../hardware.h"
+#include "devices-common.h"
 
 #define imx_mx2_emmaprp_data_entry_single(soc)                         \
        {                                                               \