]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
usb: chipidea: add flag CI_HDRC_DUAL_ROLE_NOT_OTG
authorPeter Chen <peter.chen@freescale.com>
Wed, 14 Aug 2013 09:44:08 +0000 (12:44 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 14 Aug 2013 19:37:19 +0000 (12:37 -0700)
Since we need otgsc to know vbus's status at some chipidea
controllers even it is peripheral-only mode. Besides, some
SoCs (eg, AR9331 SoC) don't have otgsc register even
the DCCPARAMS_DC and DCCPARAMS_HC are both 1 at CAP_DCCPARAMS.

We inroduce flag CI_HDRC_DUAL_ROLE_NOT_OTG to indicate if the
controller is dual role, but not supports OTG. If this flag is
not set, we follow the rule that if DCCPARAMS_DC and DCCPARAMS_HC
are both 1 at CAP_DCCPARAMS, then this controller is otg capable.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/chipidea/core.c
include/linux/usb/chipidea.h

index 75afc524b659ae2c8a1d71d7cc091c79aa427176..ab01e18bc2f83b6da027be016ec6df1495fc0fe5 100644 (file)
@@ -426,6 +426,18 @@ static inline void ci_role_destroy(struct ci_hdrc *ci)
        ci_hdrc_host_destroy(ci);
 }
 
+static void ci_get_otg_capable(struct ci_hdrc *ci)
+{
+       if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
+               ci->is_otg = false;
+       else
+               ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
+                               DCCPARAMS_DC | DCCPARAMS_HC)
+                                       == (DCCPARAMS_DC | DCCPARAMS_HC));
+       if (ci->is_otg)
+               dev_dbg(ci->dev, "It is OTG capable controller\n");
+}
+
 static int ci_hdrc_probe(struct platform_device *pdev)
 {
        struct device   *dev = &pdev->dev;
@@ -480,6 +492,8 @@ static int ci_hdrc_probe(struct platform_device *pdev)
                return -ENODEV;
        }
 
+       ci_get_otg_capable(ci);
+
        if (!ci->platdata->phy_mode)
                ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
 
@@ -512,10 +526,22 @@ static int ci_hdrc_probe(struct platform_device *pdev)
        }
 
        if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
-               ci->is_otg = true;
-               /* ID pin needs 1ms debouce time, we delay 2ms for safe */
-               mdelay(2);
-               ci->role = ci_otg_role(ci);
+               if (ci->is_otg) {
+                       /*
+                        * ID pin needs 1ms debouce time,
+                        * we delay 2ms for safe.
+                        */
+                       mdelay(2);
+                       ci->role = ci_otg_role(ci);
+                       ci_hdrc_otg_init(ci);
+               } else {
+                       /*
+                        * If the controller is not OTG capable, but support
+                        * role switch, the defalt role is gadget, and the
+                        * user can switch it through debugfs.
+                        */
+                       ci->role = CI_ROLE_GADGET;
+               }
        } else {
                ci->role = ci->roles[CI_ROLE_HOST]
                        ? CI_ROLE_HOST
@@ -534,9 +560,6 @@ static int ci_hdrc_probe(struct platform_device *pdev)
        if (ret)
                goto stop;
 
-       if (ci->is_otg)
-               ci_hdrc_otg_init(ci);
-
        ret = dbg_create_files(ci);
        if (!ret)
                return 0;
index ce4e1aa071b343dcc653ac6b102f17ba640fbf8f..10a607ce9090f8e40e030b9e5814920bcfce40ed 100644 (file)
@@ -20,6 +20,11 @@ struct ci_hdrc_platform_data {
 #define CI_HDRC_REQUIRE_TRANSCEIVER    BIT(1)
 #define CI_HDRC_PULLUP_ON_VBUS         BIT(2)
 #define CI_HDRC_DISABLE_STREAMING      BIT(3)
+       /*
+        * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
+        * but otg is not supported (no register otgsc).
+        */
+#define CI_HDRC_DUAL_ROLE_NOT_OTG      BIT(4)
        enum usb_dr_mode        dr_mode;
 #define CI_HDRC_CONTROLLER_RESET_EVENT         0
 #define CI_HDRC_CONTROLLER_STOPPED_EVENT       1