]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
arm: kirkwood: add SoC-level Device Tree data for PCIe interfaces
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Wed, 15 May 2013 13:36:56 +0000 (15:36 +0200)
committerJason Cooper <jason@lakedaemon.net>
Mon, 27 May 2013 16:02:11 +0000 (16:02 +0000)
This commit adds Device Tree details to enable the PCIe interfaces on
Kirkwood. The 6281 has one PCIe interface, the 6282 has two PCIe
interfaces.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
arch/arm/boot/dts/kirkwood-6281.dtsi
arch/arm/boot/dts/kirkwood-6282.dtsi
arch/arm/boot/dts/kirkwood.dtsi

index d6c9d65cbaeb5bba44c0f91504bc53c38f82bad8..51376683dbcdd2875b2c77aa7bfa85fd5374980d 100644 (file)
                                marvell,function = "sdio";
                        };
                };
+
+               pcie-controller {
+                       compatible = "marvell,kirkwood-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 9>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 2>;
+                               status = "disabled";
+                       };
+               };
        };
 };
index 23991e45bc55f946609e84cc319c81aeed6d0122..66a751ab5516bd8a72de4738f874e68e275eb788 100644 (file)
                        clocks = <&gate_clk 7>;
                        status = "disabled";
                };
+
+               pcie-controller {
+                       compatible = "marvell,kirkwood-pcie";
+                       status = "disabled";
+                       device_type = "pci";
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       bus-range = <0x00 0xff>;
+
+                       ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                 0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
+                                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                       pcie@1,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                               reg = <0x0800 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 9>;
+                               marvell,pcie-port = <0>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 2>;
+                               status = "disabled";
+                       };
+
+                       pcie@2,0 {
+                               device_type = "pci";
+                               assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                               reg = <0x1000 0 0 0 0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               #interrupt-cells = <1>;
+                               ranges;
+                               interrupt-map-mask = <0 0 0 0>;
+                               interrupt-map = <0 0 0 0 &intc 10>;
+                               marvell,pcie-port = <1>;
+                               marvell,pcie-lane = <0>;
+                               clocks = <&gate_clk 18>;
+                               status = "disabled";
+                       };
+               };
        };
 };
index fada7e6d24d8543fd956ef18d7981aa12b9b9ee6..7eef88f00fea9532d91f81648554f97a9cb5f11d 100644 (file)
@@ -19,6 +19,7 @@
        ocp@f1000000 {
                compatible = "simple-bus";
                ranges = <0x00000000 0xf1000000 0x4000000
+                         0xe0000000 0xe0000000 0x8100000 /* PCIE */
                          0xf5000000 0xf5000000 0x0000400>;
                #address-cells = <1>;
                #size-cells = <1>;