Merge remote-tracking branch 'samsung/for-next'
authorStephen Rothwell <sfr@canb.auug.org.au>
Wed, 4 Nov 2015 23:20:17 +0000 (10:20 +1100)
committerStephen Rothwell <sfr@canb.auug.org.au>
Wed, 4 Nov 2015 23:20:17 +0000 (10:20 +1100)
17 files changed:
Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt [new file with mode: 0644]
MAINTAINERS
arch/arm/boot/dts/exynos4.dtsi
arch/arm/boot/dts/exynos5.dtsi
arch/arm/mach-exynos/Kconfig
arch/arm/mach-exynos/exynos.c
arch/arm/mach-exynos/include/mach/map.h
arch/arm/mach-exynos/regs-srom.h [deleted file]
arch/arm/mach-exynos/suspend.c
arch/arm/plat-samsung/include/plat/map-s5p.h
drivers/cpufreq/s5pv210-cpufreq.c
drivers/soc/Kconfig
drivers/soc/Makefile
drivers/soc/samsung/Kconfig [new file with mode: 0644]
drivers/soc/samsung/Makefile [new file with mode: 0644]
drivers/soc/samsung/exynos-srom.c [new file with mode: 0644]
drivers/soc/samsung/exynos-srom.h [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
new file mode 100644 (file)
index 0000000..33886d5
--- /dev/null
@@ -0,0 +1,12 @@
+SAMSUNG Exynos SoCs SROM Controller driver.
+
+Required properties:
+- compatible : Should contain "samsung,exynos-srom".
+
+- reg: offset and length of the register set
+
+Example:
+       sromc@12570000 {
+               compatible = "samsung,exynos-srom";
+               reg = <0x12570000 0x10>;
+       };
index 0a2f094..b15c48f 100644 (file)
@@ -1458,6 +1458,7 @@ F:        arch/arm/mach-exynos*/
 F:     drivers/*/*s3c2410*
 F:     drivers/*/*/*s3c2410*
 F:     drivers/spi/spi-s3c*
+F:     drivers/soc/samsung/*
 F:     sound/soc/samsung/*
 F:     Documentation/arm/Samsung/
 F:     Documentation/devicetree/bindings/arm/samsung/
index 3184e10..2f31f77 100644 (file)
                reg = <0x10000000 0x100>;
        };
 
+       sromc@12570000 {
+               compatible = "samsung,exynos-srom";
+               reg = <0x12570000 0x10>;
+       };
+
        mipi_phy: video-phy@10020710 {
                compatible = "samsung,s5pv210-mipi-video-phy";
                #phy-cells = <1>;
index 110dbd4..b5d3437 100644 (file)
                reg = <0x10000000 0x100>;
        };
 
+       sromc@12250000 {
+               compatible = "samsung,exynos-srom";
+               reg = <0x12250000 0x10>;
+       };
+
        combiner: interrupt-controller@10440000 {
                compatible = "samsung,exynos4210-combiner";
                #interrupt-cells = <2>;
index 3a10f1a..83c85f5 100644 (file)
@@ -16,6 +16,7 @@ menuconfig ARCH_EXYNOS
        select ARM_GIC
        select COMMON_CLK_SAMSUNG
        select EXYNOS_THERMAL
+       select EXYNOS_SROM if PM
        select HAVE_ARM_SCU if SMP
        select HAVE_S3C2410_I2C if I2C
        select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -24,6 +25,7 @@ menuconfig ARCH_EXYNOS
        select PINCTRL_EXYNOS
        select PM_GENERIC_DOMAINS if PM
        select S5P_DEV_MFC
+       select SOC_SAMSUNG
        select SRAM
        select THERMAL
        select MFD_SYSCON
index 1c47aee..4ffb90e 100644 (file)
@@ -37,11 +37,6 @@ void __iomem *pmu_base_addr;
 
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
-               .virtual        = (unsigned long)S5P_VA_SROMC,
-               .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
                .length         = SZ_128K,
@@ -64,20 +59,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
        },
 };
 
-static struct map_desc exynos5_iodesc[] __initdata = {
-       {
-               .virtual        = (unsigned long)S5P_VA_SROMC,
-               .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
-               .length         = SZ_4K,
-               .type           = MT_DEVICE,
-       }, {
-               .virtual        = (unsigned long)S5P_VA_CMU,
-               .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
-               .length         = 144 * SZ_1K,
-               .type           = MT_DEVICE,
-       },
-};
-
 static struct platform_device exynos_cpuidle = {
        .name              = "exynos_cpuidle",
 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -149,9 +130,6 @@ static void __init exynos_map_io(void)
 {
        if (soc_is_exynos4())
                iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-
-       if (soc_is_exynos5())
-               iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
 static void __init exynos_init_io(void)
index de3ae59..351e839 100644 (file)
@@ -25,7 +25,6 @@
 #define EXYNOS_PA_CHIPID               0x10000000
 
 #define EXYNOS4_PA_CMU                 0x10030000
-#define EXYNOS5_PA_CMU                 0x10010000
 
 #define EXYNOS4_PA_DMC0                        0x10400000
 #define EXYNOS4_PA_DMC1                        0x10410000
 #define EXYNOS4_PA_COREPERI            0x10500000
 #define EXYNOS4_PA_L2CC                        0x10502000
 
-#define EXYNOS4_PA_SROMC               0x12570000
-#define EXYNOS5_PA_SROMC               0x12250000
-
-/* Compatibility UART */
-
-#define EXYNOS5440_PA_UART0            0x000B0000
-
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h
deleted file mode 100644 (file)
index 5c4d442..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * S5P SROMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_REGS_SROM_H
-#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_SROMREG(x)         (S5P_VA_SROMC + (x))
-
-#define S5P_SROM_BW            S5P_SROMREG(0x0)
-#define S5P_SROM_BC0           S5P_SROMREG(0x4)
-#define S5P_SROM_BC1           S5P_SROMREG(0x8)
-#define S5P_SROM_BC2           S5P_SROMREG(0xc)
-#define S5P_SROM_BC3           S5P_SROMREG(0x10)
-#define S5P_SROM_BC4           S5P_SROMREG(0x14)
-#define S5P_SROM_BC5           S5P_SROMREG(0x18)
-
-/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
-
-#define S5P_SROM_BW__DATAWIDTH__SHIFT          0
-#define S5P_SROM_BW__ADDRMODE__SHIFT           1
-#define S5P_SROM_BW__WAITENABLE__SHIFT         2
-#define S5P_SROM_BW__BYTEENABLE__SHIFT         3
-
-#define S5P_SROM_BW__CS_MASK                   0xf
-
-#define S5P_SROM_BW__NCS0__SHIFT               0
-#define S5P_SROM_BW__NCS1__SHIFT               4
-#define S5P_SROM_BW__NCS2__SHIFT               8
-#define S5P_SROM_BW__NCS3__SHIFT               12
-#define S5P_SROM_BW__NCS4__SHIFT               16
-#define S5P_SROM_BW__NCS5__SHIFT               20
-
-/* applies to same to BCS0 - BCS3 */
-
-#define S5P_SROM_BCX__PMC__SHIFT               0
-#define S5P_SROM_BCX__TACP__SHIFT              4
-#define S5P_SROM_BCX__TCAH__SHIFT              8
-#define S5P_SROM_BCX__TCOH__SHIFT              12
-#define S5P_SROM_BCX__TACC__SHIFT              16
-#define S5P_SROM_BCX__TCOS__SHIFT              24
-#define S5P_SROM_BCX__TACS__SHIFT              28
-
-#endif /* __PLAT_SAMSUNG_REGS_SROM_H */
index c169cc3..237653e 100644 (file)
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
 
+#include <mach/map.h>
+
 #include <plat/pm-common.h>
 
 #include "common.h"
 #include "exynos-pmu.h"
 #include "regs-pmu.h"
-#include "regs-srom.h"
 
 #define REG_TABLE_END (-1U)
 
@@ -53,15 +54,6 @@ struct exynos_wkup_irq {
        u32 mask;
 };
 
-static struct sleep_save exynos_core_save[] = {
-       /* SROM side */
-       SAVE_ITEM(S5P_SROM_BW),
-       SAVE_ITEM(S5P_SROM_BC0),
-       SAVE_ITEM(S5P_SROM_BC1),
-       SAVE_ITEM(S5P_SROM_BC2),
-       SAVE_ITEM(S5P_SROM_BC3),
-};
-
 struct exynos_pm_data {
        const struct exynos_wkup_irq *wkup_irq;
        unsigned int wake_disable_mask;
@@ -343,8 +335,6 @@ static void exynos_pm_prepare(void)
        /* Set wake-up mask registers */
        exynos_pm_set_wakeup_mask();
 
-       s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-
        exynos_pm_enter_sleep_mode();
 
        /* ensure at least INFORM0 has the resume address */
@@ -375,8 +365,6 @@ static void exynos5420_pm_prepare(void)
        /* Set wake-up mask registers */
        exynos_pm_set_wakeup_mask();
 
-       s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-
        exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
        /*
         * The cpu state needs to be saved and restored so that the
@@ -467,8 +455,6 @@ static void exynos_pm_resume(void)
        /* For release retention */
        exynos_pm_release_retention();
 
-       s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-
        if (cpuid == ARM_CPU_PART_CORTEX_A9)
                scu_enable(S5P_VA_SCU);
 
@@ -535,8 +521,6 @@ static void exynos5420_pm_resume(void)
 
        pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
 
-       s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-
 early_wakeup:
 
        tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
index f5cf2bd..e555769 100644 (file)
@@ -18,7 +18,6 @@
 
 #define S5P_VA_DMC0            S3C_ADDR(0x02440000)
 #define S5P_VA_DMC1            S3C_ADDR(0x02480000)
-#define S5P_VA_SROMC           S3C_ADDR(0x024C0000)
 
 #define S5P_VA_COREPERI_BASE   S3C_ADDR(0x02800000)
 #define S5P_VA_COREPERI(x)     (S5P_VA_COREPERI_BASE + (x))
index 9e231f5..ef5282b 100644 (file)
@@ -576,10 +576,8 @@ static struct cpufreq_driver s5pv210_driver = {
        .get            = cpufreq_generic_get,
        .init           = s5pv210_cpu_init,
        .name           = "s5pv210",
-#ifdef CONFIG_PM
        .suspend        = cpufreq_generic_suspend,
        .resume         = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
-#endif
 };
 
 static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
index 4e853ed..332c19f 100644 (file)
@@ -4,6 +4,7 @@ source "drivers/soc/brcmstb/Kconfig"
 source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
 source "drivers/soc/rockchip/Kconfig"
+source "drivers/soc/samsung/Kconfig"
 source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
index f2ba2e9..7577119 100644 (file)
@@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_BRCMSTB)       += brcmstb/
 obj-$(CONFIG_MACH_DOVE)                += dove/
 obj-$(CONFIG_ARCH_MEDIATEK)    += mediatek/
 obj-$(CONFIG_ARCH_QCOM)                += qcom/
+obj-$(CONFIG_SOC_SAMSUNG)      += samsung/
 obj-$(CONFIG_ARCH_ROCKCHIP)            += rockchip/
 obj-$(CONFIG_ARCH_SUNXI)       += sunxi/
 obj-$(CONFIG_ARCH_TEGRA)       += tegra/
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
new file mode 100644 (file)
index 0000000..2833b5b
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# SAMSUNG SoC drivers
+#
+menu "Samsung SOC driver support"
+
+config SOC_SAMSUNG
+       bool
+
+config EXYNOS_SROM
+       bool
+       depends on ARM && ARCH_EXYNOS && PM
+
+endmenu
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
new file mode 100644 (file)
index 0000000..9c554d5
--- /dev/null
@@ -0,0 +1 @@
+obj-$(CONFIG_EXYNOS_SROM)      += exynos-srom.o
diff --git a/drivers/soc/samsung/exynos-srom.c b/drivers/soc/samsung/exynos-srom.c
new file mode 100644 (file)
index 0000000..57a232d
--- /dev/null
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *           http://www.samsung.com/
+ *
+ * EXYNOS - SROM Controller support
+ * Author: Pankaj Dubey <pankaj.dubey@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "exynos-srom.h"
+
+static const unsigned long exynos_srom_offsets[] = {
+       /* SROM side */
+       EXYNOS_SROM_BW,
+       EXYNOS_SROM_BC0,
+       EXYNOS_SROM_BC1,
+       EXYNOS_SROM_BC2,
+       EXYNOS_SROM_BC3,
+};
+
+/**
+ * struct exynos_srom_reg_dump: register dump of SROM Controller registers.
+ * @offset: srom register offset from the controller base address.
+ * @value: the value of register under the offset.
+ */
+struct exynos_srom_reg_dump {
+       u32     offset;
+       u32     value;
+};
+
+/**
+ * struct exynos_srom: platform data for exynos srom controller driver.
+ * @dev: platform device pointer
+ * @reg_base: srom base address
+ * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
+ */
+struct exynos_srom {
+       struct device *dev;
+       void __iomem *reg_base;
+       struct exynos_srom_reg_dump *reg_offset;
+};
+
+static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump(
+               const unsigned long *rdump,
+               unsigned long nr_rdump)
+{
+       struct exynos_srom_reg_dump *rd;
+       unsigned int i;
+
+       rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
+       if (!rd)
+               return NULL;
+
+       for (i = 0; i < nr_rdump; ++i)
+               rd[i].offset = rdump[i];
+
+       return rd;
+}
+
+static int exynos_srom_probe(struct platform_device *pdev)
+{
+       struct device_node *np;
+       struct exynos_srom *srom;
+       struct device *dev = &pdev->dev;
+
+       np = dev->of_node;
+       if (!np) {
+               dev_err(&pdev->dev, "could not find device info\n");
+               return -EINVAL;
+       }
+
+       srom = devm_kzalloc(&pdev->dev,
+                       sizeof(struct exynos_srom), GFP_KERNEL);
+       if (!srom)
+               return -ENOMEM;
+
+       srom->dev = dev;
+       srom->reg_base = of_iomap(np, 0);
+       if (!srom->reg_base) {
+               dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
+               return -ENOMEM;
+       }
+
+       platform_set_drvdata(pdev, srom);
+
+       srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
+                       sizeof(exynos_srom_offsets));
+       if (!srom->reg_offset) {
+               iounmap(srom->reg_base);
+               return -ENOMEM;
+       }
+
+       return 0;
+}
+
+static int exynos_srom_remove(struct platform_device *pdev)
+{
+       struct exynos_srom *srom = platform_get_drvdata(pdev);
+
+       kfree(srom->reg_offset);
+       iounmap(srom->reg_base);
+
+       return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static void exynos_srom_save(void __iomem *base,
+                                   struct exynos_srom_reg_dump *rd,
+                                   unsigned int num_regs)
+{
+       for (; num_regs > 0; --num_regs, ++rd)
+               rd->value = readl(base + rd->offset);
+}
+
+static void exynos_srom_restore(void __iomem *base,
+                                     const struct exynos_srom_reg_dump *rd,
+                                     unsigned int num_regs)
+{
+       for (; num_regs > 0; --num_regs, ++rd)
+               writel(rd->value, base + rd->offset);
+}
+
+static int exynos_srom_suspend(struct device *dev)
+{
+       struct exynos_srom *srom = dev_get_drvdata(dev);
+
+       exynos_srom_save(srom->reg_base, srom->reg_offset,
+                               ARRAY_SIZE(exynos_srom_offsets));
+       return 0;
+}
+
+static int exynos_srom_resume(struct device *dev)
+{
+       struct exynos_srom *srom = dev_get_drvdata(dev);
+
+       exynos_srom_restore(srom->reg_base, srom->reg_offset,
+                               ARRAY_SIZE(exynos_srom_offsets));
+       return 0;
+}
+#endif
+
+static const struct of_device_id of_exynos_srom_ids[] = {
+       {
+               .compatible     = "samsung,exynos-srom",
+       },
+       {},
+};
+MODULE_DEVICE_TABLE(of, of_exynos_srom_ids);
+
+static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);
+
+static struct platform_driver exynos_srom_driver = {
+       .probe = exynos_srom_probe,
+       .remove = exynos_srom_remove,
+       .driver = {
+               .name = "exynos-srom",
+               .of_match_table = of_exynos_srom_ids,
+               .pm = &exynos_srom_pm_ops,
+       },
+};
+module_platform_driver(exynos_srom_driver);
+
+MODULE_AUTHOR("Pankaj Dubey <pankaj.dubey@samsung.com>");
+MODULE_DESCRIPTION("Exynos SROM Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/samsung/exynos-srom.h b/drivers/soc/samsung/exynos-srom.h
new file mode 100644 (file)
index 0000000..34660c6
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * Exynos SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __EXYNOS_SROM_H
+#define __EXYNOS_SROM_H __FILE__
+
+#define EXYNOS_SROMREG(x)              (x)
+
+#define EXYNOS_SROM_BW         EXYNOS_SROMREG(0x0)
+#define EXYNOS_SROM_BC0                EXYNOS_SROMREG(0x4)
+#define EXYNOS_SROM_BC1                EXYNOS_SROMREG(0x8)
+#define EXYNOS_SROM_BC2                EXYNOS_SROMREG(0xc)
+#define EXYNOS_SROM_BC3                EXYNOS_SROMREG(0x10)
+#define EXYNOS_SROM_BC4                EXYNOS_SROMREG(0x14)
+#define EXYNOS_SROM_BC5                EXYNOS_SROMREG(0x18)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define EXYNOS_SROM_BW__DATAWIDTH__SHIFT       0
+#define EXYNOS_SROM_BW__ADDRMODE__SHIFT                1
+#define EXYNOS_SROM_BW__WAITENABLE__SHIFT      2
+#define EXYNOS_SROM_BW__BYTEENABLE__SHIFT      3
+
+#define EXYNOS_SROM_BW__CS_MASK                        0xf
+
+#define EXYNOS_SROM_BW__NCS0__SHIFT            0
+#define EXYNOS_SROM_BW__NCS1__SHIFT            4
+#define EXYNOS_SROM_BW__NCS2__SHIFT            8
+#define EXYNOS_SROM_BW__NCS3__SHIFT            12
+#define EXYNOS_SROM_BW__NCS4__SHIFT            16
+#define EXYNOS_SROM_BW__NCS5__SHIFT            20
+
+/* applies to same to BCS0 - BCS3 */
+
+#define EXYNOS_SROM_BCX__PMC__SHIFT            0
+#define EXYNOS_SROM_BCX__TACP__SHIFT           4
+#define EXYNOS_SROM_BCX__TCAH__SHIFT           8
+#define EXYNOS_SROM_BCX__TCOH__SHIFT           12
+#define EXYNOS_SROM_BCX__TACC__SHIFT           16
+#define EXYNOS_SROM_BCX__TCOS__SHIFT           24
+#define EXYNOS_SROM_BCX__TACS__SHIFT           28
+
+#endif /* __EXYNOS_SROM_H */