1 //==========================================================================
5 // PowerPC QUICC (MPC8xx) ethernet
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
13 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
44 // -------------------------------------------
46 // Portions of this software may have been derived from OpenBSD or other sources,
47 // and are covered by the appropriate copyright disclaimers included herein.
49 // -------------------------------------------
51 //####BSDCOPYRIGHTEND####
52 //==========================================================================
53 //#####DESCRIPTIONBEGIN####
56 // Contributors: gthomas, nickg
62 //####DESCRIPTIONEND####
64 //==========================================================================
66 // PowerPC QUICC (MPC8xx) Ethernet
68 #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
70 struct quicc_eth_info {
71 volatile struct ethernet_pram *pram; // Parameter RAM pointer
72 volatile struct scc_regs *ctl; // SCC control registers
73 volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use
74 struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor
75 struct cp_bufdesc *tnext, *rnext; // Next descriptor to check for interrupt
76 int txsize, rxsize; // Length of individual buffers
77 int txactive; // Count of active Tx buffers
78 unsigned long txkey[CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM];
80 // Keep some statistics
81 cyg_uint32 interrupts;
84 cyg_uint32 rx_deliver;
85 cyg_uint32 rx_resource;
86 cyg_uint32 rx_restart;
88 cyg_uint32 rx_crc_errors;
89 cyg_uint32 rx_align_errors;
90 cyg_uint32 rx_resource_errors;
91 cyg_uint32 rx_overrun_errors;
92 cyg_uint32 rx_collisions;
93 cyg_uint32 rx_short_frames;
94 cyg_uint32 rx_long_frames;
98 cyg_uint32 tx_complete;
99 cyg_uint32 tx_restart;
101 cyg_uint32 tx_dropped;
102 cyg_uint32 tx_underrun;
103 cyg_uint32 tx_late_collisions;
104 cyg_uint32 tx_carrier_loss;
105 cyg_uint32 tx_retransmit_error;
106 cyg_uint32 tx_heartbeat_loss;
107 cyg_uint32 tx_deferred;
110 // SCC registers - ethernet mode
112 // General SCC mode register
113 #define QUICC_SCC_GSMH_IRP 0x00040000 // Infared polarity
114 #define QUICC_SCC_GSMH_GDE 0x00010000 // Glitch detect enable
115 #define QUICC_SCC_GSMH_TCRC 0x00008000 // Transparent CRC
116 #define QUICC_SCC_GSMH_REVD 0x00004000 // Reverse data (transparent)
117 #define QUICC_SCC_GSMH_TRX 0x00002000 // Transparent Rx
118 #define QUICC_SCC_GSMH_TTX 0x00001000 // Transparent Tx
120 #define QUICC_SCC_GSML_TCI 0x10000000 // Transmit clock invert
121 #define QUICC_SCC_GSML_TPL 0x00E00000 // Tx preamble bits
122 #define QUICC_SCC_GSML_TPL_8 0x00200000 // 8 bits
123 #define QUICC_SCC_GSML_TPL_16 0x00400000 // 16 bits
124 #define QUICC_SCC_GSML_TPL_32 0x00600000 // 32 bits
125 #define QUICC_SCC_GSML_TPL_48 0x00800000 // 48 bits (used for ethernet)
126 #define QUICC_SCC_GSML_TPL_64 0x00A00000 // 64 bits
127 #define QUICC_SCC_GSML_TPL_128 0x00C00000 // 128 bits
128 #define QUICC_SCC_GSML_TPP 0x00180000 // Tx preamble pattern
129 #define QUICC_SCC_GSML_TPP_00 0x00000000 // all zeroes
130 #define QUICC_SCC_GSML_TPP_01 0x00080000 // 10 repeats (ethernet)
131 #define QUICC_SCC_GSML_TPP_10 0x00100000 // 01 repeats
132 #define QUICC_SCC_GSML_TPP_11 0x00180000 // all ones (localtalk)
133 #define QUICC_SCC_GSML_ENR 0x00000020 // Enable receiver
134 #define QUICC_SCC_GSML_ENT 0x00000010 // Enable transmitter
135 #define QUICC_SCC_GSML_MODE 0x0000000F // Operating mode
136 #define QUICC_SCC_GSML_MODE_HDLC 0x00000000
137 #define QUICC_SCC_GSML_MODE_ATALK 0x00000002
138 #define QUICC_SCC_GSML_MODE_ENET 0x0000000C
141 #define QUICC_SCC_FCR_BE 0x0010 // Big Endian operation
144 #define QUICC_SCCE_GRC 0x0080 // Gracefull stop complete
145 #define QUICC_SCCE_TXE 0x0010 // Transmit error
146 #define QUICC_SCCE_RXF 0x0008 // Received full frame
147 #define QUICC_SCCE_BSY 0x0004 // No free receive buffers
148 #define QUICC_SCCE_TX 0x0002 // Buffer transmit complete
149 #define QUICC_SCCE_RX 0x0001 // Buffer received
150 #define QUICC_SCCE_INTS (QUICC_SCCE_TXE | QUICC_SCCE_RXF | QUICC_SCCE_TX)
152 // Protocol specific mode register
153 #define QUICC_PMSR_HEARTBEAT 0x8000 // Enable heartbeat
154 #define QUICC_PMSR_FORCE_COLLISION 0x4000 // Force a collision
155 #define QUICC_PMSR_RCV_SHORT_FRAMES 0x2000 // Accept short frames
156 #define QUICC_PMSR_INDIV_ADDR_MODE 0x1000 // Check individual address (hash)
157 #define QUICC_PMSR_ENET_CRC 0x0800 // Enable ethernet CRC mode
158 #define QUICC_PMSR_PROMISCUOUS 0x0200 // Enable promiscuous mode
159 #define QUICC_PMSR_BROADCAST 0x0100 // Accept broadcast packets
160 #define QUICC_PMSR_SPECIAL_BACKOFF 0x0080 // Enable special backoff timer
161 #define QUICC_PMSR_LOOPBACK 0x0040 // Enable loopback mode
162 #define QUICC_PMSR_SAMPLE_INPUTS 0x0020 // Discretely look at input pins
163 #define QUICC_PMSR_LATE_COLLISION 0x0010 // Enable late collision window
164 #define QUICC_PMSR_SEARCH_AFTER_22 0x000A // Start frame search after 22 bits
165 #define QUICC_PMSR_FULL_DUPLEX 0x0001 // Full duplex mode
167 // Receive buffer status
168 #define QUICC_BD_RX_LAST 0x0800 // Last buffer in chain
169 #define QUICC_BD_RX_FIRST 0x0400 // First buffer in chain
170 #define QUICC_BD_RX_MISS 0x0100 // Missed data
171 #define QUICC_BD_RX_LG 0x0020 // Rx frame too long
172 #define QUICC_BD_RX_NO 0x0010 // Rx frame not properly aligned
173 #define QUICC_BD_RX_SH 0x0008 // Rx frame too short
174 #define QUICC_BD_RX_CR 0x0004 // Bad CRC
175 #define QUICC_BD_RX_OV 0x0002 // Rx overrun
176 #define QUICC_BD_RX_CL 0x0001 // Collision during frame
178 #define QUICC_BD_RX_ERRORS ( QUICC_BD_RX_CL | QUICC_BD_RX_OV | \
179 QUICC_BD_RX_CR | QUICC_BD_RX_SH | \
180 QUICC_BD_RX_NO | QUICC_BD_RX_LG | \
183 // Transmit buffer status
184 #define QUICC_BD_TX_PAD 0x4000 // Pad short packets
185 #define QUICC_BD_TX_LAST 0x0800 // Last buffer in chain
186 #define QUICC_BD_TX_TC 0x0400 // Transmit CRC after buffer
187 #define QUICC_BD_TX_DEF 0x0200 // Transmission was deferred
188 #define QUICC_BD_TX_HB 0x0100 // Heartbeat detected
189 #define QUICC_BD_TX_LC 0x0080 // Late collision
190 #define QUICC_BD_TX_RL 0x0040 // Retransmit limit exceeded
191 #define QUICC_BD_TX_RC 0x003C // Retry count
192 #define QUICC_BD_TX_UN 0x0002 // Tx underrun
193 #define QUICC_BD_TX_CSL 0x0001 // Carrier lost
195 #define QUICC_BD_TX_ERRORS (QUICC_BD_TX_CSL | QUICC_BD_TX_UN | \
196 QUICC_BD_TX_RL | QUICC_BD_TX_LC | \
197 QUICC_BD_TX_HB | QUICC_BD_TX_DEF )
199 #include CYGDAT_DEVS_QUICC_ETH_INL // Platform specifics
201 #define IEEE_8023_MAX_FRAME 1518 // Largest possible ethernet frame
202 #define IEEE_8023_MIN_FRAME 64 // Smallest possible ethernet frame