1 #ifndef CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
2 #define CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
4 // ====================================================================
8 // Device I/O - Description of PowerPC QUICC/SMC serial hardware
10 // ====================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Gary Thomas
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 // ====================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: gthomas
50 // Purpose: Internal interfaces for serial I/O drivers
53 //####DESCRIPTIONEND####
55 // ====================================================================
57 // Description of serial ports using QUICC/SMC
59 #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
61 static unsigned int smc_select_stop_bits[] = {
63 QUICC_SMCMR_SB(1), // 1 stop bit
64 QUICC_SMCMR_SB(1), // 1.5 stop bit
65 QUICC_SMCMR_SB(2) // 2 stop bits
68 static unsigned int smc_select_parity[] = {
69 QUICC_SMCMR_PE(0), // No parity
70 QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(1), // Even parity
71 QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(0), // Odd parity
76 static unsigned int scc_select_word_length[] = {
77 QUICC_SCC_PSMR_CLEN(5), // 5 bits / word (char)
78 QUICC_SCC_PSMR_CLEN(6),
79 QUICC_SCC_PSMR_CLEN(7),
80 QUICC_SCC_PSMR_CLEN(8)
83 static unsigned int scc_select_stop_bits[] = {
84 QUICC_SCC_PSMR_SB(1), // 0.5 stop bit ??
85 QUICC_SCC_PSMR_SB(1), // 1 stop bit
86 QUICC_SCC_PSMR_SB(2), // 1.5 stop bit
87 QUICC_SCC_PSMR_SB(2) // 2 stop bits
91 static unsigned int scc_select_parity[] = {
92 QUICC_SCC_PSMR_PE(0), // No parity
93 QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(2)|QUICC_SCC_PSMR_RPM(2), // Even parity
94 QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(0)|QUICC_SCC_PSMR_RPM(0), // Odd parity
95 QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(3)|QUICC_SCC_PSMR_RPM(3), // High (mark) parity
96 QUICC_SCC_PSMR_PE(1)|QUICC_SCC_PSMR_TPM(1)|QUICC_SCC_PSMR_RPM(1), // Low (space) parity
99 // Baud rate values, based on board clock
101 static cyg_int32 select_baud[] = {
126 #define UART_BITRATE(n) ((((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)-1)
127 #define UART_SLOW_BITRATE(n) ((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/n))
129 // Channel type select
133 #endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H