packages/hal/arm/arm9/var/v2_0/include/hal_cache.h

   1 #ifndef CYGONCE_HAL_CACHE_H
   2 #define CYGONCE_HAL_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      hal_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   gthomas
  47 // Contributors:hmt, jskov
  48 //              Travis C. Furrer <furrer@mit.edu>
  49 //              Tom Chase        <tomc@dtccom.com>
  50 // Date:        2005-05-10
  51 // Purpose:     Cache control API
  52 // Description: The macros defined here provide the HAL APIs for handling
  53 //              cache control operations.
  54 // Usage:
  55 //              #include <cyg/hal/hal_cache.h>
  56 //              ...
  57 //
  58 //
  59 //####DESCRIPTIONEND####
  60 //
  61 //=============================================================================
  62
  63 #include <cyg/infra/cyg_type.h>
  64 #include <cyg/hal/hal_mmu.h>
  65
  66
  67 //-----------------------------------------------------------------------------
  68 // Cache dimensions
  69
  70 #if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
  71 # define HAL_ICACHE_SIZE                 0x4000
  72 # define HAL_ICACHE_LINE_SIZE            32
  73 # define HAL_ICACHE_WAYS                 64
  74 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  75
  76 # define HAL_DCACHE_SIZE                 0x4000
  77 # define HAL_DCACHE_LINE_SIZE            32
  78 # define HAL_DCACHE_WAYS                 64
  79 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  80
  81 # define HAL_WRITE_BUFFER                64
  82
  83 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
  84 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
  85 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
  86
  87 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
  88 # define HAL_ICACHE_SIZE                 0x2000
  89 # define HAL_ICACHE_LINE_SIZE            32
  90 # define HAL_ICACHE_WAYS                 64
  91 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  92
  93 # define HAL_DCACHE_SIZE                 0x2000
  94 # define HAL_DCACHE_LINE_SIZE            32
  95 # define HAL_DCACHE_WAYS                 64
  96 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  97
  98 # define HAL_WRITE_BUFFER                64
  99
 100 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 101 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
 102 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
 103
 104 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
 105 # define HAL_ICACHE_SIZE                 0x4000
 106 # define HAL_ICACHE_LINE_SIZE            16
 107 # define HAL_ICACHE_WAYS                 2
 108 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 109
 110 # define HAL_DCACHE_SIZE                 0x2000
 111 # define HAL_DCACHE_LINE_SIZE            16
 112 # define HAL_DCACHE_WAYS                 2
 113 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 114
 115 # define HAL_WRITE_BUFFER                64
 116 // must flush everything manually
 117 # define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
 118
 119 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
 120 # define HAL_ICACHE_SIZE                 0x4000
 121 # define HAL_ICACHE_LINE_SIZE            32
 122 # define HAL_ICACHE_WAYS                 4
 123 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 124
 125 # define HAL_DCACHE_SIZE                 0x2000
 126 # define HAL_DCACHE_LINE_SIZE            32
 127 # define HAL_DCACHE_WAYS                 4
 128 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 129
 130 # define HAL_WRITE_BUFFER                64
 131
 132 #define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
 133
 134 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
 135 # define HAL_ICACHE_SIZE                 0x1000
 136 # define HAL_ICACHE_LINE_SIZE            16
 137 # define HAL_ICACHE_WAYS                 4
 138 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 139
 140 # define HAL_DCACHE_SIZE                 0x1000
 141 # define HAL_DCACHE_LINE_SIZE            16
 142 # define HAL_DCACHE_WAYS                 4
 143 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 144
 145 # define HAL_WRITE_BUFFER                32
 146
 147 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 148 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x10
 149 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
 150
 151 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
 152 # define HAL_ICACHE_SIZE                 0
 153 # define HAL_ICACHE_LINE_SIZE            0
 154 # define HAL_ICACHE_WAYS                 0
 155 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 156
 157 # define HAL_DCACHE_SIZE                 0
 158 # define HAL_DCACHE_LINE_SIZE            0
 159 # define HAL_DCACHE_WAYS                 0
 160 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 161
 162 # define HAL_WRITE_BUFFER                32
 163
 164 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 165 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0
 166 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0
 167
 168 #else
 169 # error "No cache details defined"
 170 #endif
 171
 172 // FIXME: much of the code below should make better use of
 173 // the definitions from hal_mmu.h
 174
 175 //-----------------------------------------------------------------------------
 176 // Global control of Instruction cache
 177
 178 #if HAL_ICACHE_SIZE != 0
 179
 180 // FIXME: disable/enable instruction streaming?
 181
 182 // Enable the instruction cache
 183 #define HAL_ICACHE_ENABLE()                                             \
 184 CYG_MACRO_START                                                         \
 185     asm volatile (                                                      \
 186         "mrc  p15,0,r1,c1,c0,0;"                                        \
 187         "orr  r1,r1,#0x1000;"                                           \
 188         "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
 189                               /* that MMU and alignment faults */       \
 190                               /* are enabled)                  */       \
 191         "mcr  p15,0,r1,c1,c0,0"                                         \
 192         :                                                               \
 193         :                                                               \
 194         : "r1" /* Clobber list */                                       \
 195         );                                                              \
 196 CYG_MACRO_END
 197
 198 // Disable the instruction cache (and invalidate it, required semanitcs)
 199 #define HAL_ICACHE_DISABLE()                                            \
 200 CYG_MACRO_START                                                         \
 201     asm volatile (                                                      \
 202         "mrc    p15,0,r1,c1,c0,0;"                                      \
 203         "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
 204         "mcr    p15,0,r1,c1,c0,0;"                                      \
 205         "mov    r1,#0;"                                                 \
 206         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 207         "nop;" /* next few instructions may be via cache    */          \
 208         "nop;"                                                          \
 209         "nop;"                                                          \
 210         "nop;"                                                          \
 211         "nop;"                                                          \
 212         "nop"                                                           \
 213         :                                                               \
 214         :                                                               \
 215         : "r1" /* Clobber list */                                       \
 216         );                                                              \
 217 CYG_MACRO_END
 218
 219 // Query the state of the instruction cache
 220 #define HAL_ICACHE_IS_ENABLED(_state_)                                   \
 221 CYG_MACRO_START                                                          \
 222     register cyg_uint32 reg;                                             \
 223     asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
 224                   : "=r"(reg)                                            \
 225                   :                                                      \
 226         );                                                               \
 227     (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
 228 CYG_MACRO_END
 229
 230 // Invalidate the entire cache
 231 #define HAL_ICACHE_INVALIDATE_ALL()                                     \
 232 CYG_MACRO_START                                                         \
 233     /* this macro can discard dirty cache lines (N/A for ICache) */     \
 234     asm volatile (                                                      \
 235         "mov    r1,#0;"                                                 \
 236         "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
 237         "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
 238         "nop;" /* next few instructions may be via cache    */          \
 239         "nop;"                                                          \
 240         "nop;"                                                          \
 241         "nop;"                                                          \
 242         "nop;"                                                          \
 243         "nop;"                                                          \
 244         :                                                               \
 245         :                                                               \
 246         : "r1" /* Clobber list */                                       \
 247         );                                                              \
 248 CYG_MACRO_END
 249
 250 // Synchronize the contents of the cache with memory.
 251 // (which includes flushing out pending writes)
 252 #define HAL_ICACHE_SYNC()                                       \
 253 CYG_MACRO_START                                                 \
 254     HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
 255     HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
 256 CYG_MACRO_END
 257
 258 #else
 259
 260 #define HAL_ICACHE_ENABLE()
 261 #define HAL_ICACHE_DISABLE()
 262 #define HAL_ICACHE_IS_ENABLED(_state_) ((_state_) = 0)
 263 #define HAL_ICACHE_INVALIDATE_ALL()
 264 #define HAL_ICACHE_SYNC()
 265
 266 #endif
 267
 268 // Set the instruction cache refill burst size
 269 //#define HAL_ICACHE_BURST_SIZE(_size_)
 270
 271 // Load the contents of the given address range into the instruction cache
 272 // and then lock the cache so that it stays there.
 273 //#define HAL_ICACHE_LOCK(_base_, _size_)
 274
 275 // Undo a previous lock operation
 276 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 277
 278 // Unlock entire cache
 279 //#define HAL_ICACHE_UNLOCK_ALL()
 280
 281 //-----------------------------------------------------------------------------
 282 // Instruction cache line control
 283
 284 // Invalidate cache lines in the given range without writing to memory.
 285 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 286
 287 //-----------------------------------------------------------------------------
 288 // Global control of data cache
 289
 290 #if HAL_DCACHE_SIZE != 0
 291
 292 // Enable the data cache
 293 #define HAL_DCACHE_ENABLE()                                             \
 294 CYG_MACRO_START                                                         \
 295     asm volatile (                                                      \
 296         "mrc  p15,0,r1,c1,c0,0;"                                        \
 297         "orr  r1,r1,#0x000F;" /* enable DCache (also ensures    */      \
 298                               /* the MMU, alignment faults, and */      \
 299                               /* write buffer are enabled)      */      \
 300         "mcr  p15,0,r1,c1,c0,0"                                         \
 301         :                                                               \
 302         :                                                               \
 303         : "r1" /* Clobber list */                                       \
 304         );                                                              \
 305 CYG_MACRO_END
 306
 307 // Disable the data cache (and invalidate it, required semanitcs)
 308 #define HAL_DCACHE_DISABLE()                                            \
 309 CYG_MACRO_START                                                         \
 310     asm volatile (                                                      \
 311         "mrc  p15,0,r1,c1,c0,0;"                                        \
 312         "bic  r1,r1,#0x000C;" /* disable DCache AND write buffer  */    \
 313                               /* but not MMU and alignment faults */    \
 314         "mcr  p15,0,r1,c1,c0,0;"                                        \
 315         "mov    r1,#0;"                                                 \
 316         "mcr  p15,0,r1,c7,c6,0" /* clear data cache */                  \
 317         :                                                               \
 318         :                                                               \
 319         : "r1" /* Clobber list */                                       \
 320         );                                                              \
 321 CYG_MACRO_END
 322
 323 // Query the state of the data cache
 324 #define HAL_DCACHE_IS_ENABLED(_state_)                                   \
 325 CYG_MACRO_START                                                          \
 326     register int reg;                                                    \
 327     asm volatile ("mrc  p15,0,%0,c1,c0,0;"                               \
 328                   : "=r"(reg)                                            \
 329                   :                                                      \
 330         );                                                               \
 331     (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
 332 CYG_MACRO_END
 333
 334 // Flush the entire dcache (and then both TLBs, just in case)
 335 #define HAL_DCACHE_INVALIDATE_ALL()                                     \
 336 CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
 337     asm volatile (                                                      \
 338         "mov    r0,#0;"                                                 \
 339         "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                  \
 340         "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                 \
 341         :                                                               \
 342         :                                                               \
 343         : "r0","memory" /* clobber list */);                            \
 344 CYG_MACRO_END
 345
 346 // Synchronize the contents of the cache with memory.
 347 #ifdef CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE
 348 #define HAL_DCACHE_SYNC()                                               \
 349 CYG_MACRO_START                                                         \
 350     asm volatile (                                                      \
 351         "mov    r0, #0;"                                                \
 352         "mcr    p15,0,r0,c7,c10,0;"  /* clean DCache */                 \
 353         "1: mrc p15,0,r0,c15,c4,0;"  /* wait for dirty flag to clear */ \
 354         "ands   r0,r0,#0x80000000;"                                     \
 355         "bne    1b;"                                                    \
 356         "mov    r0,#0;"                                                 \
 357         "mcr    p15,0,r0,c7,c6,0;"  /* flush DCache */                  \
 358         "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
 359         :                                                               \
 360         :                                                               \
 361         : "r0" /* Clobber list */                                       \
 362         );                                                              \
 363 CYG_MACRO_END
 364 #elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
 365 #define HAL_DCACHE_SYNC()                                               \
 366 CYG_MACRO_START                                                         \
 367     cyg_uint32 _tmp1, _tmp2;                                            \
 368     asm volatile (                                                      \
 369         "mov    %0, #0;"                                                \
 370         "1: "                                                           \
 371         "mov    %1, #0;"                                                \
 372         "2: "                                                           \
 373         "orr    r0,%0,%1;"                                              \
 374         "mcr    p15,0,r0,c7,c14,2;"  /* clean index in DCache */        \
 375         "add    %1,%1,%2;"                                              \
 376         "cmp    %1,%3;"                                                 \
 377         "bne    2b;"                                                    \
 378         "add    %0,%0,#0x04000000;"  /* get to next index */            \
 379         "cmp    %0,#0;"                                                 \
 380         "bne    1b;"                                                    \
 381         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 382         : "=r" (_tmp1), "=r" (_tmp2)                                    \
 383         : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),            \
 384           "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)            \
 385         : "r0" /* Clobber list */                                       \
 386         );                                                              \
 387 CYG_MACRO_END
 388 #elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE)
 389 /*
 390  * 'Clean & Invalidate whole DCache'
 391   */
 392 #define HAL_DCACHE_SYNC()                                               \
 393 CYG_MACRO_START                                                         \
 394     asm volatile (                                                      \
 395         "mov    r0, #255 << 4;" /* 256 entries/set */ \
 396         "2: "                    \
 397         "mcr    p15, 0, r0, c7, c14, 2;" \
 398         "subs   r0, r0, #1 << 4;" \
 399         "bcs    2b;"            /* entries 255 to 0 */ \
 400         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 401         : \
 402         : \
 403         : "r0" /* Clobber list */                                       \
 404         );                                                              \
 405 CYG_MACRO_END
 406 #elif defined(CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE)
 407 /*
 408  * 'Clean & Invalidate whole DCache'
 409  */
 410 #define HAL_DCACHE_SYNC()                                               \
 411 CYG_MACRO_START                                                         \
 412     asm volatile (                                                      \
 413         "1: "                   /* clean & invalidate D index */ \
 414         "mrc    p15, 0, r15, c7, c14, 3;" \
 415         "bne    1b;" \
 416         "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
 417         : \
 418         : \
 419         : "r0" /* Clobber list */                                       \
 420         );                                                              \
 421 CYG_MACRO_END
 422 #else
 423 # error "Don't know how to sync Dcache"
 424 #endif
 425
 426 #else
 427
 428 #define HAL_DCACHE_ENABLE()
 429 #define HAL_DCACHE_DISABLE()
 430 #define HAL_DCACHE_IS_ENABLED(_state_) ((_state_) = 0)
 431 #define HAL_DCACHE_INVALIDATE_ALL()
 432 #define HAL_DCACHE_SYNC()
 433
 434 #endif
 435
 436
 437 // Set the data cache refill burst size
 438 //#define HAL_DCACHE_BURST_SIZE(_size_)
 439
 440 // Set the data cache write mode
 441 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 442
 443 #define HAL_DCACHE_WRITETHRU_MODE       0
 444 #define HAL_DCACHE_WRITEBACK_MODE       1
 445
 446 // Get the current writeback mode - or only writeback mode if fixed
 447 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START           \
 448     _mode_ = HAL_DCACHE_WRITEBACK_MODE;                                 \
 449 CYG_MACRO_END
 450
 451 // Load the contents of the given address range into the data cache
 452 // and then lock the cache so that it stays there.
 453 //#define HAL_DCACHE_LOCK(_base_, _size_)
 454
 455 // Undo a previous lock operation
 456 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 457
 458 // Unlock entire cache
 459 //#define HAL_DCACHE_UNLOCK_ALL()
 460
 461 //-----------------------------------------------------------------------------
 462 // Data cache line control
 463
 464 // Allocate cache lines for the given address range without reading its
 465 // contents from memory.
 466 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 467
 468 // Write dirty cache lines to memory and invalidate the cache entries
 469 // for the given address range.
 470 // ---- this seems not to work despite the documentation ---
 471 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 472 //CYG_MACRO_START
 473 //    HAL_DCACHE_STORE( _base_ , _size_ );
 474 //    HAL_DCACHE_INVALIDATE( _base_ , _size_ );
 475 //CYG_MACRO_END
 476
 477 // Invalidate cache lines in the given range without writing to memory.
 478 // ---- this seems not to work despite the documentation ---
 479 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 480 //CYG_MACRO_START
 481 //    register int addr, enda;
 482 //    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
 483 //              enda = (int)(_base_) + (_size_);
 484 //          addr < enda ;
 485 //          addr += HAL_DCACHE_LINE_SIZE )
 486 //    {
 487 //        asm volatile (
 488 //                      "mcr  p15,0,%0,c7,c6,1;" /* flush entry away */
 489 //                      :
 490 //                      : "r"(addr)
 491 //                      : "memory"
 492 //            );
 493 //    }
 494 //CYG_MACRO_END
 495
 496 // Write dirty cache lines to memory for the given address range.
 497 // ---- this seems not to work despite the documentation ---
 498 //#define HAL_DCACHE_STORE( _base_ , _size_ )
 499 //CYG_MACRO_START
 500 //    register int addr, enda;
 501 //    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
 502 //              enda = (int)(_base_) + (_size_);
 503 //          addr < enda ;
 504 //          addr += HAL_DCACHE_LINE_SIZE )
 505 //    {
 506 //        asm volatile ("mcr  p15,0,%0,c7,c10,1;" /* push entry to RAM */
 507 //                      :
 508 //                      : "r"(addr)
 509 //                      : "memory"
 510 //            );
 511 //    }
 512 //CYG_MACRO_END
 513
 514 // Preread the given range into the cache with the intention of reading
 515 // from it later.
 516 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 517
 518 // Preread the given range into the cache with the intention of writing
 519 // to it later.
 520 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 521
 522 // Allocate and zero the cache lines associated with the given range.
 523 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
 524
 525 //-----------------------------------------------------------------------------
 526 // Cache controls for safely disabling/reenabling caches around execution
 527 // of relocated code.
 528
 529 #define HAL_FLASH_CACHES_OFF(_d_, _i_)          \
 530     CYG_MACRO_START                             \
 531     HAL_ICACHE_IS_ENABLED(_i_);                 \
 532     HAL_DCACHE_IS_ENABLED(_d_);                 \
 533     HAL_ICACHE_INVALIDATE_ALL();                \
 534     HAL_ICACHE_DISABLE();                       \
 535     HAL_DCACHE_SYNC();                          \
 536     HAL_DCACHE_INVALIDATE_ALL();                \
 537     HAL_DCACHE_DISABLE();                       \
 538     CYG_MACRO_END
 539
 540 #define HAL_FLASH_CACHES_ON(_d_, _i_)           \
 541     CYG_MACRO_START                             \
 542     if (_d_) HAL_DCACHE_ENABLE();               \
 543     if (_i_) HAL_ICACHE_ENABLE();               \
 544     CYG_MACRO_END
 545
 546 //-----------------------------------------------------------------------------
 547 // Virtual<->Physical translations
 548 #ifndef HAL_VIRT_TO_PHYS_ADDRESS
 549 extern cyg_uint32 hal_virt_to_phys_address(cyg_uint32 phys);
 550 #define HAL_VIRT_TO_PHYS_ADDRESS(_va, _pa) \
 551    _pa = hal_virt_to_phys_address(_va)
 552 #endif
 553 //-----------------------------------------------------------------------------
 554 #endif // ifndef CYGONCE_HAL_CACHE_H
 555 // End of hal_cache.h