1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): nickg, gthomas
47 // Contributors: nickg, gthomas
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <cyg/infra/cyg_type.h>
62 #include <cyg/hal/hal_mmu.h>
64 //-----------------------------------------------------------------------------
65 // FIXME: This definition forces the IO flash driver to use a
66 // known-good procedure for fiddling flash before calling flash device
67 // driver functions. The procedure breaks on other platform/driver
68 // combinations though so is depricated. Hence this definition.
70 // If you work on this target, please try to remove this definition
71 // and verify that the flash driver still works (both from RAM and
72 // flash). If it does, remove the definition and this comment for good
73 // [and the old macro definition if this happens to be the last client
75 #define HAL_FLASH_CACHES_OLD_MACROS
77 //-----------------------------------------------------------------------------
80 #define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes
81 #define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line
82 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
83 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
85 #define HAL_CACHE_UNIFIED // Let programs know the caches are combined
87 //-----------------------------------------------------------------------------
88 // Global control of caches
90 // Note: the 'mrc' doesn't seem to work.
92 // Enable the data cache
93 // mrc MMU_CP,0,r1,MMU_Control,c0
94 // orr r1,r1,#MMU_Control_C|MMU_Control_B
95 // mcr MMU_CP,0,r1,MMU_Control,c0
97 #define HAL_UCACHE_ENABLE() \
99 asm volatile ("mrc p15,0,r1,c1,c0;" \
100 "orr r1,r1,#0x000C;" \
101 "mcr p15,0,r1,c1,c0;" \
104 : "r1" /* Clobber list */ \
109 // Disable the data cache
110 #define HAL_UCACHE_DISABLE() \
112 asm volatile ("mrc p15,0,r1,c1,c0;" \
113 "bic r1,r1,#0x000C;" \
114 "mcr p15,0,r1,c1,c0;" \
117 : "r1" /* Clobber list */ \
122 #define HAL_UCACHE_ENABLE() \
124 asm volatile ("mov r1,#0x7D;" \
125 "mcr p15,0,r1,c1,c0,0;" \
128 : "r1" /* Clobber list */ \
132 // Disable the data cache
133 #define HAL_UCACHE_DISABLE() \
135 asm volatile ("mov r1,#0x71;" \
136 "mcr p15,0,r1,c1,c0,0;" \
138 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
139 "nop; nop; nop; nop; nop;" \
142 : "r1" /* Clobber list */ \
147 // Is the cache turned on?
148 #define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
150 // Invalidate the entire cache
151 // mcr MMU_CP,0,r1,MMU_InvalidateCache,c0
152 #define HAL_UCACHE_INVALIDATE_ALL() \
156 "mcr p15,0,r1,c7,c7,0;" \
159 : "r1","memory" /* Clobber list */ \
164 // Synchronize the contents of the cache with memory.
165 #define HAL_UCACHE_SYNC() \
167 cyg_uint32 *RAM = (cyg_uint32 *)0x00000000; \
169 volatile cyg_uint32 val; \
170 for (i = 0; i < HAL_UCACHE_SETS; i++) { \
172 RAM += HAL_UCACHE_LINE_SIZE; \
176 // Purge contents of data cache
177 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
179 // Set the data cache refill burst size
180 //#define HAL_UCACHE_BURST_SIZE(_size_)
182 // Set the data cache write mode
183 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
185 //#define HAL_UCACHE_WRITETHRU_MODE 0
186 //#define HAL_UCACHE_WRITEBACK_MODE 1
188 // Load the contents of the given address range into the data cache
189 // and then lock the cache so that it stays there.
190 //#define HAL_UCACHE_LOCK(_base_, _size_)
192 // Undo a previous lock operation
193 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
195 // Unlock entire cache
196 //#define HAL_UCACHE_UNLOCK_ALL()
198 //-----------------------------------------------------------------------------
199 // Data cache line control
201 // Allocate cache lines for the given address range without reading its
202 // contents from memory.
203 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
205 // Write dirty cache lines to memory and invalidate the cache entries
206 // for the given address range.
207 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC()
209 // Invalidate cache lines in the given range without writing to memory.
210 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
212 // Write dirty cache lines to memory for the given address range.
213 #define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC()
215 // Preread the given range into the cache with the intention of reading
217 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
219 // Preread the given range into the cache with the intention of writing
221 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
223 // Allocate and zero the cache lines associated with the given range.
224 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
226 //-----------------------------------------------------------------------------
227 // Global control of data cache
229 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
230 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
231 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
232 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
234 // Enable the data cache
235 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
237 // Disable the data cache
238 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
240 // Invalidate the entire cache
241 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
243 // Synchronize the contents of the cache with memory.
244 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
246 // Query the state of the data cache
247 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
249 // Set the data cache refill burst size
250 //#define HAL_DCACHE_BURST_SIZE(_size_)
252 // Set the data cache write mode
253 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
255 //#define HAL_DCACHE_WRITETHRU_MODE 0
256 //#define HAL_DCACHE_WRITEBACK_MODE 1
258 // Load the contents of the given address range into the data cache
259 // and then lock the cache so that it stays there.
260 //#define HAL_DCACHE_LOCK(_base_, _size_)
262 // Undo a previous lock operation
263 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
265 // Unlock entire cache
266 //#define HAL_DCACHE_UNLOCK_ALL()
268 //-----------------------------------------------------------------------------
269 // Data cache line control
271 // Allocate cache lines for the given address range without reading its
272 // contents from memory.
273 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
275 // Write dirty cache lines to memory and invalidate the cache entries
276 // for the given address range.
277 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ )
279 // Invalidate cache lines in the given range without writing to memory.
280 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
282 // Write dirty cache lines to memory for the given address range.
283 #define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ )
285 // Preread the given range into the cache with the intention of reading
287 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
289 // Preread the given range into the cache with the intention of writing
291 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
293 // Allocate and zero the cache lines associated with the given range.
294 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
296 //-----------------------------------------------------------------------------
297 // Global control of Instruction cache - use Data cache controls since they
298 // are not separatable.
300 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
301 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
302 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
303 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
305 // Enable the instruction cache
306 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
308 // Disable the instruction cache
309 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
311 // Is the cache turned on?
312 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
314 // Invalidate the entire cache
315 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
317 // Synchronize the contents of the cache with memory.
318 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
320 // Set the instruction cache refill burst size
321 //#define HAL_ICACHE_BURST_SIZE(_size_)
323 // Load the contents of the given address range into the instruction cache
324 // and then lock the cache so that it stays there.
325 //#define HAL_ICACHE_LOCK(_base_, _size_)
327 // Undo a previous lock operation
328 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
330 // Unlock entire cache
331 //#define HAL_ICACHE_UNLOCK_ALL()
333 //-----------------------------------------------------------------------------
334 // Instruction cache line control
336 // Invalidate cache lines in the given range without writing to memory.
337 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
339 //-----------------------------------------------------------------------------
340 #endif // ifndef CYGONCE_HAL_CACHE_H
341 // End of hal_cache.h