1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Gary Thomas <gary@mind.be>
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //=============================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: gthomas
50 // Purpose: Cirrus EDB7XXX platform specific support routines
52 // Usage: #include <cyg/hal/hal_platform_setup.h>
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include <pkgconf/hal.h> // Architecture independent configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_edb7xxx.h> // Platform specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
64 #define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU
65 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
67 // Memory map - set up by ROM (GDB stubs)
69 // Region Logical Address Physical Address
70 // DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below)
71 // Expansion 2 0x20000000 0x20000000
72 // Expansion 3 0x30000000 0x30000000
73 // PCMCIA 0 0x40000000 0x40000000
74 // PCMCIA 1 0x50000000 0x50000000
75 // SRAM 0x60000000..0x600007FF 0x60000000
76 // I/O 0x80000000 0x80000000
77 // MMU Tables 0xC00y0000
78 // LCD buffer 0xC0000000..0xC001FFFF 0xC0000000
79 // ROM 0xE0000000..0xEFFFFFFF 0x00000000
80 // ROM 0xF0000000..0xFFFFFFFF 0x10000000
82 #ifdef CYGHWR_HAL_ARM_EDB7XXX_LCD_INSTALLED
83 #define LCD_BUFFER_SIZE 0x00020000
85 #define LCD_BUFFER_SIZE 0x00000000
87 #define DRAM_PA_START 0xC0000000
88 #define MMU_BASE DRAM_PA_START+LCD_BUFFER_SIZE
89 #define PTE_BASE MMU_BASE+0x4000
90 #if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
91 #define MMU_TABLES_SIZE (0x4000+0x1000+0x1000) // RAM used for PTE entries
92 #define DRAM_LA_END (0x00200000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
93 #elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
94 #define MMU_TABLES_SIZE (0x4000+0x4000+0x1000) // RAM used for PTE entries
95 #define DRAM_LA_END (0x01000000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
97 #define DRAM_LA_START 0x00000000
98 #define DRAM_PA MMU_BASE+MMU_TABLES_SIZE
99 #define LCD_LA_START 0xC0000000
100 #define LCD_LA_END 0xC0020000
101 #define LCD_PA 0xC0000000
102 #define ROM0_LA_START 0xE0000000
103 #define ROM0_PA 0x00000000
104 #if defined (__EDB7211)
105 #define ROM0_LA_END 0xE0800000
107 #define ROM0_LA_END 0xF0000000
109 #define ROM1_LA_START ROM0_LA_END
110 #define ROM1_LA_END 0x00000000
111 #define ROM1_PA 0x10000000
112 #define EXPANSION2_LA_START 0x20000000
113 #define EXPANSION2_PA 0x20000000
114 #define EXPANSION3_LA_START 0x30000000
115 #define EXPANSION3_PA 0x30000000
116 #define PCMCIA0_LA_START 0x40000000
117 #define PCMCIA0_PA 0x40000000
118 #define PCMCIA1_LA_START 0x50000000
119 #define PCMCIA1_PA 0x50000000
120 #define SRAM_LA_START 0x60000000
121 #ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_CL_PS7111 // 4K SRAM
122 #define SRAM_LA_END 0x60001000
123 #else // 72xx - 37.5K SRAM
124 #define SRAM_LA_END 0x6000A000
126 #define SRAM_PA 0x60000000
127 #define IO_LA_START 0x80000000
128 #define IO_LA_END 0x8000f000
129 #define IO_PA 0x80000000
131 #ifndef _CYGHWR_LAYOUT_ONLY
132 // Define startup code [macros]
133 #if defined(CYGSEM_HAL_INSTALL_MMU_TABLES)
135 #ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_CL_PS7111 // CL7111, 710 processor
136 .macro MMU_INITIALIZE
137 ldr r2,=MMU_Control_Init
138 mcr MMU_CP,0,r2,MMU_Control,c0 /* MMU off */
139 mcr MMU_CP,0,r1,MMU_Base,c0
140 mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */
141 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
143 mcr MMU_CP,0,r1,MMU_DomainAccess,c0
145 ldr r1,=MMU_Control_Init|MMU_Control_M
146 mcr MMU_CP,0,r1,MMU_Control,c0
147 mov pc,r2 /* Change address spaces */
153 #else // EP7xxx, 720T processor
154 .macro MMU_INITIALIZE
155 ldr r2,=MMU_Control_Init
156 mcr MMU_CP,0,r2,MMU_Control,c0 /* MMU off */
157 mcr MMU_CP,0,r1,MMU_Base,c0
158 mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
159 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
161 mcr MMU_CP,0,r1,MMU_DomainAccess,c0
163 #ifdef CYG_HAL_STARTUP_ROMRAM
164 ldr r3,=__exception_handlers
166 ldr r3,=ROM0_LA_START
169 ldr r1,=MMU_Control_Init|MMU_Control_M
170 mcr MMU_CP,0,r1,MMU_Control,c0
171 mov pc,r2 /* Change address spaces */
177 #endif // EP7xxx,720T processor
179 #ifdef CYG_HAL_STARTUP_ROMRAM
180 .macro RELOCATE_TEXT_SEGMENT
181 ldr r2,=__exception_handlers
182 ldr r3,=ROM0_LA_START
185 ldr r4,=__rom_data_end
192 mov pc,r2 /* Change address spaces */
200 #ifdef CYG_HAL_STARTUP_RAM
201 .macro RELOCATE_RAM_IMAGE
202 // Special code to handle case where program has been loaded into DRAM
203 // _somewhere_. This code first relocates itself into DRAM where eCos
204 // mapping will expect it to be. Note since we don't know the current
205 // MMU mapping, this is tricky. This is handled by putting a small
206 // routine into SRAM (which is always mapped 1-1) that turns off the
207 // MMU whilst it stores one word into physical memory. Once the whole
208 // program has been relocated thusly, the MMU is shut off again while
209 // the eCos memory mapping takes place
211 // Routine to store one item in physical memory, with the MMU off
213 ldr r5,=MMU_Control_Init
214 mcr MMU_CP,0,r5,MMU_Control,c0 /* MMU off */
218 mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
219 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
221 ldr r5,=MMU_Control_Init|MMU_Control_M
222 mcr MMU_CP,0,r5,MMU_Control,c0
225 // Copy above routine to SRAM, whose address does not change with MMU
227 add r2,r1,#_phys_store_end-_phys_store
228 ldr r3,=SRAM_LA_START
233 ldr r6,=SRAM_LA_START
234 // Relocate code in DRAM to where eCos mapping wants it
239 ldr r2,=__exception_handlers
241 // ldr r1,=0xF0020000
244 // ldr r2,=DRAM_PA+0x20000
246 ldr r4,=__exception_handlers
249 // ldr r3,=0xF0040000
251 mov lr,pc // Call phys_store() function above
255 // Now, turn off the MMU an execute the rest of this code in PHYSICAL memory
259 ldr r5,=MMU_Control_Init
260 mcr MMU_CP,0,r5,MMU_Control,c0 /* MMU off */
265 15: mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
266 mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
268 #endif // CYG_HAL_STARTUP_RAM
269 #ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_EP7312
270 .macro INIT_MEMORY_CONFIG
271 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
275 ldr r12,=SYSFLG1_UTXFF1
290 #ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_EP7209
291 // No DRAM controller
292 .macro INIT_MEMORY_CONFIG
293 /* Initialize memory configuration */
301 #else // CYGHWR_HAL_ARM_EDB7XXX_VARIANT = EP7211, EP7212
302 .macro INIT_MEMORY_CONFIG
303 /* Initialize memory configuration */
311 ldr r2,=0x81 /* DRAM refresh = 64KHz */
317 #if defined(CYGSEM_HAL_STATIC_MMU_TABLES)
318 #define PLATFORM_SETUP1 \
319 INIT_MEMORY_CONFIG ;\
320 ldr r1,=_MMU_table-0xE0000000 ;\
322 RELOCATE_TEXT_SEGMENT
324 #define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>
327 // MMU tables placed in DRAM
329 #if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
330 // Note: The DRAM on this board is very irregular in that every
331 // other 256K piece is missing. E.g. only these [physical]
332 // addresses are valid:
333 // 0xC0000000..0xC003FFFF
334 // 0xC0080000..0xC00BFFFF
335 // 0xC0200000..0xC023FFFF Note the additional GAP!
337 // 0xC0800000..0xC083FFFF Note the additional GAP!
338 // 0xC0880000..0xC08CFFFF
339 // 0xC0A00000..0xC0A3FFFF
341 // The MMU mapping code takes this into consideration and creates
342 // a continuous logical map for the DRAM.
345 ldr r3,=DRAM_LA_START
348 /* 0x00000000..0x000FFFFF */
349 mov r6,r2 /* Set up page table descriptor */
350 ldr r7,=MMU_L1_TYPE_Page
352 str r6,[r1],#4 /* Store PTE, update pointer */
353 10: mov r6,r5 /* Build page table entry */
354 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
356 ldr r7,=MMU_PAGE_SIZE
357 str r6,[r2],#4 /* Next page */
360 ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE
361 cmp r3,r8 /* Done with first 1M? */
363 ldr r7,=0x40000 /* Special check for 256K boundary */
367 add r5,r5,r7 /* Skip 256K hole */
371 add r5,r5,r7 /* Nothing at 0xC0100000 */
372 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */
378 /* 0x00100000..0x001FFFFF */
379 mov r6,r2 /* Set up page table descriptor */
380 ldr r7,=MMU_L1_TYPE_Page
382 str r6,[r1],#4 /* Store PTE, update pointer */
383 10: mov r6,r5 /* Build page table entry */
384 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
386 ldr r7,=MMU_PAGE_SIZE
387 str r6,[r2],#4 /* Next page */
389 cmp r3,r4 /* Done with first DRAM? */
392 ldr r7,=0x40000 /* Special check for 256K boundary */
396 add r5,r5,r7 /* Skip 256K hole */
400 add r5,r5,r7 /* Nothing at 0xC0300000 */
401 ldr r7,=0x400000 /* Also nothing at 0xC0400000 */
408 #elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
409 // The 16M EDB72xx boards are arranged as:
410 // 0xC0000000..0xC07FFFFF
411 // 0xC1000000..0xC17FFFFF
412 // The 16M EDB7312 board is arranged as:
413 // 0xC0000000..0xC0FFFFFF
416 ldr r3,=DRAM_LA_START
419 /* 0xXXX00000..0xXXXFFFFF */
420 10: mov r6,r2 /* Set up page table descriptor */
421 ldr r7,=MMU_L1_TYPE_Page
423 str r6,[r1],#4 /* Store PTE, update pointer */
424 ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE
425 #if !defined(__EDB7312)
426 // EDB7312 has contiguous SDRAM
427 ldr r9,=DRAM_PA_START+0x00800000 /* Skip at 8M boundary */
430 ldr r5,=DRAM_PA_START+0x01000000 /* Next chunk of DRAM */
434 15: mov r6,r5 /* Build page table entry */
435 ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
437 ldr r7,=MMU_PAGE_SIZE
438 str r6,[r2],#4 /* Next page */
441 cmp r3,r4 /* End of DRAM? */
443 sub r8,r8,#1 /* End of 1M section? */
445 bne 12b /* Next page */
446 b 10b /* Next section */
450 #error Invalid DRAM size select
453 .macro MAP_L1_SEGMENT start end phys prot
454 ldr r3,=0x3FF /* Page tables need 2K boundary */
462 ldr r7,=MMU_SECTION_SIZE
471 .macro PLATFORM_SETUP1
473 #ifdef CYG_HAL_STARTUP_RAM
476 /* Initialize MMU to create new memory map */
480 /* Nothing until PCMCIA0 */
481 MAP_L1_SEGMENT (DRAM_LA_END+0x000FFFFF)&0xFFF00000 EXPANSION2_LA_START 0 MMU_L1_TYPE_Fault
482 /* EXPANSION2, EXPANSION3, PCMCIA0, PCMCIA1 */
483 MAP_L1_SEGMENT EXPANSION2_LA_START SRAM_LA_START EXPANSION2_PA MMU_L1_TYPE_Section|MMU_AP_Any
485 ldr r3,=SRAM_LA_START
486 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
489 ldr r7,=MMU_PAGE_SIZE
491 05: ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
497 ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE
498 ldr r5,=MMU_L2_TYPE_Fault
504 ldr r5,=MMU_L1_TYPE_Fault
505 ldr r7,=MMU_SECTION_SIZE
511 ldr r3,=0x3FF /* Page tables need 2K boundary */
515 ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
520 ldr r7,=MMU_PAGE_SIZE
521 ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All
527 ldr r4,=IO_LA_START+MMU_SECTION_SIZE
528 ldr r5,=MMU_L2_TYPE_Fault
529 ldr r7,=MMU_PAGE_SIZE
535 ldr r5,=MMU_L1_TYPE_Fault
536 ldr r7,=MMU_SECTION_SIZE
541 /* LCD Buffer & Unmapped DRAM (holes and all) */
542 MAP_L1_SEGMENT LCD_LA_START ROM0_LA_START LCD_PA MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
544 MAP_L1_SEGMENT ROM0_LA_START ROM0_LA_END ROM0_PA MMU_L1_TYPE_Section|MMU_AP_Any
546 MAP_L1_SEGMENT ROM1_LA_START ROM1_LA_END ROM1_PA MMU_L1_TYPE_Section|MMU_AP_Any
547 /* Now initialize the MMU to use this new page table */
550 #ifdef CYG_HAL_STARTUP_ROMRAM
551 RELOCATE_TEXT_SEGMENT
552 #endif // CYG_HAL_STARTUP_ROM
554 #endif // CYGSEM_HAL_STATIC_MMU_TABLES
556 #else // CYGSEM_HAL_INSTALL_MMU_TABLES
558 #define PLATFORM_SETUP1
560 #endif //_CYGHWR_LAYOUT_ONLY
562 /*---------------------------------------------------------------------------*/
563 /* end of hal_platform_setup.h */
564 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */