1 #ifndef CYGONCE_FSL_BOARD_H
2 #define CYGONCE_FSL_BOARD_H
4 //=============================================================================
6 // Platform specific support (register layout, etc)
8 //=============================================================================
9 //####ECOSGPLCOPYRIGHTBEGIN####
10 // -------------------------------------------
11 // This file is part of eCos, the Embedded Configurable Operating System.
12 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //===========================================================================
43 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #define PMIC_SPI_BASE CSPI2_BASE_ADDR
46 #define PMIC_SPI_CHIP_SELECT_NO SPI_CTRL_CS0
48 #define PBC_BASE CS4_BASE_ADDR /* Peripheral Bus Controller */
49 #define PBC_VERSION 0x0
50 #define PBC_BSTAT2 0x2
51 #define PBC_BCTRL1 0x4
52 #define PBC_BCTRL1_CLR 0x6
53 #define PBC_BCTRL2 0x8
54 #define PBC_BCTRL2_CLR 0xA
55 #define PBC_BCTRL3 0xC
56 #define PBC_BCTRL3_CLR 0xE
57 #define PBC_BCTRL4 0x10
58 #define PBC_BCTRL4_CLR 0x12
59 #define PBC_BSTAT1 0x14
60 #define BOARD_CS_LAN_BASE (CS4_BASE_ADDR + 0x00020000 + 0x300)
61 #define BOARD_CS_UART_BASE (CS4_BASE_ADDR + 0x00010000)
63 #define BOARD_FLASH_START CS0_BASE_ADDR
64 #define REDBOOT_IMAGE_SIZE 0x40000
66 /* MX31 ADS SDRAM is from 0x80000000, 128M */
67 #define SDRAM_BASE_ADDR CSD0_BASE_ADDR
68 #define SDRAM_SIZE 0x08000000
69 #define RAM_BANK0_BASE SDRAM_BASE_ADDR
72 #define LED_IS_ON(n) (readw(PBC_BASE+PBC_BCTRL1_CLR) & (1 << (n+6)))
73 #define TURN_LED_ON(n) writew((readw(PBC_BASE+PBC_BCTRL1_CLR) | (1 << (n+6))), PBC_BASE+PBC_BCTRL1)
74 #define TURN_LED_OFF(n) writew((1<<(n+6)), PBC_BASE+PBC_BCTRL1_CLR)
77 #define BOARD_DEBUG_LED(n) \
79 if (n >= 0 && n < LED_MAX_NUM) { \
87 #define BOARD_PBC_VERSION ((*(volatile unsigned short*)(PBC_BASE + PBC_VERSION)) >> 8)
89 #define DEBUG_SWITCH_1 (1 << 7)
90 #define DEBUG_SWITCH_2 (1 << 6)
91 #define DEBUG_SWITCH_3 (1 << 5)
92 #define DEBUG_SWITCH_4 (1 << 4)
93 #define DEBUG_SWITCH_5 (1 << 3)
94 #define DEBUG_SWITCH_6 (1 << 2)
95 #define DEBUG_SWITCH_7 (1 << 1)
96 #define DEBUG_SWITCH_8 (1 << 0)
97 #define CLK_INPUT_27MHZ_SET DEBUG_SWITCH_4
99 #define DEBUG_SWITCH_IS_ON(n) (((*(volatile unsigned short*)(PBC_BASE + PBC_BSTAT2)) & n) == 0)
101 while (DEBUG_SWITCH_IS_ON(DEBUG_SWITCH_1)) {
105 #endif /* CYGONCE_FSL_BOARD_H */