1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
79 #define L2CC_BASE_ADDR 0x30000000
84 #define AIPS1_BASE_ADDR 0x43F00000
85 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
86 #define MAX_BASE_ADDR 0x43F04000
87 #define EVTMON_BASE_ADDR 0x43F08000
88 #define CLKCTL_BASE_ADDR 0x43F0C000
89 #define ETB_SLOT4_BASE_ADDR 0x43F10000
90 #define ETB_SLOT5_BASE_ADDR 0x43F14000
91 #define ECT_CTIO_BASE_ADDR 0x43F18000
92 #define I2C_BASE_ADDR 0x43F80000
93 #define MU_BASE_ADDR 0x43F88000
94 #define UART1_BASE_ADDR 0x43F90000
95 #define UART2_BASE_ADDR 0x43F94000
96 #define DSM_BASE_ADDR 0x43F98000
97 #define OWIRE_BASE_ADDR 0x43F9C000
98 #define SSI1_BASE_ADDR 0x43FA0000
99 #define CSPI1_BASE_ADDR 0x43FA4000
100 #define KPP_BASE_ADDR 0x43FA8000
101 #define IOMUX_AP_BASE_ADDR 0x43FAC000
102 #define GPIO3_BASE_ADDR 0x43FB0000
103 #define CTI_AP_BASE_ADDR 0x43FB8000
106 * SPBA global module enabled #0
108 #define SPBA_MOD0_BASE_ADDR 0x50000000
109 #define MMC_SDHC1_BASE_ADDR 0x50004000
110 #define MMC_SDHC2_BASE_ADDR 0x50008000
111 #define UART3_BASE_ADDR 0x5000C000
112 #define CSPI2_BASE_ADDR 0x50010000
113 #define SSI2_BASE_ADDR 0x50014000
114 #define SIM_BASE_ADDR 0x50018000
115 #define IIM_BASE_ADDR 0x5001C000
116 #define CTI_SDMA_BASE_ADDR 0x50020000
117 #define USBOTG_CTRL_BASE_ADDR 0x50024000
118 #define SPBA_CTRL_BASE_ADDR 0x5003C000
119 #define IOMUX_COM_BASE_ADDR 0x50040000
120 #define CRM_COM_BASE_ADDR 0x50044000
121 #define MRCG_BASE_ADDR 0x50048000
122 #define UDPLL_BASE_ADDR 0x5004C000
123 #define ADPLL_BASE_ADDR 0x50050000
124 #define BDPLL_BASE_ADDR 0x50054000
125 #define CRM_AP_BASE_ADDR 0x50058000
130 #define AIPS2_BASE_ADDR 0x53F00000
131 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
132 #define FIRI_BASE_ADDR 0x53F8C000
133 #define GPT_BASE_ADDR 0x53F90000
134 #define EPIT1_BASE_ADDR 0x53F94000
135 #define EPIT2_BASE_ADDR 0x53F98000
136 #define SCC_BASE_ADDR 0x53FAC000
137 #define RNGA_BASE_ADDR 0x53FB0000
138 #define IPU_CTRL_BASE_ADDR 0x53FC0000
139 #define AUDMUX_BASE_ADDR 0x53FC4000
140 #define EDIO_BASE_ADDR 0x53FC8000
141 #define GPIO1_BASE_ADDR 0x53FCC000
142 #define GPIO2_BASE_ADDR 0x53FD0000
143 #define SDMA_BASE_ADDR 0x53FD4000
144 #define RTC_BASE_ADDR 0x53FD8000
145 #define WDOG_BASE_ADDR 0x53FDC000
146 #define PWM_BASE_ADDR 0x53FE0000
147 #define HAC_BASE_ADDR 0x53FEC000
152 #define ROMPATCH_BASE_ADDR 0x60000000
153 #define AVIC_BASE_ADDR 0x68000000
156 * NAND, SDRAM, WEIM, M3IF, EMI controllers
158 #define EXT_MEM_CTRL_BASE 0xB8000000
159 #define NFC_BASE EXT_MEM_CTRL_BASE
160 #define ESDCTL_BASE 0xB8001000
161 #define WEIM_BASE_ADDR 0xB8002000
162 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
163 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
164 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
165 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
166 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
167 #define M3IF_BASE 0xB8003000
168 #define PCMCIA_CTL_BASE 0xB8004000
171 * Memory regions and CS
173 #define IPU_MEM_BASE_ADDR 0x70000000
174 #define CSD0_BASE_ADDR 0x80000000
175 #define CSD1_BASE_ADDR 0x90000000
176 #define CS0_BASE_ADDR 0xA0000000
177 #define CS1_BASE_ADDR 0xA8000000
178 #define CS2_BASE_ADDR 0xB0000000
179 #define CS3_BASE_ADDR 0xB2000000
180 #define CS4_BASE_ADDR 0xB4000000
181 #define CS4_BASE_PSRAM 0xB5000000
182 #define CS5_BASE_ADDR 0xB6000000
184 #define INTERNAL_ROM_VA 0xF0000000
187 * IRQ Controller Register Definitions.
189 #define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
190 #define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
191 #define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
194 #define L2CC_BASE_ADDR 0x30000000
195 #define L2_CACHE_LINE_SIZE 32
196 #define L2_CACHE_CTL_REG 0x100
197 #define L2_CACHE_AUX_CTL_REG 0x104
198 #define L2_CACHE_SYNC_REG 0x730
199 #define L2_CACHE_INV_LINE_REG 0x770
200 #define L2_CACHE_INV_WAY_REG 0x77C
201 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
202 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
205 #define CRM_COM_CBMR 0x00
206 #define CRM_COM_CRSRBP 0x04
207 #define CRM_COM_CCRCR 0x08
208 #define CRM_COM_CSCR 0x0C
209 #define CRM_COM_CCCR 0x10
210 #define CRM_COM_CRSRAP 0x14
213 #define CRM_AP_ASCSR 0x00
214 #define CRM_AP_ACDR 0x04
215 #define CRM_AP_ACDER1 0x08
216 #define CRM_AP_ACDER2 0x0C
217 #define CRM_AP_ACGCR 0x10
218 #define CRM_AP_ACCGCR 0x14
219 #define CRM_AP_AMLPMRA 0x18
220 #define CRM_AP_AMLPMRB 0x1C
221 #define CRM_AP_AMLPMRC 0x20
222 #define CRM_AP_AMLPMRD 0x24
223 #define CRM_AP_AMLPMRE1 0x28
224 #define CRM_AP_AMLPMRE2 0x2C
225 #define CRM_AP_AMLPMRF 0x30
226 #define CRM_AP_AMLPMRG 0x34
227 #define CRM_AP_APGCR 0x38
228 #define CRM_AP_ACSR 0x3C
229 #define CRM_AP_ADCR 0x40
230 #define CRM_AP_ACR 0x44
231 #define CRM_AP_AMCR 0x48
232 #define CRM_AP_APCR 0x4C
233 #define CRM_AP_AMORA 0x50
234 #define CRM_AP_AMORB 0x54
235 #define CRM_AP_AGPR 0x58
236 #define CRM_AP_APRA 0x5C
237 #define CRM_AP_APRB 0x60
238 #define CRM_AP_APOR 0x64
244 /* ESDRAM parameters */
245 #define SDRAM_CSD0 0x80000000
246 #define SDRAM_CSD1 0x90000000
249 #define ESDCTL_ESDCTL0 0x00
250 #define ESDCTL_ESDCFG0 0x04
251 #define ESDCTL_ESDCTL1 0x08
252 #define ESDCTL_ESDCFG1 0x0C
253 #define ESDCTL_ESDMISC 0x10
256 #define PLL_DP_CTL 0x00
257 #define PLL_DP_CONFIG 0x04
258 #define PLL_DP_OP 0x08
259 #define PLL_DP_MFD 0x0C
260 #define PLL_DP_MFN 0x10
261 #define PLL_DP_MFNMINUS 0x14
262 #define PLL_DP_MFNPLUS 0x18
263 #define PLL_DP_HFS_OP 0x1C
264 #define PLL_DP_HFS_MFD 0x20
265 #define PLL_DP_HFS_MFN 0x24
266 #define PLL_DP_TOGC 0x28
267 #define PLL_DP_DESTAT 0x2C
271 #define CHIP_REV_1_0 0x10 /* PASS 1.0 */
272 #define CHIP_REV_2_0 0x20 /* PASS 2.0 */
273 #define CHIP_REV_2_2 0x30 /* PASS 2.2 */
274 #define CHIP_LATEST CHIP_REV_2_2
276 #define IIM_STAT_OFF 0x00
277 #define IIM_STAT_BUSY (1 << 7)
278 #define IIM_STAT_PRGD (1 << 1)
279 #define IIM_STAT_SNSD (1 << 0)
280 #define IIM_STATM_OFF 0x04
281 #define IIM_ERR_OFF 0x08
282 #define IIM_ERR_PRGE (1 << 7)
283 #define IIM_ERR_WPE (1 << 6)
284 #define IIM_ERR_OPE (1 << 5)
285 #define IIM_ERR_RPE (1 << 4)
286 #define IIM_ERR_WLRE (1 << 3)
287 #define IIM_ERR_SNSE (1 << 2)
288 #define IIM_ERR_PARITYE (1 << 1)
289 #define IIM_EMASK_OFF 0x0C
290 #define IIM_FCTL_OFF 0x10
291 #define IIM_UA_OFF 0x14
292 #define IIM_LA_OFF 0x18
293 #define IIM_SDAT_OFF 0x1C
294 #define IIM_PREV_OFF 0x20
295 #define IIM_SREV_OFF 0x24
296 #define IIM_PREG_P_OFF 0x28
297 #define IIM_SCS0_OFF 0x2C
298 #define IIM_SCS1_P_OFF 0x30
299 #define IIM_SCS2_OFF 0x34
300 #define IIM_SCS3_P_OFF 0x38
302 #define FREQ_CKIH_16_8M 16800000
303 #define FREQ_DIGRF_26M 26000000
304 #define FREQ_32768HZ (32768 * 512)
305 #define FREQ_32000HZ (32000 * 512)
306 #define CKIH_CLK_FREQ FREQ_CKIH_16_8M
308 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
312 #define EPITCMPR 0x0C
315 #define DelayTimerPresVal 3
318 #define NAND_REG_BASE (NFC_BASE + 0xE00)
319 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
320 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
321 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
322 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
323 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
324 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
325 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
326 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
327 #define NF_WR_PROT_REG_OFF (0 + 0x12)
328 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
329 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
330 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
331 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
332 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
333 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
334 #define NFC_BUFSIZE_1KB 0x0
335 #define NFC_BUFSIZE_2KB 0x1
336 #define NFC_CONFIGURATION_UNLOCKED 0x2
337 #define ECC_STATUS_RESULT_NO_ERR 0x0
338 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
339 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
340 #define NF_WR_PROT_UNLOCK 0x4
341 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
342 #define NAND_FLASH_CONFIG1_RST (1 << 6)
343 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
344 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
345 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
346 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
347 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
348 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
349 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
350 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
351 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
352 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
353 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
354 #define FDO_PAGE_SPARE_VAL 0x8
356 #define MXC_NAND_BASE_DUMMY 0xE0000000
357 #define NOR_FLASH_BOOT 0
358 #define NAND_FLASH_BOOT 0x10000000
359 #define SDRAM_NON_FLASH_BOOT 0x20000000
360 #define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
361 #define MXCFIS_NOTHING 0x00000000
362 #define MXCFIS_NAND 0x10000000
363 #define MXCFIS_NOR 0x20000000
364 #define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
366 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
367 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
368 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
370 #ifndef MXCFLASH_SELECT_NAND
371 #define IS_FIS_FROM_NAND() 0
373 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
376 #ifndef MXCFLASH_SELECT_NOR
377 #define IS_FIS_FROM_NOR() 0
379 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
382 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
383 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
386 * This macro is used to get certain bit field from a number
388 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
391 * This macro is used to set certain bit field inside a number
393 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
395 #define UART_WIDTH_32 /* internal UART is 32bit access only */
399 #if !defined(__ASSEMBLER__)
400 void cyg_hal_plf_serial_init(void);
401 void cyg_hal_plf_serial_stop(void);
402 void hal_delay_us(unsigned int usecs);
403 #define HAL_DELAY_US(n) hal_delay_us(n)
429 unsigned int pll_clock(enum plls pll);
431 unsigned int get_main_clock(enum main_clocks clk);
433 unsigned int get_peri_clock(enum peri_clocks clk);
435 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
437 #endif //#if !defined(__ASSEMBLER__)
439 #define HAL_MMU_OFF() \
442 "mcr p15, 0, r0, c7, c14, 0;" \
443 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
444 "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
445 "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
446 "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
447 "bic r0, r0, #0x1000;" /* disable ICache */ \
448 "mcr p15, 0, r0, c1, c0, 0;" /* */ \
449 "nop;" /* flush i+d-TLBs */ \
450 "nop;" /* flush i+d-TLBs */ \
451 "nop;" /* flush i+d-TLBs */ \
454 : "r0","memory" /* clobber list */); \
457 #endif // __HAL_SOC_H__