1 # ====================================================================
3 # hal_sh_sh7750_dreamcast.cdl
5 # SEGA Dreamcast HAL package configuration data
7 # ====================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 ## eCos is free software; you can redistribute it and/or modify it under
14 ## the terms of the GNU General Public License as published by the Free
15 ## Software Foundation; either version 2 or (at your option) any later version.
17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 ## You should have received a copy of the GNU General Public License along
23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 ## As a special exception, if other files instantiate templates or use macros
27 ## or inline functions from this file, or you compile this file and link it
28 ## with other works to produce a work based on this file, this file does not
29 ## by itself cause the resulting work to be covered by the GNU General Public
30 ## License. However the source code for this file must still be made available
31 ## in accordance with section (3) of the GNU General Public License.
33 ## This exception does not invalidate any other reasons why a work based on
34 ## this file might be covered by the GNU General Public License.
36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 ## at http://sources.redhat.com/ecos/ecos-license/
38 ## -------------------------------------------
39 #####ECOSGPLCOPYRIGHTEND####
40 # ====================================================================
41 ######DESCRIPTIONBEGIN####
43 # Author(s): t@keshi.org
44 # Contributors: t@keshi.org, jskov
47 #####DESCRIPTIONEND####
49 # ====================================================================
51 cdl_package CYGPKG_HAL_SH_SH7750_DREAMCAST {
52 display "SEGA Dreamcast"
54 requires CYGPKG_HAL_SH_7750
55 requires ! CYGHWR_HAL_SH_BIGENDIAN
56 define_header hal_sh_sh7750_dreamcast.h
59 The HAL package provides the support needed to run
60 eCos on SEGA Dreamcast."
62 requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
63 (CYGDAT_REDBOOT_SH_LINUX_BOOT_ENTRY == 0x8c210000) }
64 requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
65 (CYGDAT_REDBOOT_SH_LINUX_BOOT_BASE_ADDR == 0x8c001000) }
66 requires { is_active(CYGSEM_REDBOOT_SH_LINUX_BOOT) implies
67 (CYGDAT_REDBOOT_SH_LINUX_BOOT_COMMAND_LINE == "mem=16M") }
69 compile hal_diag.c plf_misc.c dreamcast_pci.c fb_support.c
70 compile -library=libextras.a boot.S
72 implements CYGINT_HAL_DEBUG_GDB_STUBS
73 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
74 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
75 implements CYGINT_HAL_PLF_IF_INIT
78 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
79 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh7750_dreamcast.h>"
80 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_IO_H <cyg/hal/plf_io.h>"
81 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
82 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x8c010000"
83 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x8c010100"
86 cdl_component CYG_HAL_STARTUP {
87 display "Startup type"
92 define -file system.h CYG_HAL_STARTUP
94 When targetting the Dreamcast it is possible to build
95 the system only for RAM bootstrap via a CD ROM."
98 cdl_option CYGSEM_DREAMCAST_FB_COMM {
99 display "Support framebuffer for communication channel"
100 active_if CYGPKG_REDBOOT
105 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
106 display "Number of communication channels on the board"
108 calculated 1+CYGSEM_DREAMCAST_FB_COMM
111 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
112 display "Debug serial port"
114 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
117 Dreamcast has only one serial port. This option
118 chooses which port will be used to connect to a host
122 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
123 display "Diagnostic serial port"
125 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
128 Dreamcast has only one serial port. This option
129 chooses which port will be used for diagnostic output."
132 cdl_option CYGNUM_HAL_SH_SH4_SCIF_BAUD_RATE_DEFAULT {
137 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
138 display "SH on-chip platform clock controls"
140 The various clocks used by the system are derived from
145 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
146 display "SH clock crystal"
151 This option specifies the frequency of the crystal all
152 other clocks are derived from."
155 cdl_option CYGHWR_HAL_SH_OOC_CKIO {
156 display "SH clock CKIO output enable"
159 This selects whether CKIO output is enabled."
162 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
163 display "SH clock PLL circuit 1"
167 This selects whether PLL1 is enabled."
170 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
171 display "SH clock PLL circuit 2"
175 This selects whether PLL2 is enabled."
178 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
179 display "SH clock first clock divider"
185 First stage clock divider according to the mode (MD0..2).
186 Set 2 for mode 2 and 4, otherwise set 1."
189 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
190 display "SH clock divider, core"
194 This divider option affects the CPU core clock."
197 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
198 display "SH clock divider, bus"
202 This divider option affects the bus clock."
205 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
206 display "SH clock divider, peripheral"
210 This divider option affects the peripheral clock."
213 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
214 display "SH clock mode"
218 This option must mirror the clock mode hardwired on
219 the MD0-MD2 pins of the CPU in order to correctly
220 initialize the FRQCR register."
224 cdl_component CYGBLD_GLOBAL_OPTIONS {
225 display "Global build options"
229 Global build options including control over
230 compiler flags, linker flags and choice of toolchain."
233 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
234 display "Global command prefix"
237 default_value { "sh-elf" }
239 This option specifies the command prefix used when
240 invoking the build tools."
243 cdl_option CYGBLD_GLOBAL_CFLAGS {
244 display "Global compiler flags"
247 default_value { "-ml -m3 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
249 This option controls the global compiler flags which
250 are used to compile all packages by
251 default. Individual packages may define
252 options which override these global flags."
255 cdl_option CYGBLD_GLOBAL_LDFLAGS {
256 display "Global linker flags"
259 default_value { "-ml -m3 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
261 This option controls the global linker flags. Individual
262 packages may define options which override these global flags."
265 cdl_option CYGBLD_BUILD_GDB_STUBS {
266 display "Build GDB stub ROM image"
268 requires CYGSEM_HAL_ROM_MONITOR
269 requires CYGBLD_BUILD_COMMON_GDB_STUBS
270 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
271 requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
272 requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
273 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
274 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
277 This option enables the building of the GDB stubs for the
278 board. The common HAL controls takes care of most of the
279 build process, but the final conversion from ELF image to
280 binary data is handled by the platform CDL, allowing
281 relocation of the data if necessary."
284 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
285 $(OBJCOPY) -O binary $< $@
290 cdl_component CYGHWR_MEMORY_LAYOUT {
291 display "Memory layout"
294 calculated { "sh_sh7750_dreamcast_ram" }
296 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
297 display "Memory layout linker script fragment"
300 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
301 calculated { "<pkgconf/mlt_sh_sh7750_dreamcast_ram.ldi>" }
304 cdl_option CYGHWR_MEMORY_LAYOUT_H {
305 display "Memory layout header file"
308 define -file system.h CYGHWR_MEMORY_LAYOUT_H
309 calculated { "<pkgconf/mlt_sh_sh7750_dreamcast_ram.h>" }
313 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
314 display "Work with a ROM monitor"
316 legal_values { "GDB_stubs" }
318 requires { CYG_HAL_STARTUP == "RAM" }
319 parent CYGPKG_HAL_ROM_MONITOR
320 requires !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
322 Support can be enabled for boot ROMs or ROM monitors which contain
323 GDB stubs. This support changes various eCos semantics such as
324 the encoding of diagnostic output, and the overriding of hardware
328 cdl_option CYGSEM_HAL_ROM_MONITOR {
329 display "Behave as a ROM monitor"
332 parent CYGPKG_HAL_ROM_MONITOR
333 requires { CYG_HAL_STARTUP == "ROM" }
335 Enable this option if this program is to be used as a ROM monitor,
336 i.e. applications will be loaded into RAM on the board, and this
337 ROM monitor may process exceptions or interrupts generated from the
338 application. This enables features such as utilizing a separate
339 interrupt stack when exceptions are generated."