unified MX27, MX25, MX37 trees

[karo-tx-redboot.git] / packages / devs / eth / phy / v2_0 / src / eth_phy.c

diff --git a/packages/devs/eth/phy/v2_0/src/eth_phy.c b/packages/devs/eth/phy/v2_0/src/eth_phy.c
index 040a8d8088b85010c6915a332674085286902059..d3943987018c4a5e5f82c5245a959ad6fbe257a7 100644 (file)
--- a/packages/devs/eth/phy/v2_0/src/eth_phy.c
+++ b/packages/devs/eth/phy/v2_0/src/eth_phy.c
@@ -52,8 +52,9 @@
 //==========================================================================
 
 #include <pkgconf/system.h>
+#include <pkgconf/io_eth_drivers.h>
+#include <pkgconf/devs_eth_phy.h>
 #include <cyg/infra/cyg_type.h>
-#include <cyg/infra/diag.h>
 
 #include <cyg/hal/hal_arch.h>
 #include <cyg/hal/drv_api.h>
@@ -86,26 +87,26 @@ phy_cmd(eth_phy_access_t *f, cyg_uint32 cmd)
 {
     cyg_uint32  retval;
     int         i, off;
-    bool        is_read = ((cmd & MII_Cmd) == MII_Read);
+    bool        is_read = (cmd & MII_Cmd) == MII_Read;
 
     // Set both bits as output
-    (f->ops.bit_level_ops.set_dir)(1);
+    f->ops.bit_level_ops.set_dir(1);
 
     // Preamble
     for (i = 0; i < 32; i++) {
-        (f->ops.bit_level_ops.set_clock)(0);
-        (f->ops.bit_level_ops.set_data)(1);
+        f->ops.bit_level_ops.set_clock(0);
+        f->ops.bit_level_ops.set_data(1);
         CYGACC_CALL_IF_DELAY_US(1);
-        (f->ops.bit_level_ops.set_clock)(1);
+        f->ops.bit_level_ops.set_clock(1);
         CYGACC_CALL_IF_DELAY_US(1);
     }
 
     // Command/data
     for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
-        (f->ops.bit_level_ops.set_clock)(0);
-        (f->ops.bit_level_ops.set_data)((cmd >> off) & 0x00000001);
+        f->ops.bit_level_ops.set_clock(0);
+        f->ops.bit_level_ops.set_data((cmd >> off) & 0x00000001);
         CYGACC_CALL_IF_DELAY_US(1);
-        (f->ops.bit_level_ops.set_clock)(1);
+        f->ops.bit_level_ops.set_clock(1);
         CYGACC_CALL_IF_DELAY_US(1);
     }
 
@@ -115,33 +116,33 @@ phy_cmd(eth_phy_access_t *f, cyg_uint32 cmd)
     if (is_read) {
         retval >>= 16;
 
-        (f->ops.bit_level_ops.set_clock)(0);
-        (f->ops.bit_level_ops.set_dir)(0);
+        f->ops.bit_level_ops.set_clock(0);
+        f->ops.bit_level_ops.set_dir(0);
         CYGACC_CALL_IF_DELAY_US(1);
-        (f->ops.bit_level_ops.set_clock)(1);
+        f->ops.bit_level_ops.set_clock(1);
         CYGACC_CALL_IF_DELAY_US(1);
-        (f->ops.bit_level_ops.set_clock)(0);
+               f->ops.bit_level_ops.set_clock(0);
         CYGACC_CALL_IF_DELAY_US(1);
 
         for (i = 0, off = 15; i < 16; i++, off--) {
-            (f->ops.bit_level_ops.set_clock)(1);
+            f->ops.bit_level_ops.set_clock(1);
             retval <<= 1;
-            retval |= (f->ops.bit_level_ops.get_data)();
+            retval |= f->ops.bit_level_ops.get_data();
             CYGACC_CALL_IF_DELAY_US(1);
-            (f->ops.bit_level_ops.set_clock)(0);
+            f->ops.bit_level_ops.set_clock(0);
             CYGACC_CALL_IF_DELAY_US(1);
         }
     }
 
     // Set both bits as output
-    (f->ops.bit_level_ops.set_dir)(1);
+    f->ops.bit_level_ops.set_dir(1);
 
     // Postamble
     for (i = 0; i < 32; i++) {
-        (f->ops.bit_level_ops.set_clock)(0);
-        (f->ops.bit_level_ops.set_data)(1);
+        f->ops.bit_level_ops.set_clock(0);
+        f->ops.bit_level_ops.set_data(1);
         CYGACC_CALL_IF_DELAY_US(1);
-        (f->ops.bit_level_ops.set_clock)(1);
+        f->ops.bit_level_ops.set_clock(1);
         CYGACC_CALL_IF_DELAY_US(1);
     }
 
@@ -153,34 +154,33 @@ _eth_phy_init(eth_phy_access_t *f)
 {
     int addr;
     unsigned short state;
-    unsigned long id;
+    unsigned long id = 0;
     struct _eth_phy_dev_entry *dev;
 
     if (f->init_done) return true;
-    (f->init)();
+    f->init();
     // Scan to determine PHY address
     f->init_done = true;
     for (addr = 0;  addr < 0x20;  addr++) {
         if (_eth_phy_read(f, PHY_ID1, addr, &state)) {
-            if (state == 0xffff || state == 0x0000) {
-                   continue;
-           }
-           id = state << 16;
+            id = state << 16;
             if (_eth_phy_read(f, PHY_ID2, addr, &state)) {
                 id |= state;
                 f->phy_addr = addr;
                 for (dev = __ETH_PHY_TAB__; dev != &__ETH_PHY_TAB_END__;  dev++) {
                     if (dev->id == id) {
-                        diag_printf("PHY: %s\n", dev->name);
+                        eth_phy_printf("PHY: %s\n", dev->name);
                         f->dev = dev;
                         return true;
                     }
                 }
-                diag_printf("Unsupported PHY device - id: %08lx\n", id);
-                //break;  // Can't handle this PHY, but look for others!
             }
         }
     }
+    if (addr >= 0x20) {
+        // Can't handle this PHY
+        eth_phy_printf("Unsupported PHY device - id: %lx\n", id);
+    }
     f->init_done = false;
     return false;
 }
@@ -189,23 +189,23 @@ externC void
 _eth_phy_reset(eth_phy_access_t *f)
 {
     if (!f->init_done) {
-        diag_printf("PHY reset without init on PHY: %p\n", f);
+        eth_phy_printf("PHY reset without init on PHY: %p\n", f);
         return;
     }
-    (f->init)();
+    f->init();
 }
 
 externC void
 _eth_phy_write(eth_phy_access_t *f, int reg, int addr, unsigned short data)
 {
     if (!f->init_done) {
-        diag_printf("PHY write without init on PHY: %p\n", f);
+        eth_phy_printf("PHY write without init on PHY: %p\n", f);
         return;
     }
     if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
         phy_cmd(f, MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
     } else {
-        (f->ops.reg_level_ops.put_reg)(reg, addr, data);
+        f->ops.reg_level_ops.put_reg(reg, addr, data);
     }
 }
 
@@ -215,7 +215,7 @@ _eth_phy_read(eth_phy_access_t *f, int reg, int addr, unsigned short *val)
     cyg_uint32 ret;
 
     if (!f->init_done) {
-        diag_printf("PHY read without init on PHY: %p\n", f);
+        eth_phy_printf("PHY read without init on PHY: %p\n", f);
         return false;
     }
     if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
@@ -223,7 +223,7 @@ _eth_phy_read(eth_phy_access_t *f, int reg, int addr, unsigned short *val)
         *val = ret;
         return true;
     } else {
-        return (f->ops.reg_level_ops.get_reg)(reg, addr, val);
+        return f->ops.reg_level_ops.get_reg(reg, addr, val);
     }
 }
 
@@ -236,7 +236,7 @@ _eth_phy_cfg(eth_phy_access_t *f, int mode)
     int i;
 
     if (!f->init_done) {
-        diag_printf("PHY config without init on PHY: %p\n", f);
+        eth_phy_printf("PHY config without init on PHY: %p\n", f);
         return 0;
     }
 
@@ -247,12 +247,12 @@ _eth_phy_cfg(eth_phy_access_t *f, int mode)
     _eth_phy_write(f, PHY_BMCR, f->phy_addr, PHY_BMCR_RESET);
     for (i = 0;  i < 5*100;  i++) {
         phy_ok = _eth_phy_read(f, PHY_BMCR, f->phy_addr, &phy_state);            
-        diag_printf("PHY: %04x\n", phy_state);
+        eth_phy_printf("PHY: %x\n", phy_state);
         if (phy_ok && !(phy_state & PHY_BMCR_RESET)) break;
         CYGACC_CALL_IF_DELAY_US(10000);   // 10ms
     }
     if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
-        diag_printf("PPC405: Can't get PHY unit to soft reset: %04x\n", phy_state);
+        eth_phy_printf("PPC405: Can't get PHY unit to soft reset: %x\n", phy_state);
         return 0;
     }
 
@@ -267,7 +267,7 @@ _eth_phy_cfg(eth_phy_access_t *f, int mode)
         }
     }
     if (phy_timeout <= 0) {
-        diag_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
+        eth_phy_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
         return 0;
     }
 
@@ -280,10 +280,10 @@ _eth_phy_state(eth_phy_access_t *f)
     int state = 0;
 
     if (!f->init_done) {
-        diag_printf("PHY state without init on PHY: %p\n", f);
+        eth_phy_printf("PHY state without init on PHY: %p\n", f);
         return 0;
     }
-    if ((f->dev->stat)(f, &state)) {
+    if (f->dev->stat(f, &state)) {
         return state;
     } else {
         return 0;