unified MX27, MX25, MX37 trees

[karo-tx-redboot.git] / packages / devs / spi / arm / mxc / v2_0 / include / mxc_spi.h

diff --git a/packages/devs/spi/arm/mxc/v2_0/include/mxc_spi.h b/packages/devs/spi/arm/mxc/v2_0/include/mxc_spi.h
index 5eedc9c87a8310f7408a3ba09866bcf58425c875..a4b09f47c05837df1999d14c2168b055cc1f5cbd 100644 (file)
--- a/packages/devs/spi/arm/mxc/v2_0/include/mxc_spi.h
+++ b/packages/devs/spi/arm/mxc/v2_0/include/mxc_spi.h
@@ -56,9 +56,9 @@
 #define SPI_RX_REG_OFF              0x0
 #define SPI_TX_REG_OFF              0x4
 #define SPI_CTRL_REG_OFF            0x8
-#define SPI_INT_CTRL_REG_OFF        0xC
 
 #if defined(MXC_SPI_VER_0_4)
+#define SPI_INT_CTRL_REG_OFF        0xC
 #define SPI_DMA_REG_OFF             0x10
 #define SPI_INT_STAT_REG_OFF        0x14
 #define SPI_PERIOD_REG_OFF          0x18
@@ -71,17 +71,22 @@
 #define SPI_CTRL_REG_RATE_WD        3   // 3-bit width
 
 #define SPI_CTRL_REG_BIT_COUNT32    (0x1F << 8)  // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23    (0x16 << 8)  // 23-bit xfer
 #define SPI_CTRL_CS0                (0 << 24)
 #define SPI_CTRL_CS1                (1 << 24)
 #define SPI_CTRL_CS2                (2 << 24)
 #define SPI_CTRL_CS3                (3 << 24)
+#define SPI_CTRL_CS_MASK            (3 << 24)
 #define SPI_CTRL_SSPOL_HIGH         (1 << 7)
 #define SPI_CTRL_SSCTL_SET          (1 << 6)
 #define SPI_CTRL_SCLK_POL_LOW       (1 << 4)
 #define SPI_CTRL_MODE_MASTER        (1 << 1)
 #define SPI_CTRL_EN                 (1 << 0)
+#define SPI_TEST_REG_RXCNT_OFFSET   4
+#define SPI_TEST_REG_RXCNT_MASK     (0xF << 4)
 
 #elif defined(MXC_SPI_VER_0_7)
+#define SPI_INT_CTRL_REG_OFF        0xC
 #define SPI_DMA_REG_OFF             0x10
 #define SPI_INT_STAT_REG_OFF        0x14
 #define SPI_PERIOD_REG_OFF          0x18
@@ -93,18 +98,64 @@
 #define SPI_CTRL_REG_RATE_SH        16  // start from bit 16
 #define SPI_CTRL_REG_RATE_WD        3   // 3-bit width
 
+#define SPI_CTRL_REG_BIT_COUNT46    (0x2D << 20)  // 48-bit xfer
 #define SPI_CTRL_REG_BIT_COUNT32    (0x1F << 20)  // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23    (0x16 << 20)  // 23-bit xfer
 #define SPI_CTRL_CS0                (0 << 12)
 #define SPI_CTRL_CS1                (1 << 12)
 #define SPI_CTRL_CS2                (2 << 12)
 #define SPI_CTRL_CS3                (3 << 12)
+#define SPI_CTRL_CS_MASK            (3 << 12)
 #define SPI_CTRL_SSPOL_HIGH         (1 << 7)
 #define SPI_CTRL_SSCTL_SET          (1 << 6)
 #define SPI_CTRL_SCLK_POL_LOW       (1 << 4)
 #define SPI_CTRL_MODE_MASTER        (1 << 1)
 #define SPI_CTRL_EN                 (1 << 0)
+#define SPI_TEST_REG_RXCNT_OFFSET   4
+#define SPI_TEST_REG_RXCNT_MASK     (0xF << 4)
+
+
+#elif defined(MXC_SPI_VER_2_3)
+#define SPI_CONFIG_REG_OFF                0xC
+#define SPI_INT_CTRL_REG_OFF            0x10
+#define SPI_DMA_REG_OFF                     0x14
+#define SPI_INT_STAT_REG_OFF            0x18
+#define SPI_PERIOD_REG_OFF                0x1C
+#define SPI_TEST_REG_OFF                    0x20
 
+#define SPI_INT_STAT_RR                       (1 << 3)
+
+#define SPI_CTRL_REG_XCH_BIT             (1 << 2)
+#define SPI_CTRL_REG_RATE_SH            12  // start from bit 12
+#define SPI_CTRL_REG_RATE_WD           4   // 3-bit width
+#define SPI_CTRL_REG_BIT_COUNT32    (0x1F << 20)  // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23    (0x16 << 20)  // 23-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT46    (0x2D << 20)  // 46-bit xfer
+#define SPI_CTRL_CS0                             (0 << 18)
+#define SPI_CTRL_CS1                             (1 << 18)
+#define SPI_CTRL_CS2                             (2 << 18)
+#define SPI_CTRL_CS3                             (3 << 18)
+#define SPI_CTRL_CS_MASK                    (3 << 18)
+#define SPI_CTRL_MODE_MASTER_0       (1 << 4)
+#define SPI_CTRL_MODE_MASTER_1       (1 << 5)
+#define SPI_CTRL_MODE_MASTER_2       (1 << 6)
+#define SPI_CTRL_MODE_MASTER_3       (1 << 7)
+#define SPI_CTRL_EN                               (1 << 0)
+
+#define SPI_CFG_SS0_POL_HIGH             (1 << 12)
+#define SPI_CFG_SS1_POL_HIGH             (1 << 13)
+#define SPI_CFG_SS2_POL_HIGH             (1 << 14)
+#define SPI_CFG_SS3_POL_HIGH             (1 << 15)
+#define SPI_CFG_SS0_POL_LOW              (0 << 12)
+#define SPI_CFG_SS1_POL_LOW              (0 << 13)
+#define SPI_CFG_SS2_POL_LOW              (0 << 14)
+#define SPI_CFG_SS3_POL_LOW              (0 << 15)
+
+#define SPI_TEST_REG_RXCNT_OFFSET  8
+#define SPI_TEST_REG_RXCNT_MASK     (0x7F << 8)
 #else
+// For MX27
+#define SPI_INT_CTRL_REG_OFF        0xC
 #define SPI_INT_STAT_REG_OFF        0xC
 #define SPI_TEST_REG_OFF            0x10
 #define SPI_PERIOD_REG_OFF          0x14
@@ -123,12 +174,16 @@
 #define SPI_CTRL_CS0                (0 << 19)
 #define SPI_CTRL_CS1                (1 << 19)
 #define SPI_CTRL_CS2                (2 << 19)
+#define SPI_CTRL_CS_MASK            (3 << 19)
 #define SPI_CTRL_SSPOL_HIGH         (1 << 8)
 #define SPI_CTRL_SSCTL_SET          (1 << 7)
 #define SPI_CTRL_SCLK_POL_LOW       (1 << 5)
 #define SPI_CTRL_REG_BIT_COUNT32    0x1F   // 32-bit xfer
+#define SPI_CTRL_REG_BIT_COUNT23    0x16   // 23-bit xfer
 #define SPI_CTRL_MODE_MASTER        (1 << 11)
 #define SPI_CTRL_EN                 (1 << 10)
+#define SPI_TEST_REG_RXCNT_OFFSET   4
+#define SPI_TEST_REG_RXCNT_MASK     (0xF << 4)
 
 #endif
 
@@ -136,4 +191,10 @@ int spi_init(unsigned int base, unsigned int baud, unsigned int ctrl_val);
 unsigned int pmic_reg(unsigned int reg, unsigned int val, unsigned int write);
 unsigned int spi_xchg_single(unsigned int data, unsigned int base);
 
+#ifdef CPLD_SPI_BASE
+unsigned int spi_cpld_xchg_single(unsigned int data, unsigned int data1, unsigned int base);
+unsigned int cpld_reg(unsigned int reg, unsigned int val, unsigned int read);
+unsigned int cpld_reg_xfer(unsigned int reg, unsigned int val, unsigned int read);
+#endif   /* CPLD_SPI_BASE */
+
 #endif                         /* __MXC_SPI_H__ */