-//==-*- c-basic-offset: 4; tab-width: 4; -*-================================
+//==========================================================================
//
// hal_soc.h
//
#include <cyg/hal/mx27_pins.h>
#ifdef __ASSEMBLER__
-
+#define UL(a) (a)
#define REG8_VAL(a) (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)
#else /* __ASSEMBLER__ */
+#define UL(a) (a##UL)
+
extern char HAL_PLATFORM_EXTRA[];
#define REG8_VAL(a) ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#endif /* __ASSEMBLER__ */
-// Default Memory Layout Definitions
+/*
+ * Default Memory Layout Definitions
+ */
-#define SOC_AIPI1_BASE 0x10000000
-#define SOC_AIPI2_BASE 0x10020000
+#define SOC_AIPI1_BASE UL(0x10000000)
+#define SOC_AIPI2_BASE UL(0x10020000)
#define SOC_AIPI_PAR_OFF 8
#define CSPI2_BASE_ADDR (SOC_AIPI1_BASE + 0x0F000)
#define CSPI3_BASE_ADDR (SOC_AIPI1_BASE + 0x17000)
-#define SOC_CRM_BASE 0x10027000
+#define SOC_CRM_BASE UL(0x10027000)
#define SOC_CRM_CSCR (SOC_CRM_BASE + 0x0)
#define SOC_CRM_MPCTL0 (SOC_CRM_BASE + 0x4)
#define SOC_CRM_MPCTL1 (SOC_CRM_BASE + 0x8)
#endif
#endif
-// PD MFD MFI MFN
-#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
+// PD MFD MFI MFN
+#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0))
#if (PLL_REF_CLK == FREQ_32768HZ)
#define PLL_REF_CLK_32768HZ
// SPCTL0 for 240 MHz
#define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
#define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL
- #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 59, 7, 9)
+ #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 755, 11, -205)
#define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2
#if defined (CLOCK_266_133_66)
#define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
#endif // PLL_REF_CLK == FREQ_26MHZ
// system control
-#define SOC_SYSCTRL_BASE 0x10027800
+#define SOC_SYSCTRL_BASE UL(0x10027800)
#define SOC_SYSCTRL_CID (SOC_SYSCTRL_BASE + 0x00)
#define SOC_SYSCTRL_FMCR (SOC_SYSCTRL_BASE + 0x14)
#define FMCR_FMS (1 << 5)
#define SOC_SYSCTRL_DCVR3 (SOC_SYSCTRL_BASE + 0x70)
// Interrupt Controller Register Definitions.
-#define SOC_AITC_BASE 0x10040000
+#define SOC_AITC_BASE UL(0x10040000)
#define SOC_AITC_INTCNTL (SOC_AITC_BASE + 0x00)
#define SOC_AITC_NIMASK (SOC_AITC_BASE + 0x04)
#define SOC_AITC_INTENNUM (SOC_AITC_BASE + 0x08)
#define UART_WIDTH_32
// UART Base Addresses
-#define SOC_UART1_BASE 0x1000A000
-#define SOC_UART2_BASE 0x1000B000
-#define SOC_UART3_BASE 0x1000C000
-#define SOC_UART4_BASE 0x1000D000
-#define SOC_UART5_BASE 0x1001B000
-#define SOC_UART6_BASE 0x1001C000
-
-#define SOC_MAX_BASE 0x1003F000
+#define SOC_UART1_BASE UL(0x1000A000)
+#define SOC_UART2_BASE UL(0x1000B000)
+#define SOC_UART3_BASE UL(0x1000C000)
+#define SOC_UART4_BASE UL(0x1000D000)
+#define SOC_UART5_BASE UL(0x1001B000)
+#define SOC_UART6_BASE UL(0x1001C000)
+
+#define SOC_MAX_BASE UL(0x1003F000)
// Slave port base offset
#define MAX_SLAVE_PORT0_OFFSET 0x0
#define MAX_SLAVE_PORT1_OFFSET 0x100
/*
* MX27 GPIO Register Definitions
*/
-#define SOC_GPIOA_BASE 0x10015000
-#define SOC_GPIOB_BASE 0x10015100
-#define SOC_GPIOC_BASE 0x10015200
-#define SOC_GPIOD_BASE 0x10015300
-#define SOC_GPIOE_BASE 0x10015400
-#define SOC_GPIOF_BASE 0x10015500
-#define SOC_GPIO_PMASK 0x10015600
+#define SOC_GPIOA_BASE UL(0x10015000)
+#define SOC_GPIOB_BASE UL(0x10015100)
+#define SOC_GPIOC_BASE UL(0x10015200)
+#define SOC_GPIOD_BASE UL(0x10015300)
+#define SOC_GPIOE_BASE UL(0x10015400)
+#define SOC_GPIOF_BASE UL(0x10015500)
+#define SOC_GPIO_PMASK UL(0x10015600)
#define GPIO_DDIR 0x0 /* Data direction reg */
#define GPIO_OCR1 0x4 /* Output config reg 1 */
#define GPIO_OCR2 0x8 /* Output config reg 2 */
*/
#define HAL_DELAY_TIMER SOC_GPT2_BASE // use timer2 for hal_delay_us()
-#define SOC_GPT1_BASE 0x10003000
-#define SOC_GPT2_BASE 0x10004000
-#define SOC_GPT3_BASE 0x10005000
-#define SOC_GPT4_BASE 0x10019000
-#define SOC_GPT5_BASE 0x1001A000
-#define SOC_GPT6_BASE 0x1001F000
+#define SOC_GPT1_BASE UL(0x10003000)
+#define SOC_GPT2_BASE UL(0x10004000)
+#define SOC_GPT3_BASE UL(0x10005000)
+#define SOC_GPT4_BASE UL(0x10019000)
+#define SOC_GPT5_BASE UL(0x1001A000)
+#define SOC_GPT6_BASE UL(0x1001F000)
#define GPT_TCTL_OFFSET 0x0
#define GPT_TPRER_OFFSET 0x4
#define GPT_TCMP_OFFSET 0x8
#define MX_STARTUP_DELAY (1000000 / 10) // 0.1s delay to get around the ethernet reset failure problem
#define TIMER_PRESCALER 3
-#define SOC_SI_ID_REG 0x10027800
+#define SOC_SI_ID_REG UL(0x10027800)
#define SOC_SILICONID_Rev1_0 0x0
#define SOC_SILICONID_Rev2_0 0x1
#define SOC_SILICONID_Rev2_1 0x2
#define CHIP_REV_3_1 4
#define CHIP_REV_unknown 0x100
-#define SOC_WDOG_BASE 0x10002000
+#define SOC_WDOG_BASE UL(0x10002000)
#define WDOG_BASE_ADDR SOC_WDOG_BASE
-#define NFC_BASE 0xD8000000
-#define SOC_ESDCTL_BASE 0xD8001000
-#define SOC_EIM_BASE 0xD8002000
-#define SOC_M3IF_BASE 0xD8003000
-#define SOC_PCMCIA_BASE 0xD8004000
+#define NFC_BASE UL(0xD8000000)
+#define SOC_ESDCTL_BASE UL(0xD8001000)
+#define SOC_EIM_BASE UL(0xD8002000)
+#define SOC_M3IF_BASE UL(0xD8003000)
+#define SOC_PCMCIA_BASE UL(0xD8004000)
#define SOC_CS0_CTL_BASE SOC_EIM_BASE
#define SOC_CS1_CTL_BASE (SOC_EIM_BASE + 0x10)
#define CSWCR_OFFSET 0x60
// Memories
-#define SOC_CSD0_BASE 0xA0000000
-#define SOC_CSD1_BASE 0xB0000000
-#define SOC_CS0_BASE 0xC0000000
+#define SOC_CSD0_BASE UL(0xA0000000)
+#define SOC_CSD1_BASE UL(0xB0000000)
+#define SOC_CS0_BASE UL(0xC0000000)
#define CS0_BASE_ADDR SOC_CS0_BASE
-#define SOC_CS1_BASE 0xC8000000
-#define SOC_CS2_BASE 0xD0000000
-#define SOC_CS3_BASE 0xD2000000
-#define SOC_CS4_BASE 0xD4000000
-#define SOC_CS5_BASE 0xD6000000
+#define SOC_CS1_BASE UL(0xC8000000)
+#define SOC_CS2_BASE UL(0xD0000000)
+#define SOC_CS3_BASE UL(0xD2000000)
+#define SOC_CS4_BASE UL(0xD4000000)
+#define SOC_CS5_BASE UL(0xD6000000)
#define NAND_REG_BASE (NFC_BASE + 0xE00)
-#define SOC_IIM_BASE 0x10028000
-#define SOC_FEC_MAC_BASE 0x10028C04
-#define SOC_FEC_MAC_BASE2 0x10028814
-#define SOC_FEC_BASE 0x1002B000
+#define SOC_IIM_BASE UL(0x10028000)
+#define SOC_FEC_MAC_BASE UL(0x10028C04)
+#define SOC_FEC_MAC_BASE2 UL(0x10028814)
+#define SOC_FEC_BASE UL(0x1002B000)
#define IIM_BASE_ADDR SOC_IIM_BASE
/* IIM */
#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
#define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
#define FDO_PAGE_SPARE_VAL 0x8
-#define MXC_NAND_BASE_DUMMY 0xE0000000
+#define MXC_NAND_BASE_DUMMY UL(0xE0000000)
#define NOR_FLASH_BOOT 0
#define NAND_FLASH_BOOT 0x10
#define SDRAM_NON_FLASH_BOOT 0x20
int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
void clock_spi_enable(unsigned int spi_clk);
-enum {
- MXC_NFC_V1,
- MXC_NFC_V2,
-};
-
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
#endif //#if !defined(__ASSEMBLER__)
projects / karo-tx-redboot.git / blobdiff