#define IIM_PROD_REV_LEN 5
#define IIM_SREV_REV_SH 4
#define IIM_SREV_REV_LEN 4
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
+#define PART_NUMBER_OFFSET 12
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
void hal_hardware_init(void)
{
- volatile unsigned int temp;
- volatile unsigned int esdctl0 = readl(SOC_ESDCTL_BASE);
- volatile unsigned int v;
-
- sys_ver = readl(SOC_SI_ID_REG) >> 28 ;
-
- system_rev = 0x27 << PART_NUMBER_OFFSET;
-
- switch (sys_ver) {
- case SOC_SILICONID_Rev1_0:
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- break;
- case SOC_SILICONID_Rev2_0:
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 0 << MINOR_NUMBER_OFFSET;
- break;
- case SOC_SILICONID_Rev2_1:
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET;
- system_rev |= 1 << MINOR_NUMBER_OFFSET;
- break;
- }
-
- if ((esdctl0 & 0x20000) == 0x0) {
- HAL_PLATFORM_EXTRA[11] = '1';
- HAL_PLATFORM_EXTRA[12] = '6';
- }
-
- // enable user mode SOC register accesses
- writel(1, SOC_AIPI1_BASE + SOC_AIPI_PAR_OFF);
- writel(1, SOC_AIPI2_BASE + SOC_AIPI_PAR_OFF);
-
- // Enable clko and divide it by 8
- v = readl(SOC_CRM_PCDR0);
- v |= 0xF << 22;
- writel(v, SOC_CRM_PCDR0);
- // Default for core clock
- writel(0x7, SOC_CRM_CCSR);
- // Enable clocks for FEC, GPIO, GPT2, IIM
- writel(0x06810000, SOC_CRM_PCCR0);
- // Enable clocks for UARTs, BROM, EMI, HCLK_FEC, PERCLK1, NFC
- writel(0xFC4A0408, SOC_CRM_PCCR1);
-
- // Mask all interrupts
- writel(0xFFFFFFFF, SOC_AITC_NIMASK);
-
- // Make all interrupts do IRQ and not FIQ
- writel(0, SOC_AITC_INTTYPEH);
- writel(0, SOC_AITC_INTTYPEL);
-
- // Disable all GPIO interrupt sources
-
- // Enable caches
- HAL_ICACHE_ENABLE();
- HAL_DCACHE_ENABLE();
-
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- // increase the WDOG timeout value to the max
- writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
- }
-
- // Perform any platform specific initializations
- plf_hardware_init();
-
- // Set up eCos/ROM interfaces
- hal_if_init();
-
- // init timer2 and start it -- use 32KHz clock
-
- writel(0x4, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // counter reset when timer is disabled
- writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
-
- writel(0x00008000, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // reset timer
- while((readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET) & 0x8000) != 0); // make sure reset complete
-
- writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
- writel(0, SOC_GPT2_BASE + GPT_TPRER_OFFSET);
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000100, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // free-run mode
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000008, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // 32KHz to prescaler
- temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
- writel(temp | 0x00000001, SOC_GPT2_BASE + GPT_TCTL_OFFSET); //enable timer
-
- hal_delay_us(MX_STARTUP_DELAY);
+ unsigned int temp;
+ unsigned int esdctl0 = readl(SOC_ESDCTL_BASE);
+ unsigned int v;
+
+ sys_ver = readl(SOC_SI_ID_REG) >> 28 ;
+
+ system_rev = 0x27 << PART_NUMBER_OFFSET;
+
+ switch (sys_ver) {
+ case SOC_SILICONID_Rev1_0:
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 0 << MINOR_NUMBER_OFFSET;
+ break;
+ case SOC_SILICONID_Rev2_0:
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 0 << MINOR_NUMBER_OFFSET;
+ break;
+ case SOC_SILICONID_Rev2_1:
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET;
+ system_rev |= 1 << MINOR_NUMBER_OFFSET;
+ break;
+ }
+
+ if ((esdctl0 & 0x20000) == 0x0) {
+ HAL_PLATFORM_EXTRA[11] = '1';
+ HAL_PLATFORM_EXTRA[12] = '6';
+ }
+
+ // enable user mode SOC register accesses
+ writel(1, SOC_AIPI1_BASE + SOC_AIPI_PAR_OFF);
+ writel(1, SOC_AIPI2_BASE + SOC_AIPI_PAR_OFF);
+
+ // Enable clko and divide it by 8
+ v = readl(SOC_CRM_PCDR0);
+ v |= 0xF << 22;
+ writel(v, SOC_CRM_PCDR0);
+ // Default for core clock
+ writel(0x7, SOC_CRM_CCSR);
+ // Enable clocks for FEC, GPIO, GPT2, IIM
+ writel(0x06810000, SOC_CRM_PCCR0);
+ // Enable clocks for UARTs, BROM, EMI, HCLK_FEC, PERCLK1, NFC
+ writel(0xFC4A0408, SOC_CRM_PCCR1);
+
+ // Mask all interrupts
+ writel(0xFFFFFFFF, SOC_AITC_NIMASK);
+
+ // Make all interrupts do IRQ and not FIQ
+ writel(0, SOC_AITC_INTTYPEH);
+ writel(0, SOC_AITC_INTTYPEL);
+
+ // Disable all GPIO interrupt sources
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // init timer2 and start it -- use 32KHz clock
+
+ writel(0x4, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // counter reset when timer is disabled
+ writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
+
+ writel(0x00008000, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // reset timer
+ while((readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET) & 0x8000) != 0); // make sure reset complete
+
+ writel(0x0, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // disable timer
+ writel(0, SOC_GPT2_BASE + GPT_TPRER_OFFSET);
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000100, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // free-run mode
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000008, SOC_GPT2_BASE + GPT_TCTL_OFFSET); // 32KHz to prescaler
+ temp = readl(SOC_GPT2_BASE + GPT_TCTL_OFFSET);
+ writel(temp | 0x00000001, SOC_GPT2_BASE + GPT_TCTL_OFFSET); //enable timer
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ hal_delay_us(MX_STARTUP_DELAY);
}
// -------------------------------------------------------------------------
unsigned int hal_timer_count(void)
{
- return readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
+ return readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
}
#define WDT_MAGIC_1 0x5555
//
void hal_delay_us(unsigned int usecs)
{
- unsigned long timerCount, timerCompare;
- unsigned int delayCount = (usecs * 512) / 15625;
- //diag_printf("entering mx2 hal_delay_us: %d, delaycount = %d, system_rev = %d\n\n", usecs, delayCount, system_rev);
+ unsigned long timerCount, timerCompare;
+ unsigned int delayCount = (usecs * 512) / 15625;
+ //diag_printf("entering mx2 hal_delay_us: %d, delaycount = %d, system_rev = %d\n\n", usecs, delayCount, system_rev);
- if (delayCount == 0) {
- return;
- }
+ if (delayCount == 0) {
+ return;
+ }
- // issue the service sequence instructions
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
- writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
- }
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
- writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
- timerCount = readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
-
- timerCompare = timerCount + delayCount;
+ writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+ timerCount = readl(HAL_DELAY_TIMER + GPT_TCN_OFFSET);
- writel(timerCompare, HAL_DELAY_TIMER + GPT_TCMP_OFFSET); // setup compare reg
+ timerCompare = timerCount + delayCount;
- while ((0x1 & readl(HAL_DELAY_TIMER + GPT_TSTAT_OFFSET)) == 0); // return until compare bit is set
- writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+ writel(timerCompare, HAL_DELAY_TIMER + GPT_TCMP_OFFSET); // setup compare reg
- if ((++led_on % 3000) == 0)
- BOARD_DEBUG_LED(0);
+ while ((0x1 & readl(HAL_DELAY_TIMER + GPT_TSTAT_OFFSET)) == 0); // return until compare bit is set
+ writel(0x03, HAL_DELAY_TIMER + GPT_TSTAT_OFFSET); // clear the compare status bit
+
+ if ((++led_on % 3000) == 0)
+ BOARD_DEBUG_LED(0);
}
// -------------------------------------------------------------------------
int hal_IRQ_handler(void)
{
#ifdef HAL_EXTENDED_IRQ_HANDLER
- cyg_uint32 index;
+ cyg_uint32 index;
- // Use platform specific IRQ handler, if defined
- // Note: this macro should do a 'return' with the appropriate
- // interrupt number if such an extended interrupt exists. The
- // assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
#endif
- return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}
//
void hal_interrupt_mask(int vector)
{
-// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+ // diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_MASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_MASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
}
void hal_interrupt_unmask(int vector)
{
-// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+ // diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
}
void hal_interrupt_acknowledge(int vector)
{
-// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+ // diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
#endif
- // Interrupt priorities are not configurable.
+ // Interrupt priorities are not configurable.
}
/*------------------------------------------------------------------------*/
projects / karo-tx-redboot.git / blobdiff