unified MX27, MX25, MX37 trees

[karo-tx-redboot.git] / packages / hal / arm / mx31 / var / v2_0 / include / hal_soc.h

diff --git a/packages/hal/arm/mx31/var/v2_0/include/hal_soc.h b/packages/hal/arm/mx31/var/v2_0/include/hal_soc.h
index ffa4498200b47b1ab3f27cda35e2aef3808df6ad..71b890e118193720a4572b30ed0b3628673f2aa7 100644 (file)
--- a/packages/hal/arm/mx31/var/v2_0/include/hal_soc.h
+++ b/packages/hal/arm/mx31/var/v2_0/include/hal_soc.h
@@ -72,6 +72,7 @@ extern char HAL_PLATFORM_EXTRA[];
 
 #endif /* __ASSEMBLER__ */
 
+#define IRAM_BASE_ADDR         0x1FFC0000
 /*
  * Default Memory Layout Definitions
  */
@@ -112,6 +113,7 @@ extern char HAL_PLATFORM_EXTRA[];
 #define SPBA_BASE_ADDR          0x50000000
 #define MMC_SDHC1_BASE_ADDR     0x50004000
 #define MMC_SDHC2_BASE_ADDR     0x50008000
+#define ESDHC1_REG_BASE         MMC_SDHC1_BASE_ADDR
 #define UART3_BASE_ADDR         0x5000C000
 #define CSPI2_BASE_ADDR         0x50010000
 #define SSI2_BASE_ADDR          0x50014000
@@ -164,6 +166,7 @@ extern char HAL_PLATFORM_EXTRA[];
 #define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
 #define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
 #define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
 #define M3IF_BASE               0xB8003000
 #define PCMCIA_CTL_BASE         0xB8004000
 
@@ -192,15 +195,18 @@ extern char HAL_PLATFORM_EXTRA[];
 #define AVIC_INTTYPEL                   REG32_PTR(AVIC_BASE_ADDR + (0x1C))
 
 /* L210 */
-#define L2CC_BASE_ADDR                  0x30000000
 #define L2_CACHE_LINE_SIZE              32
 #define L2_CACHE_CTL_REG                0x100
 #define L2_CACHE_AUX_CTL_REG            0x104
 #define L2_CACHE_SYNC_REG               0x730
 #define L2_CACHE_INV_LINE_REG           0x770
 #define L2_CACHE_INV_WAY_REG            0x77C
-#define L2_CACHE_CLEAN_LINE_REG         0x7B0
-#define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
+#define L2_CACHE_CLEAN_LINE_PA_REG      0x7B0
+#define L2_CACHE_CLEAN_LINE_WAY_REG     0x7B8
+#define L2_CACHE_CLEAN_WAY_REG          0x7BC
+#define L2_CACHE_CLEAN_INV_LINE_PA_REG  0x7F0
+#define L2_CACHE_CLEAN_INV_LINE_WAY_REG 0x7F8
+#define L2_CACHE_CLEAN_INV_WAY_REG      0x7FC
 
 /* CCM */
 #define CLKCTL_CCMR                     0x00
@@ -220,6 +226,22 @@ extern char HAL_PLATFORM_EXTRA[];
 //#define PLL_REF_CLK  FREQ_32768HZ
 //#define PLL_REF_CLK  FREQ_32000HZ
 
+/* MMC */
+#define ESDHC_REG_CLK                                   0x0
+#define ESDHC_REG_INT_STATUS                     0x4
+#define ESDHC_REG_CLK_RATE                         0x8
+#define ESDHC_REG_BLK_LEN                           0x18
+#define ESDHC_REG_NOB                                  0x1C
+#define ESDHC_REG_INT_STATUS_ENABLE      0x24
+#define ESDHC_REG_COMMAND                         0x28
+#define ESDHC_REG_COMMAND_TRANS_TYPE  0x2C
+#define ESDHC_REG_COMMAND_DAT_CONT      0xC
+#define ESDHC_REG_RESFIFO                           0x34
+#define ESDHC_REG_BUFFER_DATA                  0x38
+
+#define ESDHC_CLEAR_INTERRUPT                   0xffffffff
+#define ESDHC_INTERRUPT_ENABLE                 0x0000c015
+
 /* WEIM - CS0 */
 #define CSCRU                           0x00
 #define CSCRL                           0x04
@@ -298,6 +320,10 @@ extern char HAL_PLATFORM_EXTRA[];
 #define UPCTL_PARAM_240     (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
 #define UPCTL_PARAM_240_27  (((2-1) << 26) + ((9 -1) << 16) + (8  << 10) + (8  << 0))
 
+/* SPCTL                      PD             MFD              MFI          MFN */
+#define SPCTL_PARAM_399     (((1-1) << 26) + ((52-1) << 16) + (7  << 10) + (35 << 0))
+#define SPCTL_PARAM_399_27  (((1-1) << 26) + ((5-1)  << 16) + (7  << 10) + (2  << 0))
+
 /* PDR0 */
 #define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz */
 #define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
@@ -344,34 +370,46 @@ extern char HAL_PLATFORM_EXTRA[];
 #define NAND_FLASH_CONFIG2_FCMD_EN      (1 << 0)
 #define FDO_PAGE_SPARE_VAL              0x8
 
-#define MXC_NAND_BASE_DUMMY             0x00000000
-#define NOR_FLASH_BOOT                  0
+#define MXC_MMC_BASE_DUMMY              0x00000000
+
+#define NOR_FLASH_BOOT                    0
 #define NAND_FLASH_BOOT                 0x10000000
-#define SDRAM_NON_FLASH_BOOT            0x20000000
+#define SDRAM_NON_FLASH_BOOT      0x20000000
+#define MMC_BOOT                               0x40000000
 #define MXCBOOT_FLAG_REG                (AVIC_BASE_ADDR + 0x100)
-#define MXCFIS_NOTHING                  0x00000000
-#define MXCFIS_NAND                     0x10000000
-#define MXCFIS_NOR                      0x20000000
-#define MXCFIS_FLAG_REG                 (AVIC_BASE_ADDR + 0x104)
+
+#define MXCFIS_NOTHING                    0x00000000
+#define MXCFIS_NAND                          0x10000000
+#define MXCFIS_NOR                            0x20000000
+#define MXCFIS_MMC                            0x40000000
+#define MXCFIS_FLAG_REG                  (AVIC_BASE_ADDR + 0x104)
 
 #define IS_BOOTING_FROM_NAND()          (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
-#define IS_BOOTING_FROM_NOR()           (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
-#define IS_BOOTING_FROM_SDRAM()         (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR()            (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM()        (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC()           (readl(MXCBOOT_FLAG_REG) == MMC_BOOT)
 
 #ifndef MXCFLASH_SELECT_NAND
-#define IS_FIS_FROM_NAND()              0
+#define IS_FIS_FROM_NAND()             0
 #else
-#define IS_FIS_FROM_NAND()              (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#define IS_FIS_FROM_NAND()             (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
 #endif
 
 #ifndef MXCFLASH_SELECT_NOR
 #define IS_FIS_FROM_NOR()               0
 #else
-#define IS_FIS_FROM_NOR()               (!IS_FIS_FROM_NAND())
+#define IS_FIS_FROM_NOR()               (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC()               0
+#else
+#define IS_FIS_FROM_MMC()               (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
 #endif
 
 #define MXC_ASSERT_NOR_BOOT()           writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
-#define MXC_ASSERT_NAND_BOOT()          writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT()         writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT()           writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
 
 /*
  * This macro is used to get certain bit field from a number
@@ -433,11 +471,12 @@ unsigned int get_main_clock(enum main_clocks clk);
 unsigned int get_peri_clock(enum peri_clocks clk);
 
 enum {
-    MXC_NFC_V1,
-    MXC_NFC_V2,
+    BOARD_TYPE_UNKNOWN,
+    BOARD_TYPE_ADS,
+    BOARD_TYPE_3STACK,
 };
 
-typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
 
 #endif //#if !defined(__ASSEMBLER__)