#endif
#include <cyg/infra/cyg_type.h>
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_arch.h> // HAL header
-#include <cyg/hal/hal_intr.h> // HAL header
+#include <cyg/hal/hal_arch.h> // HAL header
+#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/infra/diag.h>
/*------------------------------------------------------------------------*/
-/* First level C exception handler. */
+/* First level C exception handler. */
externC void __handle_exception (void);
static void
__take_over_debug_traps(void)
{
- hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
- hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
- hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
- hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+ hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+ hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+ hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+ hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
}
static void
__restore_debug_traps(void)
{
- hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
- hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+ hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+ hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
}
#endif // !CYGPKG_CYGMON
#endif
void
exception_handler(HAL_SavedRegisters *regs)
{
- // Special case handler for code which has chosen to take care
- // of data exceptions (i.e. code which expects them to happen)
- // This is common in discovery code, e.g. checking for a particular
- // device which may generate an exception when probing if the
- // device is not present
+ // Special case handler for code which has chosen to take care
+ // of data exceptions (i.e. code which expects them to happen)
+ // This is common in discovery code, e.g. checking for a particular
+ // device which may generate an exception when probing if the
+ // device is not present
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- if (__mem_fault_handler &&
- regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
- regs->pc = (unsigned long)__mem_fault_handler;
- return; // Caught an exception inside stubs
- }
+ if (__mem_fault_handler &&
+ regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
+ regs->pc = (unsigned long)__mem_fault_handler;
+ return; // Caught an exception inside stubs
+ }
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) && !defined(CYGPKG_CYGMON)
- if (++exception_level == 1) __take_over_debug_traps();
+ if (++exception_level == 1) __take_over_debug_traps();
- _hal_registers = regs;
- __handle_exception();
+ _hal_registers = regs;
+ __handle_exception();
- if (--exception_level == 0) __restore_debug_traps();
+ if (--exception_level == 0) __restore_debug_traps();
#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
- // We should decode the vector and pass a more appropriate
- // value as the second argument. For now we simply pass a
- // pointer to the saved registers. We should also divert
- // breakpoint and other debug vectors into the debug stubs.
+ // We should decode the vector and pass a more appropriate
+ // value as the second argument. For now we simply pass a
+ // pointer to the saved registers. We should also divert
+ // breakpoint and other debug vectors into the debug stubs.
- cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
+ cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
#else
- CYG_FAIL("Exception!!!");
-
-#endif
-
- return;
+ CYG_FAIL("Exception!!!");
+
+#endif
+
+ return;
}
void hal_spurious_IRQ(HAL_SavedRegisters *regs) CYGBLD_ATTRIB_WEAK;
hal_spurious_IRQ(HAL_SavedRegisters *regs)
{
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
- exception_handler(regs);
+ exception_handler(regs);
#else
- CYG_FAIL("Spurious interrupt!!");
-#endif
+ CYG_FAIL("Spurious interrupt!!");
+#endif
}
/*------------------------------------------------------------------------*/
cyg_hal_invoke_constructors (void)
{
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
- static pfunc *p = &__CTOR_END__[-1];
-
- cyg_hal_stop_constructors = 0;
- for (; p >= __CTOR_LIST__; p--) {
- (*p) ();
- if (cyg_hal_stop_constructors) {
- p--;
- break;
- }
- }
+ static pfunc *p = &__CTOR_END__[-1];
+
+ cyg_hal_stop_constructors = 0;
+ for (; p >= __CTOR_LIST__; p--) {
+ (*p) ();
+ if (cyg_hal_stop_constructors) {
+ p--;
+ break;
+ }
+ }
#else
- pfunc *p;
+ pfunc *p;
- for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
- (*p) ();
+ for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
+ (*p) ();
#endif
}
externC cyg_uint32
hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
- CYG_TRACE1(true, "Interrupt: %d", vector);
+ CYG_TRACE1(true, "Interrupt: %d", vector);
- CYG_FAIL("Spurious Interrupt!!!");
- return 0;
+ CYG_FAIL("Spurious Interrupt!!!");
+ return 0;
}
/*-------------------------------------------------------------------------*/
void
breakpoint(void)
{
- HAL_BREAKPOINT(_breakinst);
+ HAL_BREAKPOINT(_breakinst);
}
unsigned long
__break_opcode (void)
{
- return HAL_BREAKINST;
+ return HAL_BREAKINST;
}
#endif
int
hal_lsbindex(int mask)
{
- int i;
- for (i = 0; i < 32; i++) {
- if (mask & (1<<i)) return (i);
- }
- return (-1);
+ int i;
+ for (i = 0; i < 32; i++) {
+ if (mask & (1<<i)) return (i);
+ }
+ return (-1);
}
int
hal_msbindex(int mask)
{
- int i;
- for (i = 31; i >= 0; i--) {
- if (mask & (1<<i)) return (i);
- }
- return (-1);
+ int i;
+ for (i = 31; i >= 0; i--) {
+ if (mask & (1<<i)) return (i);
+ }
+ return (-1);
}
#ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
void
dump_frame(unsigned char *frame)
{
- HAL_SavedRegisters *rp = (HAL_SavedRegisters *)frame;
- int i;
- diag_dump_buf(frame, 128);
- diag_printf("Registers:\n");
- for (i = 0; i <= 10; i++) {
- if ((i == 0) || (i == 6)) diag_printf("R%d: ", i);
- diag_printf("%08X ", rp->d[i]);
- if ((i == 5) || (i == 10)) diag_printf("\n");
- }
- diag_printf("FP: %08X, SP: %08X, LR: %08X, PC: %08X, PSR: %08X\n",
- rp->fp, rp->sp, rp->lr, rp->pc, rp->cpsr);
+ HAL_SavedRegisters *rp = (HAL_SavedRegisters *)frame;
+ int i;
+ diag_dump_buf(frame, 128);
+ diag_printf("Registers:\n");
+ for (i = 0; i <= 10; i++) {
+ if ((i == 0) || (i == 6)) diag_printf("R%d: ", i);
+ diag_printf("%08X ", rp->d[i]);
+ if ((i == 5) || (i == 10)) diag_printf("\n");
+ }
+ diag_printf("FP: %08X, SP: %08X, LR: %08X, PC: %08X, PSR: %08X\n",
+ rp->fp, rp->sp, rp->lr, rp->pc, rp->cpsr);
}
#endif
void
show_frame_in(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[IN] IRQ Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[IN] IRQ Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
void
show_frame_out(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[OUT] IRQ Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[OUT] IRQ Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
#endif
// Debug routines
void cyg_hal_report_undefined_instruction(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[UNDEFINED INSTRUCTION] Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[UNDEFINED INSTRUCTION] Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
void cyg_hal_report_software_interrupt(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[SOFTWARE INTERRUPT] Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[SOFTWARE INTERRUPT] Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
void cyg_hal_report_abort_prefetch(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[ABORT PREFETCH] Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[ABORT PREFETCH] Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
void cyg_hal_report_abort_data(HAL_SavedRegisters *frame)
{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("[ABORT DATA] Frame:\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("[ABORT DATA] Frame:\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
void cyg_hal_report_exception_handler_returned(HAL_SavedRegisters *frame)
-{
- int old;
- HAL_DISABLE_INTERRUPTS(old);
- diag_printf("Exception handler returned!\n");
- dump_frame((unsigned char *)frame);
- HAL_RESTORE_INTERRUPTS(old);
+{
+ int old;
+ HAL_DISABLE_INTERRUPTS(old);
+ diag_printf("Exception handler returned!\n");
+ dump_frame((unsigned char *)frame);
+ HAL_RESTORE_INTERRUPTS(old);
}
#endif
// Contributors: gthomas, jskov,
// Russell King <rmk@arm.linux.org.uk>
// Date: 2001-02-20
-// Purpose:
-// Description:
-//
+// Purpose:
+// Description:
+//
// This code is part of RedBoot (tm).
//
//####DESCRIPTIONEND####
// Exported CLI function(s)
static void do_exec(int argc, char *argv[]);
-RedBoot_cmd("exec",
- "Execute an image - with MMU off",
+RedBoot_cmd("exec",
+ "Execute an image - with MMU off",
"[-w timeout] [-b <load addr> [-l <length>]]\n"
" [-r <ramdisk addr> [-s <ramdisk length>]]\n"
" [-c \"kernel command line\"] [-t <target> ] [<entry_point>]",
// Default memory layout - can be overridden by platform, typically in
// <cyg/hal/plf_io.h>
#ifndef CYGHWR_REDBOOT_LINUX_ATAG_MEM
-#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
- CYG_MACRO_START \
- /* Next ATAG_MEM. */ \
- _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
- _p_->hdr.tag = ATAG_MEM; \
- /* Round up so there's only one bit set in the memory size. \
- * Don't double it if it's already a power of two, though. \
- */ \
- _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
- if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
- _p_->u.mem.size <<= 1; \
- _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
CYG_MACRO_END
#endif
// Round up a quantity to a longword (32 bit) length
#define ROUNDUP(n) (((n) + 3) & ~3)
-static void
+static void
do_exec(int argc, char *argv[])
{
unsigned long entry;
#endif
extern char __tramp_start__[], __tramp_end__[];
-#if 1
target = load_address;
entry = entry_address;
-#else
- // Default physical entry point for Linux is kernel base.
- entry = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
- target = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
-#endif
+
base_addr = load_address;
length = load_address_end - load_address;
// Round length up to the next quad word
length = (length + 3) & ~0x3;
ramdisk_size = 4096*1024;
- init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
- &wait_time, &wait_time_set, "wait timeout");
- init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
- &base_addr, &base_addr_set, "base address");
- init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
- &length, &length_set, "length");
- init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR,
- &cmd_line, &cmd_line_set, "kernel command line");
- init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM,
- &ramdisk_addr, &ramdisk_addr_set, "ramdisk_addr");
- init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
- &ramdisk_size, &ramdisk_size_set, "ramdisk_size");
+ init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
+ &wait_time, &wait_time_set, "wait timeout");
+ init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
+ &base_addr, &base_addr_set, "base address");
+ init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
+ &length, &length_set, "length");
+ init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR,
+ &cmd_line, &cmd_line_set, "kernel command line");
+ init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM,
+ &ramdisk_addr, &ramdisk_addr_set, "ramdisk_addr");
+ init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
+ &ramdisk_size, &ramdisk_size_set, "ramdisk_size");
init_opts(&opts[6], 't', true, OPTION_ARG_TYPE_NUM,
- &target, 0, "[physical] target address");
+ &target, 0, "[physical] target address");
num_opts = 7;
#ifdef CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
- init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG,
- &swap_endian, 0, "swap endianness");
+ init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG,
+ &swap_endian, 0, "swap endianness");
++num_opts;
#endif
if (!scan_opts(argc, argv, 1, opts, num_opts, &entry,
// Set up parameters to pass to kernel
// CORE tag must be present & first
- params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header))/sizeof(long);
+ params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header)) / sizeof(long);
params->hdr.tag = ATAG_CORE;
params->u.core.flags = 0;
params->u.core.pagesize = 0;
params = (struct tag *)((long *)params + params->hdr.size);
if (ramdisk_addr_set) {
- params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header))/sizeof(long);
+ params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header)) / sizeof(long);
params->hdr.tag = ATAG_INITRD2;
params->u.initrd.start = CYGARC_PHYSICAL_ADDRESS(ramdisk_addr);
params->u.initrd.size = ramdisk_size;
// memory map possibly convoluted from 1-1. The trampoline code
// between labels __tramp_start__ and __tramp_end__ must be copied
// to RAM and then executed at the non-mapped address.
- //
+ //
// This magic was created in order to be able to execute standard
// Linux kernels with as little change/perturberance as possible.
" mov r2,%6;\n" // Kernel parameters
" mov pc,%0;\n" // Jump to kernel
"__xtramp_end__:\n"
- : :
+ : :
"r"(entry),
"r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
"r"(length),
" mov r2,%6;\n" // Kernel parameters
" mov pc,%0;\n" // Jump to kernel
"__tramp_end__:\n"
- : :
+ : :
"r"(entry),
"r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
"r"(length),
: "r0", "r1"
);
}
-
+
#endif // HAL_PLATFORM_MACHINE_TYPE - otherwise we do not support this stuff...
// EOF redboot_linux_exec.c
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
-//
+//
//
//####DESCRIPTIONEND####
//
// Cache dimensions
#if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
-# define HAL_ICACHE_SIZE 0x4000
-# define HAL_ICACHE_LINE_SIZE 32
-# define HAL_ICACHE_WAYS 64
+# define HAL_ICACHE_SIZE 0x4000
+# define HAL_ICACHE_LINE_SIZE 32
+# define HAL_ICACHE_WAYS 64
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0x4000
-# define HAL_DCACHE_LINE_SIZE 32
-# define HAL_DCACHE_WAYS 64
+# define HAL_DCACHE_SIZE 0x4000
+# define HAL_DCACHE_LINE_SIZE 32
+# define HAL_DCACHE_WAYS 64
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 64
+# define HAL_WRITE_BUFFER 64
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
-# define HAL_ICACHE_SIZE 0x2000
-# define HAL_ICACHE_LINE_SIZE 32
-# define HAL_ICACHE_WAYS 64
+# define HAL_ICACHE_SIZE 0x2000
+# define HAL_ICACHE_LINE_SIZE 32
+# define HAL_ICACHE_WAYS 64
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0x2000
-# define HAL_DCACHE_LINE_SIZE 32
-# define HAL_DCACHE_WAYS 64
+# define HAL_DCACHE_SIZE 0x2000
+# define HAL_DCACHE_LINE_SIZE 32
+# define HAL_DCACHE_WAYS 64
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 64
+# define HAL_WRITE_BUFFER 64
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
-# define HAL_ICACHE_SIZE 0x4000
-# define HAL_ICACHE_LINE_SIZE 16
-# define HAL_ICACHE_WAYS 2
+# define HAL_ICACHE_SIZE 0x4000
+# define HAL_ICACHE_LINE_SIZE 16
+# define HAL_ICACHE_WAYS 2
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0x2000
-# define HAL_DCACHE_LINE_SIZE 16
-# define HAL_DCACHE_WAYS 2
+# define HAL_DCACHE_SIZE 0x2000
+# define HAL_DCACHE_LINE_SIZE 16
+# define HAL_DCACHE_WAYS 2
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 64
+# define HAL_WRITE_BUFFER 64
// must flush everything manually
-# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
+# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
-# define HAL_ICACHE_SIZE 0x4000
-# define HAL_ICACHE_LINE_SIZE 32
-# define HAL_ICACHE_WAYS 4
+# define HAL_ICACHE_SIZE 0x4000
+# define HAL_ICACHE_LINE_SIZE 32
+# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0x2000
-# define HAL_DCACHE_LINE_SIZE 32
-# define HAL_DCACHE_WAYS 4
+# define HAL_DCACHE_SIZE 0x2000
+# define HAL_DCACHE_LINE_SIZE 32
+# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 64
+# define HAL_WRITE_BUFFER 64
#define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
-# define HAL_ICACHE_SIZE 0x1000
-# define HAL_ICACHE_LINE_SIZE 16
-# define HAL_ICACHE_WAYS 4
+# define HAL_ICACHE_SIZE 0x1000
+# define HAL_ICACHE_LINE_SIZE 16
+# define HAL_ICACHE_WAYS 4
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0x1000
-# define HAL_DCACHE_LINE_SIZE 16
-# define HAL_DCACHE_WAYS 4
+# define HAL_DCACHE_SIZE 0x1000
+# define HAL_DCACHE_LINE_SIZE 16
+# define HAL_DCACHE_WAYS 4
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 32
+# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x10
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
#elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
-# define HAL_ICACHE_SIZE 0
-# define HAL_ICACHE_LINE_SIZE 0
-# define HAL_ICACHE_WAYS 0
+# define HAL_ICACHE_SIZE 0
+# define HAL_ICACHE_LINE_SIZE 0
+# define HAL_ICACHE_WAYS 0
# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
-# define HAL_DCACHE_SIZE 0
-# define HAL_DCACHE_LINE_SIZE 0
-# define HAL_DCACHE_WAYS 0
+# define HAL_DCACHE_SIZE 0
+# define HAL_DCACHE_LINE_SIZE 0
+# define HAL_DCACHE_WAYS 0
# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
-# define HAL_WRITE_BUFFER 32
+# define HAL_WRITE_BUFFER 32
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0
// FIXME: disable/enable instruction streaming?
// Enable the instruction cache
-#define HAL_ICACHE_ENABLE() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15,0,r1,c1,c0,0;" \
- "orr r1,r1,#0x1000;" \
- "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
- /* that MMU and alignment faults */ \
- /* are enabled) */ \
- "mcr p15,0,r1,c1,c0,0" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_ICACHE_ENABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "orr r1,r1,#0x1000;" \
+ "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
+ /* that MMU and alignment faults */ \
+ /* are enabled) */ \
+ "mcr p15,0,r1,c1,c0,0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Disable the instruction cache (and invalidate it, required semanitcs)
-#define HAL_ICACHE_DISABLE() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15,0,r1,c1,c0,0;" \
- "bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
- "mcr p15,0,r1,c1,c0,0;" \
- "mov r1,#0;" \
- "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
- "nop;" /* next few instructions may be via cache */ \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_ICACHE_DISABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
+ "mcr p15,0,r1,c1,c0,0;" \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Query the state of the instruction cache
-#define HAL_ICACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- register cyg_uint32 reg; \
- asm volatile ("mrc p15,0,%0,c1,c0,0" \
- : "=r"(reg) \
- : \
- ); \
- (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ("mrc p15,0,%0,c1,c0,0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
CYG_MACRO_END
// Invalidate the entire cache
-#define HAL_ICACHE_INVALIDATE_ALL() \
-CYG_MACRO_START \
- /* this macro can discard dirty cache lines (N/A for ICache) */ \
- asm volatile ( \
- "mov r1,#0;" \
- "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
- "mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
- "nop;" /* next few instructions may be via cache */ \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_ICACHE_INVALIDATE_ALL() \
+CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
+ "mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Synchronize the contents of the cache with memory.
// (which includes flushing out pending writes)
-#define HAL_ICACHE_SYNC() \
-CYG_MACRO_START \
- HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
- HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+#define HAL_ICACHE_SYNC() \
+CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
CYG_MACRO_END
#else
#if HAL_DCACHE_SIZE != 0
// Enable the data cache
-#define HAL_DCACHE_ENABLE() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15,0,r1,c1,c0,0;" \
- "orr r1,r1,#0x000F;" /* enable DCache (also ensures */ \
- /* the MMU, alignment faults, and */ \
- /* write buffer are enabled) */ \
- "mcr p15,0,r1,c1,c0,0" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_DCACHE_ENABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "orr r1,r1,#0x000F;" /* enable DCache (also ensures */ \
+ /* the MMU, alignment faults, and */ \
+ /* write buffer are enabled) */ \
+ "mcr p15,0,r1,c1,c0,0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Disable the data cache (and invalidate it, required semanitcs)
-#define HAL_DCACHE_DISABLE() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15,0,r1,c1,c0,0;" \
- "bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \
- /* but not MMU and alignment faults */ \
- "mcr p15,0,r1,c1,c0,0;" \
- "mov r1,#0;" \
- "mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_DCACHE_DISABLE() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15,0,r1,c1,c0,0;" \
+ "bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \
+ /* but not MMU and alignment faults */ \
+ "mcr p15,0,r1,c1,c0,0;" \
+ "mov r1,#0;" \
+ "mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Query the state of the data cache
-#define HAL_DCACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- register int reg; \
- asm volatile ("mrc p15,0,%0,c1,c0,0;" \
- : "=r"(reg) \
- : \
- ); \
- (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+CYG_MACRO_START \
+ register int reg; \
+ asm volatile ("mrc p15,0,%0,c1,c0,0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
CYG_MACRO_END
// Flush the entire dcache (and then both TLBs, just in case)
-#define HAL_DCACHE_INVALIDATE_ALL() \
-CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
- asm volatile ( \
- "mov r0,#0;" \
- "mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
- "mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
- : \
- : \
- : "r0","memory" /* clobber list */); \
+#define HAL_DCACHE_INVALIDATE_ALL() \
+CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
+ asm volatile ( \
+ "mov r0,#0;" \
+ "mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
+ "mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
+ : \
+ : \
+ : "r0","memory" /* clobber list */); \
CYG_MACRO_END
// Synchronize the contents of the cache with memory.
#ifdef CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE
-#define HAL_DCACHE_SYNC() \
-CYG_MACRO_START \
- asm volatile ( \
- "mov r0, #0;" \
- "mcr p15,0,r0,c7,c10,0;" /* clean DCache */ \
- "1: mrc p15,0,r0,c15,c4,0;" /* wait for dirty flag to clear */ \
- "ands r0,r0,#0x80000000;" \
- "bne 1b;" \
- "mov r0,#0;" \
- "mcr p15,0,r0,c7,c6,0;" /* flush DCache */ \
- "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
- : \
- : \
- : "r0" /* Clobber list */ \
- ); \
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "mov r0, #0;" \
+ "mcr p15,0,r0,c7,c10,0;" /* clean DCache */ \
+ "1: mrc p15,0,r0,c15,c4,0;" /* wait for dirty flag to clear */ \
+ "ands r0,r0,#0x80000000;" \
+ "bne 1b;" \
+ "mov r0,#0;" \
+ "mcr p15,0,r0,c7,c6,0;" /* flush DCache */ \
+ "mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
CYG_MACRO_END
#elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
-#define HAL_DCACHE_SYNC() \
-CYG_MACRO_START \
- cyg_uint32 _tmp1, _tmp2; \
- asm volatile ( \
- "mov %0, #0;" \
- "1: " \
- "mov %1, #0;" \
- "2: " \
- "orr r0,%0,%1;" \
- "mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
- "add %1,%1,%2;" \
- "cmp %1,%3;" \
- "bne 2b;" \
- "add %0,%0,#0x04000000;" /* get to next index */ \
- "cmp %0,#0;" \
- "bne 1b;" \
- "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
- : "=r" (_tmp1), "=r" (_tmp2) \
- : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
- "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
- : "r0" /* Clobber list */ \
- ); \
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ cyg_uint32 _tmp1, _tmp2; \
+ asm volatile ( \
+ "mov %0, #0;" \
+ "1: " \
+ "mov %1, #0;" \
+ "2: " \
+ "orr r0,%0,%1;" \
+ "mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
+ "add %1,%1,%2;" \
+ "cmp %1,%3;" \
+ "bne 2b;" \
+ "add %0,%0,#0x04000000;" /* get to next index */ \
+ "cmp %0,#0;" \
+ "bne 1b;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : "=r" (_tmp1), "=r" (_tmp2) \
+ : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
+ "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
+ : "r0" /* Clobber list */ \
+ ); \
CYG_MACRO_END
#elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE)
/*
* 'Clean & Invalidate whole DCache'
*/
-#define HAL_DCACHE_SYNC() \
-CYG_MACRO_START \
- asm volatile ( \
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
"mov r0, #255 << 4;" /* 256 entries/set */ \
- "2: " \
+ "2: " \
"mcr p15, 0, r0, c7, c14, 2;" \
"subs r0, r0, #1 << 4;" \
"bcs 2b;" /* entries 255 to 0 */ \
- "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
- : \
- : \
- : "r0" /* Clobber list */ \
- ); \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
CYG_MACRO_END
#elif defined(CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE)
/*
* 'Clean & Invalidate whole DCache'
*/
-#define HAL_DCACHE_SYNC() \
-CYG_MACRO_START \
- asm volatile ( \
- "1: " /* clean & invalidate D index */ \
+#define HAL_DCACHE_SYNC() \
+CYG_MACRO_START \
+ asm volatile ( \
+ "1: " /* clean & invalidate D index */ \
"mrc p15, 0, r15, c7, c14, 3;" \
- "bne 1b;" \
- "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
- : \
- : \
- : "r0" /* Clobber list */ \
- ); \
+ "bne 1b;" \
+ "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
CYG_MACRO_END
#else
# error "Don't know how to sync Dcache"
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
-#define HAL_DCACHE_WRITETHRU_MODE 0
-#define HAL_DCACHE_WRITEBACK_MODE 1
+#define HAL_DCACHE_WRITETHRU_MODE 0
+#define HAL_DCACHE_WRITEBACK_MODE 1
// Get the current writeback mode - or only writeback mode if fixed
-#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
- _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
+#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
+ _mode_ = HAL_DCACHE_WRITEBACK_MODE; \
CYG_MACRO_END
// Load the contents of the given address range into the data cache
// ---- this seems not to work despite the documentation ---
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
//CYG_MACRO_START
-// HAL_DCACHE_STORE( _base_ , _size_ );
-// HAL_DCACHE_INVALIDATE( _base_ , _size_ );
+// HAL_DCACHE_STORE( _base_ , _size_ );
+// HAL_DCACHE_INVALIDATE( _base_ , _size_ );
//CYG_MACRO_END
// Invalidate cache lines in the given range without writing to memory.
// ---- this seems not to work despite the documentation ---
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
//CYG_MACRO_START
-// register int addr, enda;
-// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
-// enda = (int)(_base_) + (_size_);
-// addr < enda ;
-// addr += HAL_DCACHE_LINE_SIZE )
-// {
-// asm volatile (
-// "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
-// :
-// : "r"(addr)
-// : "memory"
-// );
-// }
+// register int addr, enda;
+// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+// enda = (int)(_base_) + (_size_);
+// addr < enda ;
+// addr += HAL_DCACHE_LINE_SIZE )
+// {
+// asm volatile (
+// "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
+// :
+// : "r"(addr)
+// : "memory"
+// );
+// }
//CYG_MACRO_END
-
+
// Write dirty cache lines to memory for the given address range.
// ---- this seems not to work despite the documentation ---
//#define HAL_DCACHE_STORE( _base_ , _size_ )
//CYG_MACRO_START
-// register int addr, enda;
-// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
-// enda = (int)(_base_) + (_size_);
-// addr < enda ;
-// addr += HAL_DCACHE_LINE_SIZE )
-// {
-// asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */
-// :
-// : "r"(addr)
-// : "memory"
-// );
-// }
+// register int addr, enda;
+// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+// enda = (int)(_base_) + (_size_);
+// addr < enda ;
+// addr += HAL_DCACHE_LINE_SIZE )
+// {
+// asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */
+// :
+// : "r"(addr)
+// : "memory"
+// );
+// }
//CYG_MACRO_END
// Preread the given range into the cache with the intention of reading
// Cache controls for safely disabling/reenabling caches around execution
// of relocated code.
-#define HAL_FLASH_CACHES_OFF(_d_, _i_) \
- CYG_MACRO_START \
- HAL_ICACHE_IS_ENABLED(_i_); \
- HAL_DCACHE_IS_ENABLED(_d_); \
- HAL_ICACHE_INVALIDATE_ALL(); \
- HAL_ICACHE_DISABLE(); \
- HAL_DCACHE_SYNC(); \
- HAL_DCACHE_INVALIDATE_ALL(); \
- HAL_DCACHE_DISABLE(); \
- CYG_MACRO_END
-
-#define HAL_FLASH_CACHES_ON(_d_, _i_) \
- CYG_MACRO_START \
- if (_d_) HAL_DCACHE_ENABLE(); \
- if (_i_) HAL_ICACHE_ENABLE(); \
- CYG_MACRO_END
+#define HAL_FLASH_CACHES_OFF(_d_, _i_) \
+ CYG_MACRO_START \
+ HAL_ICACHE_IS_ENABLED(_i_); \
+ HAL_DCACHE_IS_ENABLED(_d_); \
+ HAL_ICACHE_INVALIDATE_ALL(); \
+ HAL_ICACHE_DISABLE(); \
+ HAL_DCACHE_SYNC(); \
+ HAL_DCACHE_INVALIDATE_ALL(); \
+ HAL_DCACHE_DISABLE(); \
+ CYG_MACRO_END
+
+#define HAL_FLASH_CACHES_ON(_d_, _i_) \
+ CYG_MACRO_START \
+ if (_d_) HAL_DCACHE_ENABLE(); \
+ if (_i_) HAL_ICACHE_ENABLE(); \
+ CYG_MACRO_END
//-----------------------------------------------------------------------------
// Virtual<->Physical translations
NAND_Copy_Main_done:
Normal_Boot_Continue:
- bl jump_to_sdram
+// bl jump_to_sdram
// Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
-Now_in_SDRAM:
- LED_BLINK #3
-
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
/* Copy image from flash to SDRAM first */
ldr r0, =0xFFFFF000
ble 1b
bl jump_to_sdram
+Now_in_SDRAM:
+ LED_BLINK #3
#endif /* CYG_HAL_STARTUP_ROMRAM */
HWInitialise_skip_SDRAM_copy:
// Get the pagesize for a particular virtual address:
// This does not depend on the vaddr.
-#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START \
- (pagesize) = SZ_1M; \
+#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
CYG_MACRO_END
// Get the physical address from a virtual address:
#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
- cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
- if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
- _v_ += 0xA00u * SZ_1M; \
- else /* Rest of it */ \
- /* no change */ ; \
- (paddr) = _v_; \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += 0xA00u * SZ_1M; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
CYG_MACRO_END
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ if(virt < 0x08000000) {
+ return virt|0xA0000000;
+ }
+ if((virt & 0xF0000000) == 0xA0000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0xA0000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
+}
+
//---------------------------------------------------------------------------
#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSI/ATA Registers */
- X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
// X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
X_ARM_MMU_SECTION(0xD40, 0xD40, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4 for External I/O */
X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS5 PSRAM */
{
/* GPIOs to set up for TX27/Starterkit-5:
Function GPIO Dir act. FCT
- Lvl
+ Lvl
FEC_RESET PB30 OUT LOW GPIO
FEC_ENABLE PB27 OUT HIGH GPIO
OSCM26_ENABLE PB22 OUT HIGH GPIO
#define SOC_I2C2_BASE UL(0x1001D000)
/* Address offsets of the I2C registers */
-#define MXC_IADR 0x00 /* Address Register */
-#define MXC_IFDR 0x04 /* Freq div register */
-#define MXC_I2CR 0x08 /* Control regsiter */
-#define MXC_I2SR 0x0C /* Status register */
-#define MXC_I2DR 0x10 /* Data I/O register */
+#define MXC_IADR 0x00 /* Address Register */
+#define MXC_IFDR 0x04 /* Freq div register */
+#define MXC_I2CR 0x08 /* Control regsiter */
+#define MXC_I2SR 0x0C /* Status register */
+#define MXC_I2DR 0x10 /* Data I/O register */
/* Bit definitions of I2CR */
-#define MXC_I2CR_IEN 0x0080
-#define MXC_I2CR_IIEN 0x0040
-#define MXC_I2CR_MSTA 0x0020
-#define MXC_I2CR_MTX 0x0010
-#define MXC_I2CR_TXAK 0x0008
-#define MXC_I2CR_RSTA 0x0004
+#define MXC_I2CR_IEN 0x0080
+#define MXC_I2CR_IIEN 0x0040
+#define MXC_I2CR_MSTA 0x0020
+#define MXC_I2CR_MTX 0x0010
+#define MXC_I2CR_TXAK 0x0008
+#define MXC_I2CR_RSTA 0x0004
/* Bit definitions of I2SR */
-#define MXC_I2SR_ICF 0x0080
-#define MXC_I2SR_IAAS 0x0040
-#define MXC_I2SR_IBB 0x0020
-#define MXC_I2SR_IAL 0x0010
-#define MXC_I2SR_SRW 0x0004
-#define MXC_I2SR_IIF 0x0002
-#define MXC_I2SR_RXAK 0x0001
+#define MXC_I2SR_ICF 0x0080
+#define MXC_I2SR_IAAS 0x0040
+#define MXC_I2SR_IBB 0x0020
+#define MXC_I2SR_IAL 0x0010
+#define MXC_I2SR_SRW 0x0004
+#define MXC_I2SR_IIF 0x0002
+#define MXC_I2SR_RXAK 0x0001
#define LP3972_SLAVE_ADDR 0x34
if ((fuse | mac_addr[i]) != mac_addr[i]) {
diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
- i, fuse, mac_addr[i]);
+ i, fuse, mac_addr[i]);
return -1;
}
if (fuse != mac_addr[i]) {
}
if (fuse_blow(0, i + 5, bit)) {
diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
- i, bit);
+ i, bit);
ret = -1;
goto out;
}
/*
* Translation Table Base Bit Masks
*/
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
/*
* Domain Access Control Bit Masks
*/
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id : 2;
- unsigned int sbz : 30;
+ unsigned int id : 2;
+ unsigned int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id : 2;
- unsigned int imp : 2;
- unsigned int domain : 4;
- unsigned int sbz : 1;
- unsigned int base_address : 23;
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id : 2;
- unsigned int b : 1;
- unsigned int c : 1;
- unsigned int imp : 1;
- unsigned int domain : 4;
- unsigned int sbz0 : 1;
- unsigned int ap : 2;
- unsigned int sbz1 : 8;
- unsigned int base_address : 12;
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id : 2;
- unsigned int sbz : 30;
+ unsigned int id : 2;
+ unsigned int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- CYG_MACRO_START \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- CYG_MACRO_END
-
-#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
- { int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--,j++,k++) \
- { \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- } \
- }
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = (cacheable); \
+ desc.section.b = (bufferable); \
+ desc.section.ap = (perm); \
+ desc.section.base_address = (actual_base); \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+ = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ { int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--,j++,k++) \
+ { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ }
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
/*
* Initialization for the Domain Access Control Register
*/
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15) )
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
+#if 0
/*
* translate the virtual address of ram space to physical address
* It is dependent on the implementation of hal_mmu_init
*/
static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
{
- if(virt < 0x08000000) {
- return virt|0xA0000000;
- }
- if((virt & 0xF0000000) == 0xA0000000) {
- return virt&(~0x08000000);
- }
- return virt;
+ if(virt < 0x08000000) {
+ return virt|0xA0000000;
+ }
+ if((virt & 0xF0000000) == 0xA0000000) {
+ return virt&(~0x08000000);
+ }
+ return virt;
}
/*
*/
static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
{
- /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
- if((phy & 0xF0000000) == 0xA0000000) {
- phy |= 0x08000000;
- }
- return phy;
+ /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+ if((phy & 0xF0000000) == 0xA0000000) {
+ phy |= 0x08000000;
+ }
+ return phy;
}
+#endif
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
#define UL(a) (a##UL)
-extern char HAL_PLATFORM_EXTRA[];
+extern char HAL_PLATFORM_EXTRA[20];
#define REG8_VAL(a) ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#define REG32_VAL(a) ((unsigned int)(a))
#include <redboot.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/plf_mmap.h>
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
#include <cyg/hal/hal_cache.h>
-typedef unsigned long long u64;
-typedef unsigned int u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
-
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 //actual pd+1
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 6 // See TLSbo80174
-#define PLL_MFD_MAX 1024 //actual mfd+1
-#define PLL_MFN_MAX 1022
-#define PLL_MFN_MAX_2 510
-#define PRESC_MAX 8
-#define IPG_DIV_MAX 2
-#define AHB_DIV_MAX 16
-#define ARM_DIV_MAX 4
-
-#define CPLM_SETUP 0
-
-#define PLL_FREQ_MAX (2 * PLL_REF_CLK * PLL_MFI_MAX)
-#define PLL_FREQ_MIN ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
-#define AHB_CLK_MAX 133333333
-#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 33333333
-
-#define ERR_WRONG_CLK -1
-#define ERR_NO_MFI -2
-#define ERR_NO_MFN -3
-#define ERR_NO_PD -4
-#define ERR_NO_PRESC -5
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 6 // See TLSbo80174
+#define PLL_MFD_MAX 1024 //actual mfd+1
+#define PLL_MFN_MAX 1022
+#define PLL_MFN_MAX_2 510
+#define PRESC_MAX 8
+#define IPG_DIV_MAX 2
+#define AHB_DIV_MAX 16
+#define ARM_DIV_MAX 4
+
+#define CPLM_SETUP 0
+
+#define PLL_FREQ_MAX (2 * PLL_REF_CLK * PLL_MFI_MAX)
+#define PLL_FREQ_MIN ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 33333333
+
+#define ERR_WRONG_CLK -1
+#define ERR_NO_MFI -2
+#define ERR_NO_MFN -3
+#define ERR_NO_PD -4
+#define ERR_NO_PRESC -5
u32 pll_clock(enum plls pll);
u32 get_main_clock(enum main_clocks clk);
#define MXC_PERCLK_NUM 4
RedBoot_cmd("clock",
- "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
- "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
-If a divider is zero or no divider is specified, the optimal divider values \n\
-will be chosen. Examples:\n\
- [clock] -> Show various clocks\n\
- [clock 266] -> Core=266 AHB=133 IPG=66.5\n\
- [clock 350] -> Core=350 AHB=117 IPG=58.5\n\
- [clock 266:4] -> Core=266 AHB=66.5(Core/4) IPG=66.5\n\
- [clock 266:4:2] -> Core=266 AHB=66.5(Core/4) IPG=33.25(AHB/2)\n",
- clock_setup
- );
+ "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+ "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]]\n\n"
+ "If a divider is zero or no divider is specified, the optimum divider values\n"
+ "will be chosen. Examples:\n"
+ " [clock] -> Show various clocks\n"
+ " [clock 266] -> Core=266 AHB=133 IPG=66.5\n"
+ " [clock 350] -> Core=350 AHB=117 IPG=58.5\n"
+ " [clock 266:4] -> Core=266 AHB=66.5(Core/4) IPG=66.5\n"
+ " [clock 266:4:2] -> Core=266 AHB=66.5(Core/4) IPG=33.25(AHB/2)\n",
+ clock_setup
+ );
/*!
* This is to calculate various parameters based on reference clock and
* @return 0 if successful; non-zero otherwise.
*/
int calc_pll_params(u32 ref, u32 target, int *p_pd,
- int *p_mfi, int *p_mfn, int *p_mfd)
+ int *p_mfi, int *p_mfn, int *p_mfd)
{
- int pd, mfi, mfn;
- u64 n_target = target, n_ref = ref;
-
- if (g_clock_src == FREQ_26MHZ) {
- pll_mfd_fixed = 26 * 16;
- } else if (g_clock_src == FREQ_27MHZ) {
- pll_mfd_fixed = 27 * 16;
- } else {
- pll_mfd_fixed = 512;
- }
+ int pd, mfi, mfn;
+ u64 n_target = target, n_ref = ref;
- // Make sure targeted freq is in the valid range. Otherwise the
- // following calculation might be wrong!!!
- if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
- return ERR_WRONG_CLK;
- }
- // Use n_target and n_ref to avoid overflow
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- mfi = (n_target * pd) / (2 * n_ref);
- if (mfi > PLL_MFI_MAX) {
- return ERR_NO_MFI;
- } else if (mfi < PLL_MFI_MIN) {
- continue;
+ if (g_clock_src == FREQ_26MHZ) {
+ pll_mfd_fixed = 26 * 16;
+ } else if (g_clock_src == FREQ_27MHZ) {
+ pll_mfd_fixed = 27 * 16;
+ } else {
+ pll_mfd_fixed = 512;
}
- break;
- }
- // Now got pd and mfi already
- mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
- // Check mfn within limit and mfn < denominator
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
- return ERR_NO_MFN;
+
+ // Make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
+ return ERR_WRONG_CLK;
}
- } else {
- if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
- return ERR_NO_MFN;
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (2 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < PLL_MFI_MIN) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
+ // Check mfn within limit and mfn < denominator
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
+ return ERR_NO_MFN;
+ }
+ } else {
+ if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
+ return ERR_NO_MFN;
+ }
}
- }
- if (pd > PLL_PD_MAX) {
- return ERR_NO_PD;
- }
- *p_pd = pd;
- *p_mfi = mfi;
- *p_mfn = mfn;
- *p_mfd = pll_mfd_fixed;
- return 0;
+ if (pd > PLL_PD_MAX) {
+ return ERR_NO_PD;
+ }
+ *p_pd = pd;
+ *p_mfi = mfi;
+ *p_mfn = mfn;
+ *p_mfd = pll_mfd_fixed;
+ return 0;
}
static u32 per_clk_old[MXC_PERCLK_NUM];
#define CMD_CLOCK_DEBUG
int configure_clock(u32 ref, u32 core_clk, u32 ahb_div, u32 ipg_div)
{
- u32 pll, presc = 1;
- int pd, mfi, mfn, mfd;
- u32 cscr, mpctl0;
- u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
- u32 per_div[MXC_PERCLK_NUM];
- int ret, i, arm_src = 0;
-
- per_clk_old[0] = get_peri_clock(PER_CLK1);
- per_clk_old[1] = get_peri_clock(PER_CLK2);
- per_clk_old[2] = get_peri_clock(PER_CLK3);
- per_clk_old[3] = get_peri_clock(PER_CLK4);
-diag_printf("per1=%9u\n", per_clk_old[0]);
-diag_printf("per2=%9u\n", per_clk_old[1]);
-diag_printf("per3=%9u\n", per_clk_old[2]);
-diag_printf("per4=%9u\n", per_clk_old[3]);
- // assume pll default to core clock first
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- pll = core_clk;
- nfc_div_factor = 1;
- } else {
- if (core_clk > 266 * SZ_DEC_1M) {
- pll = core_clk;
- arm_src = 1;
+ u32 pll, presc = 1;
+ int pd, mfi, mfn, mfd;
+ u32 cscr, mpctl0;
+ u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
+ u32 per_div[MXC_PERCLK_NUM];
+ int ret, i, arm_src = 0;
+
+ per_clk_old[0] = get_peri_clock(PER_CLK1);
+ per_clk_old[1] = get_peri_clock(PER_CLK2);
+ per_clk_old[2] = get_peri_clock(PER_CLK3);
+ per_clk_old[3] = get_peri_clock(PER_CLK4);
+ diag_printf("per1=%9u\n", per_clk_old[0]);
+ diag_printf("per2=%9u\n", per_clk_old[1]);
+ diag_printf("per3=%9u\n", per_clk_old[2]);
+ diag_printf("per4=%9u\n", per_clk_old[3]);
+ // assume pll default to core clock first
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ pll = core_clk;
+ nfc_div_factor = 1;
} else {
- pll = core_clk * 3 / 2;
+ if (core_clk > 266 * SZ_DEC_1M) {
+ pll = core_clk;
+ arm_src = 1;
+ } else {
+ pll = core_clk * 3 / 2;
+ }
+ nfc_div_factor = ahb_div;
}
- nfc_div_factor = ahb_div;
- }
- // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
- // Otherwise, need to calculate presc value below and adjust the targeted pll
- if (pll < PLL_FREQ_MIN) {
- int presc_max;
+ // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
+ // Otherwise, need to calculate presc value below and adjust the targeted pll
+ if (pll < PLL_FREQ_MIN) {
+ int presc_max;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- presc_max = PRESC_MAX;
- } else {
- presc_max = ARM_DIV_MAX;
- }
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ presc_max = PRESC_MAX;
+ } else {
+ presc_max = ARM_DIV_MAX;
+ }
- for (presc = 1; presc <= presc_max; presc++) {
- if (pll * presc > PLL_FREQ_MIN) {
- break;
- }
- }
- if (presc == presc_max + 1) {
- diag_printf("can't make presc=%d\n", presc);
- return ERR_NO_PRESC;
- }
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- pll = core_clk * presc;
- } else {
- pll = 3 * core_clk * presc / 2;
+ for (presc = 1; presc <= presc_max; presc++) {
+ if (pll * presc > PLL_FREQ_MIN) {
+ break;
+ }
+ }
+ if (presc == presc_max + 1) {
+ diag_printf("can't make presc=%d\n", presc);
+ return ERR_NO_PRESC;
+ }
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ pll = core_clk * presc;
+ } else {
+ pll = 3 * core_clk * presc / 2;
+ }
}
- }
- // pll is now the targeted pll output. Use it along with ref input clock
- // to get pd, mfi, mfn, mfd
- if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
+ // pll is now the targeted pll output. Use it along with ref input clock
+ // to get pd, mfi, mfn, mfd
+ if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
#ifdef CMD_CLOCK_DEBUG
- diag_printf("can't find pll parameters: %d\n", ret);
+ diag_printf("can't find pll parameters: %d\n", ret);
#endif
- return ret;
- }
+ return ret;
+ }
#ifdef CMD_CLOCK_DEBUG
- diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- ref, pll, pd, mfi, mfn, mfd);
+ diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ ref, pll, pd, mfi, mfn, mfd);
#endif
- // blindly increase divider first to avoid too fast ahbclk and ipgclk
- // in case the core clock increases too much
- cscr = readl(SOC_CRM_CSCR);
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
- cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
- } else {
- if (core_clk > 266 * SZ_DEC_1M) {
- hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+ // blindly increase divider first to avoid too fast ahbclk and ipgclk
+ // in case the core clock increases too much
+ cscr = readl(SOC_CRM_CSCR);
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+ cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
} else {
- hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
+ if (core_clk > 266 * SZ_DEC_1M) {
+ hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+ } else {
+ hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
+ }
+ cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
}
- cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
- }
- writel(cscr, SOC_CRM_CSCR);
-
- // update PLL register
- if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
- writel(1 << 6, SOC_CRM_MPCTL1);
-
- mpctl0 = readl(SOC_CRM_MPCTL0);
- mpctl0 = (mpctl0 & 0xC000C000) |
- CPLM_SETUP |
- ((pd - 1) << 26) |
- ((mfd - 1) << 16) |
- (mfi << 10) |
- mfn;
- writel(mpctl0, SOC_CRM_MPCTL0);
-
- // restart mpll
- writel((cscr | (1 << 18)), SOC_CRM_CSCR);
- // check the LF bit to insure lock
- while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
- // have to add some delay for new values to take effect
- for (i = 0; i < 100000; i++);
-
- // PLL locked already so use the new divider values
- cscr = readl(SOC_CRM_CSCR);
- cscr &= ~0x0000FF00;
-
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
- } else {
- cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
- }
- writel(cscr, SOC_CRM_CSCR);
+ writel(cscr, SOC_CRM_CSCR);
+
+ // update PLL register
+ if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
+ writel(1 << 6, SOC_CRM_MPCTL1);
+
+ mpctl0 = readl(SOC_CRM_MPCTL0);
+ mpctl0 = (mpctl0 & 0xC000C000) |
+ CPLM_SETUP |
+ ((pd - 1) << 26) |
+ ((mfd - 1) << 16) |
+ (mfi << 10) |
+ mfn;
+ writel(mpctl0, SOC_CRM_MPCTL0);
+
+ // restart mpll
+ writel((cscr | (1 << 18)), SOC_CRM_CSCR);
+ // check the LF bit to insure lock
+ while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
+ // have to add some delay for new values to take effect
+ for (i = 0; i < 100000; i++);
+
+ // PLL locked already so use the new divider values
+ cscr = readl(SOC_CRM_CSCR);
+ cscr &= ~0x0000FF00;
- // Make sure optimal NFC clock but less than NFC_CLK_MAX
- for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
- if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
- break;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
+ } else {
+ cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
}
- }
- pcdr0 = readl(SOC_CRM_PCDR0);
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
- SOC_CRM_PCDR0);
- } else {
- writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
- SOC_CRM_PCDR0);
- }
+ writel(cscr, SOC_CRM_CSCR);
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- pll = pll_clock(MCU_PLL) + 500000;
- } else {
- if (core_clk > (266 * SZ_DEC_1M)) {
- pll = pll_clock(MCU_PLL) + 500000;
+ // Make sure optimal NFC clock but less than NFC_CLK_MAX
+ for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
+ if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
+ break;
+ }
+ }
+ pcdr0 = readl(SOC_CRM_PCDR0);
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
+ SOC_CRM_PCDR0);
} else {
- pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
+ writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
+ SOC_CRM_PCDR0);
}
- }
- for (i = 0; i < MXC_PERCLK_NUM; i++) {
- per_div[i] = (pll / per_clk_old[i]) - 1;
- }
- writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
- (per_div[0]), SOC_CRM_PCDR1);
- return 0;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ pll = pll_clock(MCU_PLL) + 500000;
+ } else {
+ if (core_clk > (266 * SZ_DEC_1M)) {
+ pll = pll_clock(MCU_PLL) + 500000;
+ } else {
+ pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
+ }
+ }
+ for (i = 0; i < MXC_PERCLK_NUM; i++) {
+ per_div[i] = (pll / per_clk_old[i]) - 1;
+ }
+ writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
+ (per_div[0]), SOC_CRM_PCDR1);
+
+ return 0;
}
static void clock_setup(int argc, char *argv[])
{
- u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
- u32 presc_max, ahb_div_max, pll;
- unsigned long temp;
- int ret;
-
- if (argc == 1)
- goto print_clock;
- if (g_clock_src == FREQ_27MHZ) {
- diag_printf("Error: clock setup is not supported for 27MHz source\n\n");
- return;
- }
- for (i = 0; i < 3; i++) {
- if (!parse_num(argv[1], &temp, &argv[1], ":")) {
- diag_printf("Error: Invalid parameter\n");
- return;
+ u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
+ u32 presc_max, ahb_div_max, pll;
+ unsigned long temp;
+ int ret;
+
+ if (argc == 1)
+ goto print_clock;
+ if (g_clock_src == FREQ_27MHZ) {
+ diag_printf("Error: clock setup is not supported for 27MHz source\n");
+ return;
}
- data[i] = temp;
- }
+ for (i = 0; i < 3; i++) {
+ if (!parse_num(argv[1], &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0] * SZ_DEC_1M;
+ ahb_div = data[1]; // actual register field + 1
+ ipg_div = data[2]; // actual register field + 1
- core_clk = data[0] * SZ_DEC_1M;
- ahb_div = data[1]; // actual register field + 1
- ipg_div = data[2]; // actual register field + 1
-
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- presc_max = PRESC_MAX;
- ahb_div_max = AHB_DIV_MAX;
- pll = core_clk;
- ahb_clk_in = core_clk;
- } else {
- presc_max = ARM_DIV_MAX;
- ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
- if (core_clk > (266 * SZ_DEC_1M)) {
- pll = core_clk;
- ahb_clk_in = core_clk * 2 / 3;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ presc_max = PRESC_MAX;
+ ahb_div_max = AHB_DIV_MAX;
+ pll = core_clk;
+ ahb_clk_in = core_clk;
} else {
- pll = 3 * core_clk / 2;
- ahb_clk_in = core_clk;
+ presc_max = ARM_DIV_MAX;
+ ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
+ if (core_clk > (266 * SZ_DEC_1M)) {
+ pll = core_clk;
+ ahb_clk_in = core_clk * 2 / 3;
+ } else {
+ pll = 3 * core_clk / 2;
+ ahb_clk_in = core_clk;
+ }
+ ipg_div = 2;
}
- ipg_div = 2;
- }
- if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
- PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
- return;
- }
+ if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
+ return;
+ }
- // find the ahb divider
- if (ahb_div > ahb_div_max) {
- diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
- ahb_div, ahb_div_max);
- return;
- }
- if (ahb_div == 0) {
- // no AHBCLK divider specified
- for (ahb_div = 1; ; ahb_div++) {
- if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
- break;
- }
+ // find the ahb divider
+ if (ahb_div > ahb_div_max) {
+ diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
+ ahb_div, ahb_div_max);
+ return;
+ }
+ if (ahb_div == 0) {
+ // no AHBCLK divider specified
+ for (ahb_div = 1; ; ahb_div++) {
+ if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
+ break;
+ }
+ }
+ }
+ if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
+ diag_printf("Can't make AHB=%d since max=%d\n",
+ core_clk / ahb_div, AHB_CLK_MAX);
+ return;
}
- }
- if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
- diag_printf("Can't make AHB=%d since max=%d\n",
- core_clk / ahb_div, AHB_CLK_MAX);
- return;
- }
- // find the ipg divider
- ahb_clk = ahb_clk_in / ahb_div;
- if (ipg_div > IPG_DIV_MAX) {
- diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
- ipg_div, IPG_DIV_MAX);
- return;
- }
- if (ipg_div == 0) {
- ipg_div++; // At least =1
- if (ahb_clk > IPG_CLK_MAX)
- ipg_div++; // Make it =2
- }
- if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
- diag_printf("Can't make IPG=%d since max=%d\n",
- (ahb_clk / ipg_div), IPG_CLK_MAX);
- return;
- }
- ipg_clk = ahb_clk / ipg_div;
-
- diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
- core_clk, ahb_clk, ipg_clk);
-
- // stop the serial to be ready to adjust the clock
- hal_delay_us(100000);
- cyg_hal_plf_serial_stop();
- // adjust the clock
- ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
- // restart the serial driver
- cyg_hal_plf_serial_init();
- hal_delay_us(100000);
-
- if (ret != 0) {
- diag_printf("Failed to setup clock: %d\n", ret);
- return;
- }
+ // find the ipg divider
+ ahb_clk = ahb_clk_in / ahb_div;
+ if (ipg_div > IPG_DIV_MAX) {
+ diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+ ipg_div, IPG_DIV_MAX);
+ return;
+ }
+ if (ipg_div == 0) {
+ ipg_div++; // At least =1
+ if (ahb_clk > IPG_CLK_MAX)
+ ipg_div++; // Make it =2
+ }
+ if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
+ diag_printf("Can't make IPG=%d since max=%d\n",
+ (ahb_clk / ipg_div), IPG_CLK_MAX);
+ return;
+ }
+ ipg_clk = ahb_clk / ipg_div;
+
+ diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+ core_clk, ahb_clk, ipg_clk);
+
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+ ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
- // check for new per clock settings and warn user if there is a change.
- if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
- diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
- }
- if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
- diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
- }
- if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
- diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
- }
- if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
- diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
- }
+ // check for new per clock settings and warn user if there is a change.
+ if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
+ diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
+ }
+ if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
+ diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
+ }
+ if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
+ diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
+ }
+ if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
+ diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
+ }
- diag_printf("\n<<<New clock setting>>>\n");
+ diag_printf("\n<<<New clock setting>>>\n");
- // Now printing clocks
+ // Now printing clocks
print_clock:
- diag_printf("\nMPLL\t\tSPLL\n");
- diag_printf("=========================\n");
- diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
- diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
- diag_printf("========================================================================\n");
- diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
- get_main_clock(CPU_CLK),
- get_main_clock(AHB_CLK),
- get_main_clock(IPG_CLK),
- get_main_clock(NFC_CLK),
- get_main_clock(USB_CLK));
-
- diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
- diag_printf("===========================================");
- diag_printf("=============\n");
-
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(PER_CLK1),
- get_peri_clock(PER_CLK2),
- get_peri_clock(PER_CLK3),
- get_peri_clock(PER_CLK4));
-
- diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
- diag_printf("========================================================\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(H264_BAUD),
- get_peri_clock(MSHC_BAUD),
- get_peri_clock(SSI1_BAUD),
- get_peri_clock(SSI2_BAUD));
- diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
+ diag_printf("\nMPLL\t\tSPLL\n");
+ diag_printf("=========================\n");
+ diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
+ diag_printf("========================================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK));
+
+ diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(PER_CLK1),
+ get_peri_clock(PER_CLK2),
+ get_peri_clock(PER_CLK3),
+ get_peri_clock(PER_CLK4));
+
+ diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(H264_BAUD),
+ get_peri_clock(MSHC_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD));
+ diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
}
/*!
*/
u32 pll_clock(enum plls pll)
{
- int mfi, mfn, mfd, pdf;
- u32 pll_out;
- u32 reg = readl(pll);
- u64 ref_clk;
+ int mfi, mfn, mfd, pdf;
+ u32 pll_out;
+ u32 reg = readl(pll);
+ u64 ref_clk;
- if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
- writel(reg, pll);
- }
- pdf = (reg >> 26) & 0xF;
- mfd = (reg >> 16) & 0x3FF;
- mfi = (reg >> 10) & 0xF;
- if (mfi < 5) {
- mfi = 5;
- }
- mfn = reg & 0x3FF;
- if (mfn >= 512) {
- mfn = 1024 - mfn;
- }
- ref_clk = g_clock_src;
+ if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
+ writel(reg, pll);
+ }
+ pdf = (reg >> 26) & 0xF;
+ mfd = (reg >> 16) & 0x3FF;
+ mfi = (reg >> 10) & 0xF;
+ if (mfi < 5) {
+ mfi = 5;
+ }
+ mfn = reg & 0x3FF;
+ if (mfn >= 512) {
+ mfn = 1024 - mfn;
+ }
+ ref_clk = g_clock_src;
- pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
+ pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+ (pdf + 1);
- return pll_out;
+ return pll_out;
}
/*!
*/
u32 get_main_clock(enum main_clocks clk)
{
- u32 presc, ahb_div, ipg_pdf, nfc_div;
- u32 ret_val = 0, usb_div;
- u32 cscr = readl(SOC_CRM_CSCR);
- u32 pcdr0 = readl(SOC_CRM_PCDR0);
-
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
- } else {
- presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
- }
+ u32 presc, ahb_div, ipg_pdf, nfc_div;
+ u32 ret_val = 0, usb_div;
+ u32 cscr = readl(SOC_CRM_CSCR);
+ u32 pcdr0 = readl(SOC_CRM_PCDR0);
- switch (clk) {
- case CPU_CLK:
- if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
- ret_val = pll_clock(MCU_PLL) / presc;
- } else {
- ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
- }
- break;
- case AHB_CLK:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
- ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
- } else {
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
- }
- break;
- case IPG_CLK:
if (sys_ver == SOC_SILICONID_Rev1_0) {
- ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
- ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
- ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
+ presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
} else {
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = pll_clock(MCU_PLL) / (3*ahb_div);
+ presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
}
- break;
- case NFC_CLK:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
- /* AHB/nfc_div */
- ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
- } else {
- nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
- ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
+
+ switch (clk) {
+ case CPU_CLK:
+ if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
+ ret_val = pll_clock(MCU_PLL) / presc;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
+ }
+ break;
+ case AHB_CLK:
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+ ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
+ } else {
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
+ }
+ break;
+ case IPG_CLK:
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+ ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
+ ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
+ } else {
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = pll_clock(MCU_PLL) / (3 * ahb_div);
+ }
+ break;
+ case NFC_CLK:
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
+ /* AHB/nfc_div */
+ ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
+ } else {
+ nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
+ ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+ ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
+ }
+ break;
+ case USB_CLK:
+ usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
+ ret_val = pll_clock(SER_PLL) / usb_div;
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ break;
}
- break;
- case USB_CLK:
- usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
- ret_val = pll_clock(SER_PLL) / usb_div;
- break;
- default:
- diag_printf("Unknown clock: %d\n", clk);
- break;
- }
- return ret_val;
+ return ret_val;
}
/*!
*/
u32 get_peri_clock(enum peri_clocks clk)
{
- u32 ret_val = 0, div;
- u32 pcdr0 = readl(SOC_CRM_PCDR0);
- u32 pcdr1 = readl(SOC_CRM_PCDR1);
- u32 cscr = readl(SOC_CRM_CSCR);
-
- switch (clk) {
- case PER_CLK1:
- div = (pcdr1 & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK2:
- case SPI1_CLK:
- case SPI2_CLK:
- div = ((pcdr1 >> 8) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK3:
- div = ((pcdr1 >> 16) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case PER_CLK4:
- div = ((pcdr1 >> 24) & 0x3F) + 1;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- break;
- case SSI1_BAUD:
- div = (pcdr0 >> 16) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 22)) != 0) {
- // This takes care of 0.5*SSIDIV[0] by x2
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case SSI2_BAUD:
- div = (pcdr0 >> 26) & 0x3F;
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div += 4;
- }
- if ((cscr & (1 << 23)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case H264_BAUD:
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 >> 8) & 0xF;
- if (div < 2) {
- div = 62 * 2;
- }
- } else {
- div = (pcdr0 >> 10) & 0x3F;
- div += 4;
- }
- if ((cscr & (1 << 21)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- ret_val = (2 * pll_clock(MCU_PLL)) / div;
- } else {
- ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
- }
- } else {
- ret_val = (2 * pll_clock(SER_PLL)) / div;
- }
- break;
- case MSHC_BAUD:
- if ((cscr & (1 << 20)) != 0) {
- if (sys_ver == SOC_SILICONID_Rev1_0) {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = pll_clock(MCU_PLL) / div;
- } else {
- div = (pcdr0 & 0x3F) + 1;
- ret_val = 2*pll_clock(MCU_PLL) / (3*div);
- }
- } else {
- div = (pcdr0 & 0x1F) + 1;
- ret_val = (2 * pll_clock(SER_PLL)) / div;
+ u32 ret_val = 0, div;
+ u32 pcdr0 = readl(SOC_CRM_PCDR0);
+ u32 pcdr1 = readl(SOC_CRM_PCDR1);
+ u32 cscr = readl(SOC_CRM_CSCR);
+
+ switch (clk) {
+ case PER_CLK1:
+ div = (pcdr1 & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK2:
+ case SPI1_CLK:
+ case SPI2_CLK:
+ div = ((pcdr1 >> 8) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK3:
+ div = ((pcdr1 >> 16) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case PER_CLK4:
+ div = ((pcdr1 >> 24) & 0x3F) + 1;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ break;
+ case SSI1_BAUD:
+ div = (pcdr0 >> 16) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 22)) != 0) {
+ // This takes care of 0.5*SSIDIV[0] by x2
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case SSI2_BAUD:
+ div = (pcdr0 >> 26) & 0x3F;
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div += 4;
+ }
+ if ((cscr & (1 << 23)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case H264_BAUD:
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 >> 8) & 0xF;
+ if (div < 2) {
+ div = 62 * 2;
+ }
+ } else {
+ div = (pcdr0 >> 10) & 0x3F;
+ div += 4;
+ }
+ if ((cscr & (1 << 21)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ ret_val = (2 * pll_clock(MCU_PLL)) / div;
+ } else {
+ ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+ }
+ } else {
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ case MSHC_BAUD:
+ if ((cscr & (1 << 20)) != 0) {
+ if (sys_ver == SOC_SILICONID_Rev1_0) {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = pll_clock(MCU_PLL) / div;
+ } else {
+ div = (pcdr0 & 0x3F) + 1;
+ ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+ }
+ } else {
+ div = (pcdr0 & 0x1F) + 1;
+ ret_val = (2 * pll_clock(SER_PLL)) / div;
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet\n",
+ __FUNCTION__, clk);
+ break;
}
- break;
- default:
- diag_printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
- }
- return ret_val;
+ return ret_val;
}
RedBoot_cmd("clko",
- "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
- " The output clock is the actual clock source freq divided by 8. Default is FCLK\n\
- Note that the module clock will be turned on for reading!\n\
- <0> - display current clko selection \n\
- <1> - CLK32 \n\
- <2> - PREMCLK \n\
- <3> - CLK26M (may see nothing if 26MHz Crystal is not connected) \n\
- <4> - MPLL Reference CLK \n\
- <5> - SPLL Reference CLK \n\
- <6> - MPLL CLK \n\
- <7> - SPLL CLK \n\
- <8> - FCLK \n\
- <9> - AHBCLK \n\
- <10> - IPG_CLK (PERCLK) \n\
- <11> - PERCLK1 \n\
- <12> - PERCLK2 \n\
- <13> - PERCLK3 \n\
- <14> - PERCLK4 \n\
- <15> - SSI 1 Baud \n\
- <16> - SSI 2 Baud \n\
- <17> - NFC \n\
- <18> - MSHC Baud \n\
- <19> - H264 Baud \n\
- <20> - CLK60M Always \n\
- <21> - CLK32K Always \n\
- <22> - CLK60M \n\
- <23> - DPTC Ref",
- clko
- );
-
-static u8* clko_name[] ={
- "NULL",
- "CLK32",
- "PREMCLK",
- "CLK26M (may see nothing if 26MHz Crystal is not connected)",
- "MPLL Reference CLK",
- "SPLL Reference CLK",
- "MPLL CLK",
- "SPLL CLK",
- "FCLK",
- "AHBCLK",
- "IPG_CLK (PERCLK)",
- "PERCLK1",
- "PERCLK2",
- "PERCLK3",
- "PERCLK4",
- "SSI 1 Baud",
- "SSI 2 Baud",
- "NFC",
- "MSHC Baud",
- "H264 Baud",
- "CLK60M Always",
- "CLK32K Always",
- "CLK60M",
- "DPTC Ref",
+ "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
+ " The output clock is the actual clock source freq divided by 8. Default is FCLK\n"
+ " Note that the module clock will be turned on for reading!\n"
+ " <0> - display current clko selection\n"
+ " <1> - CLK32\n"
+ " <2> - PREMCLK\n"
+ " <3> - CLK26M (may see nothing if 26MHz Crystal is not connected)\n"
+ " <4> - MPLL Reference CLK\n"
+ " <5> - SPLL Reference CLK\n"
+ " <6> - MPLL CLK\n"
+ " <7> - SPLL CLK\n"
+ " <8> - FCLK\n"
+ " <9> - AHBCLK\n"
+ " <10> - IPG_CLK (PERCLK)\n"
+ " <11> - PERCLK1\n"
+ " <12> - PERCLK2\n"
+ " <13> - PERCLK3\n"
+ " <14> - PERCLK4\n"
+ " <15> - SSI 1 Baud\n"
+ " <16> - SSI 2 Baud\n"
+ " <17> - NFC\n"
+ " <18> - MSHC Baud\n"
+ " <19> - H264 Baud\n"
+ " <20> - CLK60M Always\n"
+ " <21> - CLK32K Always\n"
+ " <22> - CLK60M\n"
+ " <23> - DPTC Ref",
+ clko
+ );
+
+static u8* clko_name[] = {
+ "NULL",
+ "CLK32",
+ "PREMCLK",
+ "CLK26M (may see nothing if 26MHz Crystal is not connected)",
+ "MPLL Reference CLK",
+ "SPLL Reference CLK",
+ "MPLL CLK",
+ "SPLL CLK",
+ "FCLK",
+ "AHBCLK",
+ "IPG_CLK (PERCLK)",
+ "PERCLK1",
+ "PERCLK2",
+ "PERCLK3",
+ "PERCLK4",
+ "SSI 1 Baud",
+ "SSI 2 Baud",
+ "NFC",
+ "MSHC Baud",
+ "H264 Baud",
+ "CLK60M Always",
+ "CLK32K Always",
+ "CLK60M",
+ "DPTC Ref",
};
-#define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
+#define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
static void clko(int argc,char *argv[])
{
- u32 action = 0, ccsr;
+ u32 action = 0, ccsr;
- if (!scan_opts(argc, argv, 1, 0, 0, &action,
- OPTION_ARG_TYPE_NUM, "action"))
- return;
+ if (!scan_opts(argc, argv, 1, 0, 0, &action,
+ OPTION_ARG_TYPE_NUM, "action"))
+ return;
- if (action >= CLKO_MAX_INDEX) {
- diag_printf("%d is not supported\n\n", action);
- return;
- }
+ if (action >= CLKO_MAX_INDEX) {
+ diag_printf("%d is not supported\n", action);
+ return;
+ }
- ccsr = readl(SOC_CRM_CCSR);
+ ccsr = readl(SOC_CRM_CCSR);
- if (action != 0) {
- ccsr = (ccsr & (~0x1F)) + action - 1;
- writel(ccsr, SOC_CRM_CCSR);
- diag_printf("Set clko to ");
- }
+ if (action != 0) {
+ ccsr = (ccsr & (~0x1F)) + action - 1;
+ writel(ccsr, SOC_CRM_CCSR);
+ diag_printf("Set clko to ");
+ }
- ccsr = readl(SOC_CRM_CCSR);
- diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
- diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
+ ccsr = readl(SOC_CRM_CCSR);
+ diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
+ diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
}
extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
void auto_flash_start(void)
{
- void *err_addr;
+ void *err_addr;
int stat;
- int nor_update = 1; //todo: need to support NAND
- u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
- u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
- u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
-
- if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
- return;
- }
+ int nor_update = 1; //todo: need to support NAND
+ u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
+ u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
+ u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
- if (nor_update) {
- // Erase area to be programmed
- if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
- diag_printf("BEADDEAD\n");
- return;
+ if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
+ return;
}
- diag_printf("BEADBEEF\n");
- // Now program it
- if ((stat = flash_program((void *)dst, (void *)src, sz,
- &err_addr)) != 0) {
- diag_printf("BEADFEEF\n");
+
+ if (nor_update) {
+ // Erase area to be programmed
+ if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
+ diag_printf("BEADDEAD\n");
+ return;
+ }
+ diag_printf("BEADBEEF\n");
+ // Now program it
+ if ((stat = flash_program((void *)dst, (void *)src, sz,
+ &err_addr)) != 0) {
+ diag_printf("BEADFEEF\n");
+ }
}
- }
- diag_printf("BEADCEEF\n");
+ diag_printf("BEADCEEF\n");
}
RedBoot_init(auto_flash_start, RedBoot_INIT_LAST);
-#define IIM_ERR_SHIFT 8
-#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
-#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
static void fuse_op_start(void)
{
- /* Do not generate interrupt */
- writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
- // clear the status bits and error bits
- writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
- writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
}
/*
*/
static int poll_fuse_op_done(int action)
{
+ u32 status, error;
- u32 status, error;
-
- if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
- diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
- return -1;
- }
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
- /* Poll busy bit till it is NOT set */
- while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
- }
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
- /* Test for successful write */
- status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
- error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
- if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
- if (error) {
- diag_printf("Even though the operation seems successful...\n");
- diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
}
- return 0;
- }
- diag_printf("%s(%d) failed\n", __FUNCTION__, action);
- diag_printf("status address=0x%08lx, value=0x%08x\n",
- (IIM_BASE_ADDR + IIM_STAT_OFF), status);
- diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- return -1;
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%08lx, value=0x%08x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
}
static void sense_fuse(int bank, int row, int bit)
{
- int ret;
- int addr, addr_l, addr_h, reg_addr;
+ int ret;
+ int addr, addr_l, addr_h, reg_addr;
- fuse_op_start();
+ fuse_op_start();
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
- __FUNCTION__, addr_h, addr_l);
+ diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
+ __FUNCTION__, addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start sensing */
- writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
- diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
- __FUNCTION__, bank, row, bit);
- }
- reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
- if (ret == 0)
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ if (ret == 0)
diag_printf("fuses at (bank:%d, row:%d) = 0x%02x\n", bank, row, readl(reg_addr));
}
void do_fuse_read(int argc, char *argv[])
{
- unsigned long bank, row;
-
- if (argc == 1) {
- diag_printf("Useage: fuse_read <bank> <row>\n");
- return;
- } else if (argc == 3) {
- if (!parse_num(argv[1], &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(argv[2], &row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
+ unsigned long bank, row;
+
+ if (argc == 1) {
+ diag_printf("Usage: fuse_read <bank> <row>\n");
return;
- }
+ } else if (argc == 3) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
- diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
- sense_fuse(bank, row, 0);
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ sense_fuse(bank, row, 0);
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: fuse_read <bank> <row>\n");
- }
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Usage: fuse_read <bank> <row>\n");
+ }
}
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
int fuse_blow(int bank, int row, int bit)
{
- int addr, addr_l, addr_h, ret = -1;
+ int addr, addr_l, addr_h, ret = -1;
- fuse_op_start();
+ fuse_op_start();
- /* Disable IIM Program Protect */
- writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
- diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
+ diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
+ diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start Programming */
- writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
- ret = 0;
- }
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
- /* Enable IIM Program Protect */
- writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- return ret;
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
}
/*
* This command is added for burning IIM fuses
*/
RedBoot_cmd("fuse_read",
- "read some fuses",
- "<bank> <row>",
- do_fuse_read
- );
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
RedBoot_cmd("fuse_blow",
- "blow some fuses",
- "<bank> <row> <value>",
- do_fuse_blow
- );
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
-#define INIT_STRING "12345678"
+#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
void do_fuse_blow(int argc, char *argv[])
{
- unsigned long bank, row, value;
- int i;
-
- if (argc == 1) {
- diag_printf("It is too dangeous for you to use this command.\n");
- return;
- } else if (argc == 2) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
- diag_printf("%s\n", "fuse blown not needed");
- }
- return;
- } else if (argc == 3) {
- if (strcasecmp(argv[1], "nandboot") == 0) {
+ unsigned long bank, row, value;
+ int i;
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ } else if (argc == 2) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
+ diag_printf("%s\n", "fuse blown not needed");
+ }
+ return;
+ } else if (argc == 3) {
+ if (strcasecmp(argv[1], "nandboot") == 0) {
#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
- diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+ diag_printf("No need to blow any fuses for NAND boot on this platform\n");
#else
- diag_printf("Ready to burn NAND boot fuses\n");
- if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
- diag_printf("NAND BOOT fuse blown failed miserably ...\n");
- } else {
- diag_printf("NAND BOOT fuse blown successfully ...\n");
- }
- } else {
- diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+ diag_printf("Ready to burn NAND boot fuses\n");
+ if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+ diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+ } else {
+ diag_printf("NAND BOOT fuse blown successfully ...\n");
+ }
+ } else {
+ diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
#endif
- }
- } else if (argc == 4) {
- if (!parse_num(argv[1], &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid fuse bank\n");
- return;
- }
- if (!parse_num(argv[2], &row, &argv[2], " ")) {
- diag_printf("Error: Invalid fuse row\n");
- return;
- }
- if (!parse_num(argv[3], &value, &argv[3], " ")) {
- diag_printf("Error: Invalid value\n");
- return;
- }
-
- if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
- bank, row, value)) {
- diag_printf("fuse_blow canceled\n");
- return;
- }
+ }
+ } else if (argc == 4) {
+ if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid fuse bank\n");
+ return;
+ }
+ if (!parse_num(argv[2], &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid fuse row\n");
+ return;
+ }
+ if (!parse_num(argv[3], &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid value\n");
+ return;
+ }
- for (i = 0; i < 8; i++) {
- if (((value >> i) & 0x1) == 0) {
- continue;
+ if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
+ bank, row, value)) {
+ diag_printf("fuse_blow canceled\n");
+ return;
}
- if (fuse_blow(bank, row, i) != 0) {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
- bank, row, i);
- } else {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
- bank, row, i);
+
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+ bank, row, i);
+ } else {
+ diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+ bank, row, i);
+ }
}
+ sense_fuse(bank, row, 0);
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
}
- sense_fuse(bank, row, 0);
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- }
- /* Reset to default string */
- strcpy(ready_to_blow, INIT_STRING);
+ /* Reset to default string */
+ strcpy(ready_to_blow, INIT_STRING);
}
/* precondition: m>0 and n>0. Let g=gcd(m,n). */
int gcd(int m, int n)
{
- int t;
- while (m > 0) {
- if (n > m) {t = m; m = n; n = t;} /* swap */
- m -= n;
- }
- return n;
+ int t;
+ while (m > 0) {
+ if (n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
}
#define CLOCK_SRC_DETECT_MS 100
void mxc_show_clk_input(void)
{
#if 0
- u32 c1, c2, diff, ipg_real, num = 0;
- u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
-
- return; // FIXME
-
- switch (prcs) {
- case 0x01:
- diag_printf("FPM enabled --> 32KHz input source\n");
- return;
- case 0x02:
- break;
- default:
- diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
- return;
- }
+ u32 c1, c2, diff, ipg_real, num = 0;
+ u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
- // enable GPT with IPG clock input
- writel(0x241, GPT_BASE_ADDR + GPTCR);
- // prescaler = 1
- writel(0, GPT_BASE_ADDR + GPTPR);
-
- c1 = readl(GPT_BASE_ADDR + GPTCNT);
- // use 32KHz input clock to get the delay
- hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
- c2 = readl(GPT_BASE_ADDR + GPTCNT);
- diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
-
- ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
-
- if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
- if (g_clock_src != FREQ_27MHZ)
- num = 27;
- } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
- if (g_clock_src != FREQ_26MHZ)
- num = 26;
- }
- if (num != 0) {
- diag_printf("Error: Actual clock input is %d MHz\n", num);
- diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- diag_printf(" But clock source defined to be %d\n\n", g_clock_src);
- hal_delay_us(2000000);
- } else {
- diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- diag_printf("clock source defined to be %d\n\n", g_clock_src);
- }
+ return; // FIXME
+
+ switch (prcs) {
+ case 0x01:
+ diag_printf("FPM enabled --> 32KHz input source\n");
+ return;
+ case 0x02:
+ break;
+ default:
+ diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+ return;
+ }
+
+ // enable GPT with IPG clock input
+ writel(0x241, GPT_BASE_ADDR + GPTCR);
+ // prescaler = 1
+ writel(0, GPT_BASE_ADDR + GPTPR);
+
+ c1 = readl(GPT_BASE_ADDR + GPTCNT);
+ // use 32KHz input clock to get the delay
+ hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+ c2 = readl(GPT_BASE_ADDR + GPTCNT);
+ diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+
+ ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
+
+ if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
+ if (g_clock_src != FREQ_27MHZ)
+ num = 27;
+ } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
+ if (g_clock_src != FREQ_26MHZ)
+ num = 26;
+ }
+ if (num != 0) {
+ diag_printf("Error: Actual clock input is %d MHz\n", num);
+ diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ diag_printf(" But clock source defined to be %d\n", g_clock_src);
+ hal_delay_us(2000000);
+ } else {
+ diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
+ ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+ diag_printf("clock source defined to be %d\n", g_clock_src);
+ }
#endif
}
This HAL platform package provides generic
support for the Freescale MX51 3-Stack Board."
+# compile board_misc.c board_diag.c mx51_fastlogo.c epson_lcd.c
compile board_misc.c board_diag.c
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
#define LED_MAX_NUM 8
+#define LCD_HEIGHT 640
+#define LCD_WIDTH 480
+#define DISPLAY_CHANNEL 28
#endif /* CYGONCE_FSL_BOARD_H */
b reset_vector
.org 0x400
app_code_jump_v: .long reset_vector
-app_code_barker: .long 0xB1
-app_code_csf: .long 0
+app_code_barker: .long 0xB1 // barker code
+app_code_csf: .long (0x97f40000 - 0x1000) // reserve 4K for csf
dcd_ptr_ptr: .long dcd_ptr
-super_root_key: .long 0
+super_root_key: .long hab_super_root_key
dcd_ptr: .long dcd_data
app_dest_ptr: .long 0x97f00000
dcd_data: .long 0xB17219E9 // Fixed. can't change.
-#ifdef IMX51_TO_2
-dcd_len: .long (56*12)
+
+#ifdef IMX51_MDDR
+// DCD
+dcd_len: .long (38*12)
+// DDR IOMUX configuration
+// Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x4b8, 0x000000e7) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
+DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x4d4, 0x000000e4) // DQM0 DS high, slew rate slow
+DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x4d8, 0x000000e4) // DQM1 DS high, slew rate slow
+DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x4dc, 0x000000e4) // DQM2 DS high, slew rate slow
+DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x4e0, 0x000000e4) // DQM3 DS high, slew rate slow
+DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x000000c4) // SDQS0 DS high, slew rate slow
+DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x000000c4) // SDQS1 DS high, slew rate slow
+DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x000000c4) // SDQS2 DS high, slew rate slow
+DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x000000c4) // SDQS3 DS high, slew rate slow
+DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000004) // DRAM_B0
+DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000004) // DRAM_B1
+DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000004) // DRAM_B2
+DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x82c, 0x00000004) // DRAM_B3
+DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x878, 0x00000000) // DRAM_B0_SR
+DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x880, 0x00000000) // DRAM_B1_SR
+DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x88c, 0x00000000) // DRAM_B2_SR
+DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x89c, 0x00000000) // DRAM_B3_SR
+// Configure CS0
+DCDGEN(18, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x83220000) // ESDCTL0: Enable controller
+DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) // ESDSCR: Precharge command
+DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801a) // ESDSCR: EMR with Half Drive strength
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) // ESDSCR
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000) // ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+// tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xC33574AA)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000a1700) // ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+// Configure CS1
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x83220000) // ESDCTL1: Enable controller
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) // ESDSCR: Precharge command
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0033801c) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801e) // ESDSCR: EMR with Half Drive strength
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) // ESDSCR
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xC3220000) // ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+// tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0xC33574AA)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) // ESDSCR - clear "configuration request" bit
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00f58000) //Delay line write - -11
+
+#else
+dcd_len: .long (57*12)
//DCD
//DDR2 IOMUX configuration
DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
-//Set drive strength to MAX
-DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
-DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
-DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
-DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
//CAS=3, BL=4
-DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
-DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
-DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
-DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
-DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
// Init DRAM on CS0
-DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
-DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
-DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
-DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
-DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
-DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
-DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
-DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019)
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019)
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
// Init DRAM on CS1
-DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
-DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
-DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
-DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
-DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
-DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
-DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
-DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
-
-DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
-DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
-DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
-DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
-DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
-
-#else
-dcd_len: .long (9*12)
-
-//DCD
- // ldr r0, ESDCTL_BASE_W
- // /* Set CSD0 */
- // ldr r1, =0x80000000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
- // /* Precharge command */
- // ldr r1, SDRAM_0x04008008
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
- // /* 2 refresh commands */
- // ldr r1, SDRAM_0x00008010
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // /* LMR with CAS=3 and BL=3 */
- // ldr r1, SDRAM_0x00338018
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
- // /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
- // ldr r1, SDRAM_0xB2220000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xB2220000)
- // /* Timing parameters */
- // ldr r1, SDRAM_0xB02567A9
- // str r1, [r0, #ESDCTL_ESDCFG0]
-DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB02567A9)
- // /* MDDR enable, RLAT=2 */
- // ldr r1, SDRAM_0x000A0104
- // str r1, [r0, #ESDCTL_ESDMISC]
-DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
- // /* Normal mode */
- // ldr r1, =0x00000000
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d)
+DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+
+DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+
+// Delay settings
+DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000)
+DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000)
+DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000)
+DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000)
+DCDGEN(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
#endif
-image_len: .long 256*1024
+image_len: .long 256 * 1024 // 256K for Redboot and csf
.endm
// This macro represents the initial startup code for the platform
.macro _platform_setup1
FSL_BOARD_SETUP_START:
- // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
- // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+ ldr r1, =ROM_BASE_ADDR
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+
+ setup_sdram
+
+ ldr r0, =GPC_BASE_ADDR
+ cmp r3, #0x10 // r3 contains the silicon rev
+ ldrls r1, =0x1FC00000
+ ldrhi r1, =0x1A800000
+ str r1, [r0, #4]
+
#ifdef ENABLE_IMPRECISE_ABORT
mrs r1, spsr // save old spsr
mrs r0, cpsr // read out the cpsr
// reconfigure L2 cache aux control reg
mov r0, #0xC0 // tag RAM
add r0, r0, #0x4 // data RAM
- orr r0, r0, #(1 << 25) // disable write combine
orr r0, r0, #(1 << 24) // disable write allocate delay
orr r0, r0, #(1 << 23) // disable write allocate combine
orr r0, r0, #(1 << 22) // disable write allocate
+ cmp r3, #0x10 // r3 contains the silicon rev
+ orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs
+
mcr 15, 1, r0, c9, c0, 2
- /* Reload data from spare area to 0x400 of main area if booting from NAND */
- ldr r0, NFC_BASE_W
- cmp pc, r0
- blo 1f
- cmp pc, r1
- bhi 1f
-1:
- /* Store the boot type, from NAND or SDRAM */
- mov r11, #SDRAM_NON_FLASH_BOOT
-
-init_spba_start:
- init_spba
init_aips_start:
init_aips
-init_max_start:
- init_max
init_m4if_start:
init_m4if
-init_iomux_start:
-// init_iomux
-
- // disable wdog
- ldr r0, =0x30
- ldr r1, WDOG1_BASE_W
- strh r0, [r1]
-
- /* If SDRAM has been setup, bypass clock/WEIM setup */
- cmp pc, #SDRAM_BASE_ADDR
- blo external_boot_cont
- cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
- blo internal_boot_cont
-
-external_boot_cont:
-
-init_sdram_start:
- setup_sdram
-
-
-internal_boot_cont:
-init_clock_start:
- init_clock
-
-HWInitialise_skip_SDRAM_setup:
- ldr r0, NFC_BASE_W
- add r2, r0, #0x1000 // 4K window
- cmp pc, r0
- blo Normal_Boot_Continue
- cmp pc, r2
- bhi Normal_Boot_Continue
-
-NAND_Boot_Start:
- /* Copy image from flash to SDRAM first */
- ldr r1, MXC_REDBOOT_ROM_START
-1: ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- cmp r0, r2
- blo 1b
-
- /* Jump to SDRAM */
- ldr r1, CONST_0x0FFF
- and r0, pc, r1 /* offset of pc */
- ldr r1, MXC_REDBOOT_ROM_START
- add r1, r1, #0x10
- add pc, r0, r1
- nop
- nop
- nop
- nop
- nop
- nop
-
-NAND_Copy_Main:
- ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
- ldr r0, [r11, #0x24]
- and r0, r0, #3
- cmp r0, #1
- mov r0, #4096
- moveq r0, #2048
- movlt r0, #512
- ldr r1, =_nand_pg_sz // r1 -> _nand_pg_sz
- str r0, [r1] // store the page size into the global variable _nand_pg_sz
-
- ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
- ldr r1, _nand_pg_sz //r1: starting flash addr to be copied. Updated constantly
- add r2, r0, #0x800 //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
- cmp r1, #2048
- addgt r2, r2, #2048 // for 4K page, copy 4K instead of 2K
-
- add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
- ldr r14, MXC_REDBOOT_ROM_START
- add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
- add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
-
- //unlock internal buffer
- mov r3, #0xFF000000
- add r3, r3, #0x00FF0000
- str r3, [r11, #0x4]
- str r3, [r11, #0x8]
- str r3, [r11, #0xC]
- str r3, [r11, #0x10]
- str r3, [r11, #0x14]
- str r3, [r11, #0x18]
- str r3, [r11, #0x1C]
- str r3, [r11, #0x20]
- mov r4, #0x7
- mov r3, #0x84
-1: add r5, r3, r4, lsr #3
- str r5, [r11, #0x0]
- subs r4, r4, #0x1
- bne 1b
-
- mov r3, #0
- str r3, [r11, #0x2C]
-
-Nfc_Read_Page:
- //start_nfc_addr_ops1(pg_no, pg_off);
- ldr r3, _nand_pg_sz
- cmp r3, #2048
- // TODO: need to deal with 512B page
- movgt r3, r1, lsr #12 // get the page number for 4K page nand
- moveq r3, r1, lsr #11 // get the page number for 2K page nand
- mov r3, r3, lsl #16
- str r3, [r12, #0x4] // set the addr
-
- // writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
- mov r3, #0x3000
- str r3, [r12, #0x0]
-
- // writel(0x00000000, NAND_CONFIGURATION1_REG);
- mov r3, #0x0
- str r3, [r12, #0x34]
-
- // start auto-read
- //writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
- mov r3, #NAND_LAUNCH_AUTO_READ
- str r3, [r12, #0x40]
-
- do_wait_op_done
-
-Copy_Good_Blk:
- //copying page
-1: ldmia r0!, {r3-r10}
- stmia r14!, {r3-r10}
- cmp r0, r2
- blo 1b
- cmp r14, r13
- bge NAND_Copy_Main_done
- ldr r3, _nand_pg_sz
- add r1, r1, r3
- ldr r0, NFC_BASE_W
- b Nfc_Read_Page
-
-NAND_Copy_Main_done:
-
-Normal_Boot_Continue:
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
- /* Copy image from flash to SDRAM first */
+ /* Check if need to copy image to Redboot ROM space */
ldr r0, =0xFFFFF000
and r0, r0, pc
ldr r1, MXC_REDBOOT_ROM_START
cmp r0, r1
- beq HWInitialise_skip_SDRAM_copy
+ beq skip_copy_to_ddr
add r2, r0, #REDBOOT_IMAGE_SIZE
nop
#endif /* CYG_HAL_STARTUP_ROMRAM */
-HWInitialise_skip_SDRAM_copy:
+skip_copy_to_ddr:
+ /* Skip clock setup if already booted up */
+ ldr r0, =IRAM_BASE_ADDR
+ ldr r0, [r0]
+ ldr r1, =FROM_SPI_NOR_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+ ldr r1, =FROM_MMC_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+ ldr r1, =FROM_NAND_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+
+init_clock_start:
+ init_clock
-init_cs1_start:
-// init_cs1 -- moved to plf_hardware_init()
+Normal_Boot_Continue:
/*
* Note:
// Create MMU tables
bl hal_mmu_init
+ /* Workaround for arm errata #709718 */
+ //Setup PRRR so device is always mapped to non-shared
+ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
+ bic r1, #(3 << 16)
+ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
+
// Enable MMU
ldr r2, =10f
- ldr r0, =ROM_BASE_ADDRESS
- ldr r3, [r0, #ROM_SI_REV_OFFSET]
- cmp r3, #0x1
- bne skip_L1_workaround
- // Workaround for L1 cache issue
- mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
- bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
- bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
- bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
- mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
-skip_L1_workaround:
- mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ mrc MMU_CP, 0, r1, MMU_Control, c0
orr r1, r1, #7 // enable MMU bit
orr r1, r1, #0x800 // enable z bit
- orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ orr r1, r1, #(1 << 28) // Enable TEX remap
mcr MMU_CP, 0, r1, MMU_Control, c0
+
+ /* Workaround for arm errata #621766 */
+ mrc MMU_CP, 0, r1, MMU_Control, c0, 1
+ orr r1, r1, #(1 << 5) // enable L1NEON bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0, 1
+
mov pc,r2 /* Change address spaces */
nop
nop
#define PLATFORM_SETUP1
#endif
- /* Do nothing */
- .macro init_spba
- .endm /* init_spba */
-
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
.macro init_aips
/*
.endm /* init_aips */
- /* MAX (Multi-Layer AHB Crossbar Switch) setup */
- .macro init_max
- .endm /* init_max */
-
.macro init_clock
ldr r0, CCM_BASE_ADDR_W
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #CLKCTL_CCDR]
-#ifdef IMX51_TO_2
/* Make sure to switch the DDR away from PLL 1 */
- ldr r1, CCM_VAL_0x19239100
+ ldr r1, CCM_VAL_0x19239145
str r1, [r0, #CLKCTL_CBCDR]
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
-#endif
+
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
setup_pll PLL3, 665
/* Switch peripheral to PLL 3 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x0000D3C0
+ ldr r1, CCM_VAL_0x000010C0
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, CCM_VAL_0x033B9145
+ ldr r1, CCM_VAL_0x13239145
str r1, [r0, #CLKCTL_CBCDR]
setup_pll PLL2, 665
/* Switch peripheral to PLL 2 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x013B9145
+ ldr r1, CCM_VAL_0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, CCM_VAL_0x0000E3C0
+ ldr r1, CCM_VAL_0x000020C0
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3, 216
ldr r1, PLATFORM_CLOCK_DIV_W
str r1, [r0, #PLATFORM_ICGC]
- /* Switch ARM back to PLL 1. */
ldr r0, CCM_BASE_ADDR_W
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r1, =ROM_BASE_ADDR
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
/* Use lp_apm (24MHz) source for perclk */
-#ifdef IMX51_TO_2
ldr r1, CCM_VAL_0x000020C2
str r1, [r0, #CLKCTL_CBCMR]
// ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
- ldr r1, CCM_VAL_0x59239100
- str r1, [r0, #CLKCTL_CBCDR]
+#ifdef IMX51_MDDR
+ ldr r1, CCM_VAL_0x61E35100
#else
- ldr r1, CCM_VAL_0x0000E3C2
- str r1, [r0, #CLKCTL_CBCMR]
- // emi=ahb, all perclk dividers are 1 since using 24MHz
- ldr r1, CCM_VAL_0x013B9100
- str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, CCM_VAL_0x59E35100
#endif
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, CCM_VAL_0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
/* M3IF setup */
.macro init_m4if
ldr r1, M4IF_BASE_W
-#ifdef IMX51_TO_2
- ldr r0, M4IF_0x00240180
- str r0, [r1, #M4IF_MIF4]
-#else
- /* IPU accesses with ID=0x1 given highest priority (=0xA) */
- ldr r0, M4IF_0x00000a01
- str r0, [r1, #M4IF_FIDBP]
-#endif
- /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
- ldr r0, M4IF_0x00000404
+ ldr r0, M4IF_0x00000203
str r0, [r1, #M4IF_FBPM0]
+
+ ldr r0, =0x0
+ str r0, [r1, #M4IF_FBPM1]
+
+ ldr r0, M4IF_0x00120125
+ str r0, [r1, #M4IF_FPWC]
+
+ ldr r0, M4IF_0x001901A3
+ str r0, [r1, #M4IF_MIF4]
+
.endm /* init_m4if */
.macro setup_sdram
+ cmp r3, #0x10 // r3 contains the silicon rev
+ bls skip_setup
+ /* Decrease the DRAM SDCLK to HIGH Drive strength */
+ ldr r0, IOMUXC_BASE_ADDR_W
+ ldr r1, =0x000000e5
+ str r1, [r0, #0x4b8]
+ /* Change the delay line configuration */
ldr r0, ESDCTL_BASE_W
- /* Set CSD0 */
- ldr r1, =0x80000000
- str r1, [r0, #ESDCTL_ESDCTL0]
- /* Precharge command */
- ldr r1, SDRAM_0x04008008
- str r1, [r0, #ESDCTL_ESDSCR]
- /* 2 refresh commands */
- ldr r1, SDRAM_0x00008010
- str r1, [r0, #ESDCTL_ESDSCR]
- str r1, [r0, #ESDCTL_ESDSCR]
- /* LMR with CAS=3 and BL=3 */
- ldr r1, SDRAM_0x00338018
- str r1, [r0, #ESDCTL_ESDSCR]
- /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
- ldr r1, SDRAM_0xB2220000
- str r1, [r0, #ESDCTL_ESDCTL0]
- /* Timing parameters */
-// ldr r1, SDRAM_0x899F6BBA
- ldr r1, SDRAM_0xB02567A9
- str r1, [r0, #ESDCTL_ESDCFG0]
- /* MDDR enable, RLAT=2 */
- ldr r1, SDRAM_0x000A0104
- str r1, [r0, #ESDCTL_ESDMISC]
- /* Normal mode */
- ldr r1, =0x00000000
- str r1, [r0, #ESDCTL_ESDSCR]
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ ldr r1, =0x00f49a00
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ ldr r1, =0x00f49100
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ ldr r1, =0x00f48900
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY5]
+skip_setup:
.endm
- .macro do_wait_op_done
- 1:
- ldr r3, [r11, #0x2C]
- ands r3, r3, #NFC_IPC_INT
- beq 1b
- mov r3, #0x0
- str r3, [r11, #0x2C]
- .endm // do_wait_op_done
-
- .macro init_iomux
- // do nothing
- .endm /* init_iomux */
-
#define PLATFORM_VECTORS _platform_vectors
.macro _platform_vectors
.globl _board_BCR, _board_CFG
_board_BCR: .long 0 // Board Control register shadow
_board_CFG: .long 0 // Board Configuration (read at RESET)
+ .globl _KARO_MAGIC
+_KARO_MAGIC:
+ .ascii "KARO_CE6"
+ .globl _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+ .word 0 // reserve space structure length
+
+ .globl _KARO_CECFG_START
+_KARO_CECFG_START:
+ .rept 1024/4
+ .word 0 // reserve space for CE configuration
+ .endr
+
+ .globl _KARO_CECFG_END
+_KARO_CECFG_END:
.endm
-WDOG1_BASE_W: .word WDOG1_BASE_ADDR
IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
MAX_PARAM1: .word 0x00302154
ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
M4IF_BASE_W: .word M4IF_BASE_ADDR
-M4IF_0x00000a01: .word 0x00000a01
-M4IF_0x00240180: .word 0x00240180
-M4IF_0x00000404: .word 0x00000404
-NFC_BASE_W: .word NFC_BASE_ADDR_AXI
-NFC_IP_BASE_W: .word NFC_IP_BASE
+M4IF_0x00120125: .word 0x00120125
+M4IF_0x001901A3: .word 0x001901A3
+M4IF_0x00000203: .word 0x00000203
SDRAM_0x04008008: .word 0x04008008
SDRAM_0x00008010: .word 0x00008010
SDRAM_0x00338018: .word 0x00338018
CCM_VAL_0x0000E3C2: .word 0x0000E3C2
CCM_VAL_0x000020C2: .word 0x000020C2
CCM_VAL_0x013B9100: .word 0x013B9100
-CCM_VAL_0x59239100: .word 0x59239100
-CCM_VAL_0x19239100: .word 0x19239100
+CCM_VAL_0x59E35100: .word 0x59E35100
+CCM_VAL_0x61E35100: .word 0x61E35100
+CCM_VAL_0x19239145: .word 0x19239145
CCM_VAL_0xA5A2A020: .word 0xA5A2A020
CCM_VAL_0x00C30321: .word 0x00C30321
-CCM_VAL_0x0000D3C0: .word 0x0000D3C0
-CCM_VAL_0x033B9145: .word 0x033B9145
-CCM_VAL_0x013B9145: .word 0x013B9145
-CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+CCM_VAL_0x000010C0: .word 0x000010C0
+CCM_VAL_0x13239145: .word 0x13239145
+CCM_VAL_0x000020C0: .word 0x000020C0
PLL_VAL_0x222: .word 0x222
PLL_VAL_0x232: .word 0x232
BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
W_DP_MFD_216: .word DP_MFD_216
W_DP_MFN_216: .word DP_MFN_216
PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000725
-_nand_pg_sz: .word 0
+PLATFORM_CLOCK_DIV_W: .word 0x00000124
/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
extern unsigned int cpld_base_addr;
#define LAN92XX_REG_READ(reg_offset) \
- (*(volatile unsigned int *)(cpld_base_addr + reg_offset))
+ (*(volatile unsigned int *)(cpld_base_addr + reg_offset))
#define LAN92XX_REG_WRITE(reg_offset, val) \
- (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val))
+ (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val))
-#define LED_IS_ON(n) ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0)
+#define LED_IS_ON(n) ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0)
#define TURN_LED_ON(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) | (1 << (n))), cpld_base_addr + PBC_LED_CTRL)
#define TURN_LED_OFF(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) & (~(1<<(n)))), cpld_base_addr + PBC_LED_CTRL)
-#define BOARD_DEBUG_LED(n) 0
+#define BOARD_DEBUG_LED(n) CYG_EMPTY_STATEMENT
/*
-#define BOARD_DEBUG_LED(n) \
+#define BOARD_DEBUG_LED(n) \
CYG_MACRO_START \
- if (n >= 0 && n < LED_MAX_NUM) { \
- if (LED_IS_ON(n)) \
- TURN_LED_OFF(n); \
- else \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
TURN_LED_ON(n); \
} \
CYG_MACRO_END
extern unsigned int system_rev;
-#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
- CYG_MACRO_START \
- { \
- extern unsigned int system_rev; \
- /* Next ATAG_MEM. */ \
- _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
- _p_->hdr.tag = ATAG_MEM; \
- /* Round up so there's only one bit set in the memory size. \
- * Don't double it if it's already a power of two, though. \
- */ \
- _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
- if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
- _p_->u.mem.size <<= 1; \
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) \
- _p_->u.mem.size = 512 * 0x100000; \
- _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
- _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
- _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \
- _p_->hdr.tag = ATAG_REVISION; \
- _p_->u.revision.rev = system_rev; \
- } \
- CYG_MACRO_END
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) \
+ _p_->u.mem.size = 512 * 0x100000; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
package -hardware CYGPKG_IO_ETH_DRIVERS current ;
package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
- package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ #package -hardware CYGPKG_DEVS_ETH_FEC current ;
package -hardware CYGPKG_COMPRESS_ZLIB current ;
package -hardware CYGPKG_DIAGNOSIS current ;
package -hardware CYGPKG_IO_FLASH current ;
package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
package -hardware CYGPKG_DEVS_IMX_SPI current ;
package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_IMX_IPU current ;
+ package -hardware CYGPKG_IMX_CMDS current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
};
cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
- inferred_value 0
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ inferred_value 1
};
cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
inferred_value 1
};
+cdl_option CYGHWR_DEVS_IPU_3_EX {
+ inferred_value 1
+};
+
cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
inferred_value 0
};
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200904"
+ user_value 1 "FSL 200938"
};
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "" ;
+ hardware mx51_3stack ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+ package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+ #package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_DIAGNOSIS current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_IMX_IPU current ;
+ package -hardware CYGPKG_IMX_CMDS current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGHWR_MX51_MDDR {
+ inferred_value 1
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_IPU_3_EX {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+ user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+ user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+ user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+ user_value 1
+};
+
+cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
+ user_value 0
+};
+
+#cdl_component CYGPKG_WDT_DIAGNOSIS {
+# user_value 1
+#};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+ inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ user_value 1 "FSL 200938"
+};
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_soc.h> // Hardware definitions
#include <cyg/hal/fsl_board.h> // Platform specifics
+#include <cyg/hal/mx51_iomux.h>
#include <cyg/io/mxc_i2c.h>
#include <cyg/io/imx_nfc.h>
#include <cyg/infra/diag.h> // diag_printf
// All the MM table layout is here:
#include <cyg/hal/hal_mm.h>
+#include <cyg/io/imx_spi.h>
externC void* memset(void *, int, size_t);
extern nfc_iomuxsetup_func_t *nfc_iomux_setup;
unsigned int cpld_base_addr;
+struct spi_v2_3_reg spi_nor_reg;
+struct imx_spi_dev imx_spi_nor = {
+ base : CSPI2_BASE_ADDR,
+ freq : 25000000,
+ ss_pol : IMX_SPI_ACTIVE_LOW,
+ ss : 1,
+ fifo_sz : 32,
+ us_delay: 0,
+ reg : &spi_nor_reg,
+};
+
+imx_spi_init_func_t *spi_nor_init;
+imx_spi_xfer_func_t *spi_nor_xfer;
+
void hal_mmu_init(void)
{
unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
X_ARM_MMU_SECTION(0x900, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0x900, 0x900, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0x900, 0x980, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xA00, 0xA00, 0x100, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
}
switch (module_base) {
case I2C_BASE_ADDR:
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x600;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B4;
- writel(0x1, reg);
-
- reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x614;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0x9B0;
- writel(0x1, reg);
- } else {
- reg = IOMUXC_BASE_ADDR + 0x230; // i2c SCL
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x6e0;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0xA00;
- writel(0x1, reg);
-
- reg = IOMUXC_BASE_ADDR + 0x21C; // i2c SDA
- writel(0x11, reg);
- reg = IOMUXC_BASE_ADDR + 0x6cc;
- writel(0x1ad, reg);
- reg = IOMUXC_BASE_ADDR + 0xA04;
- writel(0x1, reg);
- }
+ reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x600;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0x9B4;
+ writel(0x1, reg);
+
+ reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
+ writel(0x11, reg);
+ reg = IOMUXC_BASE_ADDR + 0x614;
+ writel(0x1ad, reg);
+ reg = IOMUXC_BASE_ADDR + 0x9B0;
+ writel(0x1, reg);
break;
case I2C2_BASE_ADDR:
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- /* Workaround for Atlas Lite */
- writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
- writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg |= 0xC; // write a 1 on the SCL and SDA lines
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg |= 0xC; // configure GPIO lines as output
- writel(reg, GPIO1_BASE_ADDR + 0x4);
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg &= ~0x4 ; // set SCL low for a few milliseconds
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- hal_delay_us(20000);
- reg |= 0x4;
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- hal_delay_us(10);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg &= ~0xC; // configure GPIO lines back as input
- writel(reg, GPIO1_BASE_ADDR + 0x4);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
- writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
- writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
- } else {
- /* Workaround for Atlas Lite */
- writel(0x0, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
- writel(0x0, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg |= 0xC; // write a 1 on the SCL and SDA lines
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg |= 0xC; // configure GPIO lines as output
- writel(reg, GPIO1_BASE_ADDR + 0x4);
- reg = readl(GPIO1_BASE_ADDR + 0x0);
- reg &= ~0x4 ; // set SCL low for a few milliseconds
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- hal_delay_us(20000);
- reg |= 0x4;
- writel(reg, GPIO1_BASE_ADDR + 0x0);
- hal_delay_us(10);
- reg = readl(GPIO1_BASE_ADDR + 0x4);
- reg &= ~0xC; // configure GPIO lines back as input
- writel(reg, GPIO1_BASE_ADDR + 0x4);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
- writel(0x3, IOMUXC_BASE_ADDR + 0xA08);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A0);
-
- writel(0x12, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
- writel(0x3, IOMUXC_BASE_ADDR + 0xA0C);
- writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A4);
- }
+ /* Workaround for Atlas Lite */
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+ writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg |= 0xC; // write a 1 on the SCL and SDA lines
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg |= 0xC; // configure GPIO lines as output
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+ reg = readl(GPIO1_BASE_ADDR + 0x0);
+ reg &= ~0x4 ; // set SCL low for a few milliseconds
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(20000);
+ reg |= 0x4;
+ writel(reg, GPIO1_BASE_ADDR + 0x0);
+ hal_delay_us(10);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg &= ~0xC; // configure GPIO lines back as input
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
break;
default:
diag_printf("Invalid I2C base: 0x%x\n", module_base);
// config NANDF_WE_B pad for pata instance DIOW port
// config_pad_mode(NANDF_WE_B, ALT1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to Pull (Different from Module Level value: NA)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_WE_B, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
// config NANDF_RE_B pad for pata instance DIOR port
// config_pad_mode(NANDF_RE_B, ALT1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to Pull (Different from Module Level value: NA)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_RE_B, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE);
// config NANDF_CLE pad for pata instance PATA_RESET_B port
// config_pad_mode(NANDF_CLE, ALT1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Hyst. Enable to Disabled
- // Pull / Keep Select to Keep (Different from Module Level value: NA)
- // Pull Up / Down Config. to 100Kohm PU (Different from Module Level value: NA)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CLE, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
// config NANDF_WP_B pad for pata instance DMACK port
// config_pad_mode(NANDF_WP_B, ALT1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to Pull (Different from Module Level value: NA)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_WP_B, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
// config NANDF_RB0 pad for pata instance DMARQ port
// config_pad_mode(NANDF_RB0, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled (Different from Module Level value: NA)
- // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to CFG(360Kohm PD)
- // config_pad_settings(NANDF_RB0, 0x20c0);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
// config NANDF_RB1 pad for pata instance IORDY port
// config_pad_mode(NANDF_RB1, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to NA (CFG in SoC Level however NA in Module Level)
- // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // config_pad_settings(NANDF_RB1, 0x20e0);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
// config NANDF_RB5 pad for pata instance INTRQ port
// config_pad_mode(NANDF_RB5, 0x1);
- writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull Up / Down Config. to 100Kohm PU
- // Open Drain Enable to Disabled (Different from Module Level value: NA)
- // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // config_pad_settings(NANDF_RB5, 0x20c0);
- writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5);
+ writel(0x1, IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND);
+ writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND);
// config NANDF_CS2 pad for pata instance CS_0 port
// config_pad_mode(NANDF_CS2, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Open Drain Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CS2, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
// config NANDF_CS3 pad for pata instance CS_1 port
// config_pad_mode(NANDF_CS3, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Open Drain Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CS3, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
// config NANDF_CS4 pad for pata instance DA_0 port
// config_pad_mode(NANDF_CS4, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CS4, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
// config NANDF_CS5 pad for pata instance DA_1 port
// config_pad_mode(NANDF_CS5, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CS5, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
// config NANDF_CS6 pad for pata instance DA_2 port
// config_pad_mode(NANDF_CS6, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull / Keep Select to Pull (Different from Module Level value: NA)
- // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_CS6, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
// config NANDF_D15 pad for pata instance PATA_DATA[15] port
// config_pad_mode(NANDF_D15, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D15, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
// config NANDF_D14 pad for pata instance PATA_DATA[14] port
// config_pad_mode(NANDF_D14, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D14, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
// config NANDF_D13 pad for pata instance PATA_DATA[13] port
// config_pad_mode(NANDF_D13, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D13, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
// config NANDF_D12 pad for pata instance PATA_DATA[12] port
// config_pad_mode(NANDF_D12, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D12, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
// config NANDF_D11 pad for pata instance PATA_DATA[11] port
// config_pad_mode(NANDF_D11, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D11, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
// config NANDF_D10 pad for pata instance PATA_DATA[10] port
// config_pad_mode(NANDF_D10, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D10, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
// config NANDF_D9 pad for pata instance PATA_DATA[9] port
// config_pad_mode(NANDF_D9, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D9, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
// config NANDF_D8 pad for pata instance PATA_DATA[8] port
// config_pad_mode(NANDF_D8, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D8, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
// config NANDF_D7 pad for pata instance PATA_DATA[7] port
// config_pad_mode(NANDF_D7, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull Up / Down Config. to 100Kohm PU
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D7, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
// config NANDF_D6 pad for pata instance PATA_DATA[6] port
// config_pad_mode(NANDF_D6, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull Up / Down Config. to 100Kohm PU
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Open Drain Enable to Disabled
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D6, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
// config NANDF_D5 pad for pata instance PATA_DATA[5] port
// config_pad_mode(NANDF_D5, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull Up / Down Config. to 100Kohm PU
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D5, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
// config NANDF_D4 pad for pata instance PATA_DATA[4] port
// config_pad_mode(NANDF_D4, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Pull Up / Down Config. to 100Kohm PU
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D4, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
// config NANDF_D3 pad for pata instance PATA_DATA[3] port
// config_pad_mode(NANDF_D3, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D3, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
// config NANDF_D2 pad for pata instance PATA_DATA[2] port
// config_pad_mode(NANDF_D2, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D2, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
// config NANDF_D1 pad for pata instance PATA_DATA[1] port
// config_pad_mode(NANDF_D1, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D1, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
// config NANDF_D0 pad for pata instance PATA_DATA[0] port
// config_pad_mode(NANDF_D0, 0x1);
writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
- // CONSTANT SETTINGS:
- // test_ts to Disabled
- // dse test to regular
- // strength mode to NA (Different from Module Level value: 4_level)
- // DDR / CMOS Input Mode to NA
- // Open Drain Enable to Disabled
- // Slew Rate to NA
- // CONFIGURED SETTINGS:
- // low/high output voltage to CFG(High)
- // Hyst. Enable to Disabled
- // Pull / Keep Enable to CFG(Enabled)
- // Pull / Keep Select to Pull
- // Pull Up / Down Config. to 100Kohm PU
- // Drive Strength to CFG(High)
- // config_pad_settings(NANDF_D0, 0x2004);
writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
}
{
volatile unsigned int reg;
- /* No FEC support for TO 2.0 yet */
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2)
+ /* No FEC support for TO 2.0 and higher yet */
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2)
return;
/*FEC_TX_CLK*/
writel(0x2, IOMUXC_BASE_ADDR + 0x0390);
static void mxc_nfc_iomux_setup(void)
{
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- writel(0x0, IOMUXC_BASE_ADDR + 0x108);
- writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x110);
- writel(0x0, IOMUXC_BASE_ADDR + 0x114);
- writel(0x0, IOMUXC_BASE_ADDR + 0x118);
- writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x120);
- writel(0x0, IOMUXC_BASE_ADDR + 0x124);
- writel(0x0, IOMUXC_BASE_ADDR + 0x128);
- writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x130);
- writel(0x0, IOMUXC_BASE_ADDR + 0x134);
- writel(0x0, IOMUXC_BASE_ADDR + 0x138);
- writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x140);
- writel(0x0, IOMUXC_BASE_ADDR + 0x144);
- writel(0x0, IOMUXC_BASE_ADDR + 0x148);
- writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x150);
- writel(0x0, IOMUXC_BASE_ADDR + 0x154);
- writel(0x0, IOMUXC_BASE_ADDR + 0x158);
- writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x160);
- writel(0x0, IOMUXC_BASE_ADDR + 0x164);
- writel(0x0, IOMUXC_BASE_ADDR + 0x168);
- writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x170);
- writel(0x0, IOMUXC_BASE_ADDR + 0x174);
- writel(0x0, IOMUXC_BASE_ADDR + 0x178);
- writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x180);
- writel(0x0, IOMUXC_BASE_ADDR + 0x184);
- writel(0x0, IOMUXC_BASE_ADDR + 0x188);
- writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x190);
- } else {
- writel(0x0, IOMUXC_BASE_ADDR + 0x108);
- writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x110);
- writel(0x0, IOMUXC_BASE_ADDR + 0x114);
- writel(0x0, IOMUXC_BASE_ADDR + 0x118);
- writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x120);
- writel(0x0, IOMUXC_BASE_ADDR + 0x124);
- writel(0x0, IOMUXC_BASE_ADDR + 0x128);
- writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x130);
- writel(0x0, IOMUXC_BASE_ADDR + 0x134);
- writel(0x0, IOMUXC_BASE_ADDR + 0x138);
- writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x140);
- writel(0x0, IOMUXC_BASE_ADDR + 0x144);
- writel(0x0, IOMUXC_BASE_ADDR + 0x148);
- writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x150);
- writel(0x0, IOMUXC_BASE_ADDR + 0x154);
- writel(0x0, IOMUXC_BASE_ADDR + 0x158);
- writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x160);
- writel(0x0, IOMUXC_BASE_ADDR + 0x164);
- writel(0x0, IOMUXC_BASE_ADDR + 0x168);
- writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x170);
- writel(0x0, IOMUXC_BASE_ADDR + 0x174);
- writel(0x0, IOMUXC_BASE_ADDR + 0x178);
- writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x180);
- writel(0x0, IOMUXC_BASE_ADDR + 0x184);
- writel(0x0, IOMUXC_BASE_ADDR + 0x188);
- writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x190);
- writel(0x0, IOMUXC_BASE_ADDR + 0x194);
- writel(0x0, IOMUXC_BASE_ADDR + 0x198);
- writel(0x0, IOMUXC_BASE_ADDR + 0x19C);
- }
+ writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x110);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x114);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x118);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x120);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x124);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x128);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x130);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x134);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x138);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x140);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x144);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x154);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x170);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x174);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x178);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x180);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x184);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x188);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x190);
}
-//
-// Platform specific initialization
-//
+#define REV_ATLAS_LITE_2_0 0x20
-void plf_hardware_init(void)
+void setup_core_voltages(void)
{
- unsigned long sw_rest_reg, weim_base;
- unsigned int reg;
- unsigned char buf[4];
struct mxc_i2c_request rq;
+ unsigned char buf[4];
+
+ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+ rq.dev_addr = 0x8;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
- /* Atlas Workaround needed only for TO 1.0 and 1.1 boards */
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) != 0x2) {
- if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
- rq.dev_addr = 0x8;
- rq.reg_addr = 0x7;
- rq.reg_addr_sz = 1;
- rq.buffer_sz = 3;
- rq.buffer = buf;
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
+ /* Set core voltage to 1.1V */
+ rq.reg_addr = 24;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0x1F)) | 0x14;
+ i2c_xfer(1, &rq, 0);
+
+ /* Setup VCC (SW2) to 1.25 */
+ rq.reg_addr = 25;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+ i2c_xfer(1, &rq, 0);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ rq.reg_addr = 26;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+ i2c_xfer(1, &rq, 0);
+ hal_delay_us(50);
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+ } else {
+ /* TO 3.0 */
+ /* Setup VCC (SW2) to 1.225 */
+ rq.reg_addr = 25;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0x1F)) | 0x19;
+ i2c_xfer(1, &rq, 0);
+ /* Setup 1V2_DIG1 (SW3) to 1.2 */
+ rq.reg_addr = 26;
i2c_xfer(1, &rq, 1);
- /* Make sure we implement this workaround only for boards with Atlas-Lite to turn off the charger */
- if ((buf[1] == 0x41) && (buf[2] == 0xc8 || buf[2] == 0xc9)) {
- buf[0] = 0xb4;
- buf[1] = 0x0;
- buf[2] = 0x3;
- rq.dev_addr = 0x8;
- rq.reg_addr = 0x30;
- rq.reg_addr_sz = 1;
- rq.buffer_sz = 3;
- rq.buffer = buf;
-
- i2c_xfer(1, &rq, 0);
- }
+ buf[2] = (buf[2] & (~0x1F)) | 0x18;
+ i2c_xfer(1, &rq, 0);
+ }
+
+ rq.reg_addr = 7;
+ i2c_xfer(1, &rq, 1);
+
+ if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
+ /* Set switchers in PWM mode for Atlas 2.0 and lower */
+ /* Setup the switcher mode for SW1 & SW2*/
+ rq.reg_addr = 28;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0xF)) | 0x5;
+ buf[1] = (buf[1] & (~0x3C)) | 0x14;
+ i2c_xfer(1, &rq, 0);
+
+ /* Setup the switcher mode for SW3 & SW4*/
+ rq.reg_addr = 29;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0xF)) | 0x5;
+ buf[1] = (buf[1] & (~0xF)) | 0x5;
+ i2c_xfer(1, &rq, 0);
+ } else {
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+ /* Setup the switcher mode for SW1 & SW2*/
+ rq.reg_addr = 28;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0xF)) | 0x8;
+ buf[1] = (buf[1] & (~0x3C)) | 0x20;
+ i2c_xfer(1, &rq, 0);
+
+ /* Setup the switcher mode for SW3 & SW4*/
+ rq.reg_addr = 29;
+ i2c_xfer(1, &rq, 1);
+ buf[2] = (buf[2] & (~0xF)) | 0x8;
+ buf[1] = (buf[1] & (~0xF)) | 0x8;
+ i2c_xfer(1, &rq, 0);
}
}
- // CS5 setup
- writel(0, IOMUXC_BASE_ADDR + 0xF4);
- weim_base = WEIM_BASE_ADDR + 0x78;
- writel(0x00410089, weim_base + CSGCR1);
- writel(0x00000002, weim_base + CSGCR2);
- // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
- writel(0x32260000, weim_base + CSRCR1);
- // APR=0
- writel(0x00000000, weim_base + CSRCR2);
- // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
- writel(0x72080F00, weim_base + CSWCR1);
- cpld_base_addr = CS5_BASE_ADDR;
-
- /* Reset interrupt status reg */
- writew(0x1F, cpld_base_addr + PBC_INT_REST);
- writew(0x00, cpld_base_addr + PBC_INT_REST);
- writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
-
- /* Reset the XUART and Ethernet controllers */
- sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
- sw_rest_reg |= 0x9;
- writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
- sw_rest_reg &= ~0x9;
- writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
-
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- // UART1
- //RXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x228);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
- //TXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
- //RTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x230);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
- //CTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x234);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
- // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
- writel(0x00000004, 0x73fa83E8);
- writel(0x00000004, 0x73fa83Ec);
- } else {
- // UART1
- //RXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x234);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
- //TXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x238);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
- //RTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
- //CTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x240);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
- // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
- writel(0x00000004, 0x73fa83F4);
- writel(0x00000004, 0x73fa83F0);
- }
+}
+
+//
+// Platform specific initialization
+//
- // enable ARM clock div by 8
- writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
+void plf_hardware_init(void)
+{
+ unsigned long sw_rest_reg, weim_base;
+
+ setup_core_voltages();
+ // CS5 setup
+ writel(0, IOMUXC_BASE_ADDR + 0xF4);
+ weim_base = WEIM_BASE_ADDR + 0x78;
+ writel(0x00410089, weim_base + CSGCR1);
+ writel(0x00000002, weim_base + CSGCR2);
+ // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
+ writel(0x32260000, weim_base + CSRCR1);
+ // APR=0
+ writel(0x00000000, weim_base + CSRCR2);
+ // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
+ writel(0x72080F00, weim_base + CSWCR1);
+ cpld_base_addr = CS5_BASE_ADDR;
+
+ /* Reset interrupt status reg */
+ writew(0x1F, cpld_base_addr + PBC_INT_REST);
+ writew(0x00, cpld_base_addr + PBC_INT_REST);
+ writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
+
+ /* Reset the XUART and Ethernet controllers */
+ sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
+ sw_rest_reg |= 0x9;
+ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+ sw_rest_reg &= ~0x9;
+ writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+
+ // UART1
+ //RXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
+ //TXD
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
+ //RTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
+ //CTS
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
+ // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+ writel(0x00000004, 0x73fa83E8);
+ writel(0x00000004, 0x73fa83Ec);
+
+ // enable ARM clock div by 8
+ writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
#ifdef MXCFLASH_SELECT_NAND
- nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
+ nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
#endif
- mxc_fec_setup();
+ mxc_fec_setup();
+
+ spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+}
+
+
+void mxc_ipu_iomux_config(void)
+{
+ // configure display data0~17 for Epson panel
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2,0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10, 0x5);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17, 0x5);
+
+ // DI1_PIN2 and DI1_PIN3, configured to be HSYNC and VSYNC of Epson LCD
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+
+ // PCLK - DISP_CLK
+ // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+ // DRDY - PIN15
+ // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+ // configure this pin to be the SER_DISP_CS
+
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT4);
+ CONFIG_PIN(IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS,0x85);
+
+ // configure to be DISPB1_SER_RS
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP1, 0x85);
+ // configure to be SER_DISP1_CLK
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP2, 0x85);
+ // configure to be DISPB1_SER_DIO
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP3, 0xC5);
+ // configure to be DISPB1_SER_DIN
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP4, 0xC4);
+ //CS0
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS, 0x85);
+ // WR
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11, 0x85);
+ // RD
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12, 0x85);
+ // RS
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13, 0x85);
+
}
void mxc_mmc_init(unsigned int base_address)
{
switch(base_address) {
case MMC_SDHC1_BASE_ADDR:
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- /* SD1 CMD, SION bit */
- writel(0x10, IOMUXC_BASE_ADDR + 0x394);
- /* Configure SW PAD */
- /* SD1 CMD */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x79C);
- /* SD1 CLK */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A0);
- /* SD1 DAT0 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A4);
- /* SD1 DAT1 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A8);
- /* SD1 DAT2 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x7AC);
- /* SD1 DAT3 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x7B0);
- } else {
- /* SD1 CMD, SION bit */
- writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
- /* SD1 CD, as gpio1_0 */
- writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
- /* Configure SW PAD */
- /* SD1 CMD */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
- /* SD1 CLK */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
- /* SD1 DAT0 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
- /* SD1 DAT1 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
- /* SD1 DAT2 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
- /* SD1 DAT3 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
- /* SD1 CD as gpio1_0 */
- writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
- }
+ /* SD1 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x394);
+ /* Configure SW PAD */
+ /* SD1 CMD */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x79C);
+ /* SD1 CLK */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0);
+ /* SD1 DAT0 */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4);
+ /* SD1 DAT1 */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8);
+ /* SD1 DAT2 */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC);
+ /* SD1 DAT3 */
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0);
break;
default:
break;
unsigned char buf[4];
struct mxc_i2c_request rq;
+ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+ rq.dev_addr = 0x8;
+ rq.reg_addr = 24;
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = 3;
+ rq.buffer = buf;
- rq.dev_addr = 0x8;
- rq.reg_addr = 24;
- rq.reg_addr_sz = 1;
- rq.buffer_sz = 3;
- rq.buffer = buf;
+ i2c_xfer(1, &rq, 1);
- i2c_xfer(1, &rq, 1);
-
- if (i) {
- buf[2] = buf[2] & (~0x1F) | 0x17;
+ if (i) {
+ buf[2] = (buf[2] & (~0x1F)) | 0x17; //1.175
+ //buf[2] = (buf[2] & (~0x1F)) | 0x18; //1.2
+ } else {
+ buf[2] = (buf[2] & (~0x1F)) | 0x12;
+ }
+ i2c_xfer(1, &rq, 0);
} else {
- buf[2] = buf[2] & (~0x1F) | 0x12;
+ diag_printf("Cannot increase core voltage, failed to initialize I2C2\n");
+ }
+}
+
+void io_cfg_spi(struct imx_spi_dev *dev)
+{
+ unsigned int reg;
+
+ switch (dev->base) {
+ case CSPI1_BASE_ADDR:
+ break;
+ case CSPI2_BASE_ADDR:
+ // Select mux mode: ALT2 mux port: MOSI of instance: ecspi2
+ writel(0x2, IOMUXC_BASE_ADDR + 0x154);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x53C);
+
+ // Select mux mode: ALT2 mux port: MISO of instance: ecspi2.
+ writel(0x2, IOMUXC_BASE_ADDR + 0x128);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x504);
+
+ // de-select SS0 of instance: ecspi1.
+ writel(0x2, IOMUXC_BASE_ADDR + 0x298);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x698);
+ // Select mux mode: ALT2 mux port: SS1 of instance: ecspi2.
+ writel(0x2, IOMUXC_BASE_ADDR + 0x160);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x548);
+
+ // Select mux mode: ALT3 mux port: GPIO mode
+ writel(0x3, IOMUXC_BASE_ADDR + 0x150);
+ writel(0xE0, IOMUXC_BASE_ADDR + 0x538);
+ reg = readl(GPIO3_BASE_ADDR + 0x0);
+ reg |= 0x1000000; // write a 1
+ writel(reg, GPIO3_BASE_ADDR + 0x0);
+ reg = readl(GPIO3_BASE_ADDR + 0x4);
+ reg |= 0x1000000; // configure GPIO lines as output
+ writel(reg, GPIO3_BASE_ADDR + 0x4);
+
+ // Select mux mode: ALT2 mux port: SCLK of instance: ecspi2.
+ writel(0x2, IOMUXC_BASE_ADDR + 0x124);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x500);
+ break;
+ default:
+ break;
}
- i2c_xfer(1, &rq, 0);
}
+
#include CYGHWR_MEMORY_LAYOUT_H
typedef void code_fun(void);
--- /dev/null
+//==========================================================================
+//
+// epson_lcd.c
+//
+// LCD Display Implementation
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+#include <cyg/io/mxc_i2c.h>
+
+#define MX51_ATLAS_PMIC_ADDRESS 0x8
+
+static int pmic_read_reg(unsigned int reg_addr, unsigned char *data, unsigned int count)
+{
+ struct mxc_i2c_request rq;
+
+ rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS; // dev_addr of Atlas PMIC
+ rq.reg_addr = reg_addr; // addr of LEC Control0 Reg
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = count; // send 3 data in a series
+ rq.buffer = data;
+ i2c_xfer(1, &rq, 1);
+
+ return 1;
+}
+
+static int pmic_write_reg(unsigned int reg_addr, unsigned char *data, unsigned int count)
+{
+ struct mxc_i2c_request rq;
+
+ rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS; // dev_addr of Atlas PMIC
+ rq.reg_addr = reg_addr; // addr of LEC Control0 Reg
+ rq.reg_addr_sz = 1;
+ rq.buffer_sz = count; // send 3 data in a series
+ rq.buffer = data;
+ i2c_xfer(1, &rq, 0);
+
+ return 1;
+}
+
+/*this function use common pins of IPU to simulate a cspi interface*/
+static void epson_lcd_spi_simulate(void)
+{
+ dc_microcode_t microcode = { 0 };
+ microcode.addr = 0x24;
+ microcode.stop = 1;
+ microcode.opcode = "WROD";
+ microcode.lf = 0;
+ microcode.af = 0;
+ microcode.operand = 0;
+ microcode.mapping = 5;
+ microcode.waveform = 7;
+ microcode.gluelogic = 0;
+ microcode.sync = 0;
+ ipu_dc_microcode_config(microcode);
+
+ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1, 0x24); //address of second region
+ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0, 0x24); //address of first region
+ ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8, 1); //MEDIUM PRIORITY FOR DATA
+
+ /* Data Mapping of 24-bit new data
+ |23..16|15..8|7..0| ==>> bit[15..0]&(0x1FF), just keep the last 17bit for LCD configuration */
+ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4, 3);
+ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4, 4);
+ ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4, 5);
+ ipu_write_field(IPU_DC_MAP_CONF_16__MD_OFFSET_3, 0);
+ ipu_write_field(IPU_DC_MAP_CONF_16__MD_MASK_3, 0x00);
+ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_4, 15);
+ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_4, 0x01);
+ ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_5, 7);
+ ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_5, 0xFF);
+
+ /*set clock and cs signal for command.
+ sclk should be more than 90ns interval, derived from base clock. */
+ ipu_di_waveform_config(0, 6, 0, 0, 11);
+ ipu_di_waveform_config(0, 6, 1, 1, 2);
+ ipu_di_waveform_config(0, 6, 2, 0, 0);
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6, 3); //base clock, 133MHz/div
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6, 0); //start immediatly
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_CST_6, 0); //pointer for CS
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6, 8); //8+1 bit, should be more than or equal with 9
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6, 2); //RS=0
+ ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6, 1); //SCLK for command, should be less than 11MHz
+ ipu_write_field(IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY, 1);
+ ipu_write_field(IPU_IPU_DISP_GEN__MCU_DI_ID_8, 0); //MCU accesses DC's channel #8 via DI0.
+
+ /* T VALUE, seperate into two parts */
+ ipu_write_field(IPU_IPU_DISP_GEN__MCU_T, T_VALUE); //diffrenciate
+
+ ipu_write_field(IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8, 1); //display 1
+ ipu_write_field(IPU_DC_WR_CH_CONF1_8__W_SIZE_8, 3); //32 bits are used (RGB)
+
+ ipu_write_field(IPU_DC_DISP_CONF1_1__DISP_TYP_1, 0); //serial display
+
+ ipu_write_field(IPU_IPU_CONF__DI0_EN, 1);
+ ipu_write_field(IPU_IPU_CONF__DP_EN, 0);
+ ipu_write_field(IPU_IPU_CONF__DC_EN, 1);
+ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 1);
+}
+
+static void epson_lcd_rst(void)
+{
+ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 1);
+ hal_delay_us(1000);
+ ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 0);
+}
+
+void lcd_backlit_on(void)
+{
+ struct mxc_i2c_request rq;
+ unsigned char data[3];
+ unsigned char dataCheck[3];
+ int timeout = 0;
+ int ret = 0xFF;
+ /*duty cycle = (mainDispDutyCycle % 32) / 32; */
+ unsigned char mainDispDutyCycle = 0x20;
+ /*current = mainDispCurrentSet * 3 * 2^mainDispHiCurMode
+ current should be no more than 15 */
+ unsigned char mainDispCurrentSet = 3;
+ unsigned char mainDispHiCurMode = 0;
+
+#ifndef CYGPKG_REDBOOT
+ mxc_i2c2_clock_gate(1);
+#endif
+ if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+ while (timeout < 5) {
+ data[0] = 0x0;
+ data[1] = ((mainDispCurrentSet << 1) & 0xE) | ((mainDispDutyCycle >> 5) & 0x1);
+ data[2] = ((mainDispHiCurMode << 1) & 0x2) | ((mainDispDutyCycle << 3) & 0xF8);
+ pmic_write_reg(0x33, data, 3);
+ dataCheck[0] = 0x0;
+ dataCheck[1] = 0x0;
+ dataCheck[2] = 0x0;
+ pmic_read_reg(0x33, dataCheck, 3);
+
+ if ((dataCheck[0] == data[0]) && (dataCheck[1] == data[1]) && (dataCheck[2] == data[2])) {
+ break;
+ }
+ timeout++;
+ hal_delay_us(20);
+ }
+ } else {
+ diag_printf("ERROR:I2C initialization failed\n");
+ }
+#ifndef CYGPKG_REDBOOT
+ mxc_i2c2_clock_gate(0);
+#endif
+}
+
+void lcd_config(void)
+{
+ /* set these regs to conpensate color. */
+ writel((readl(MIPI_HSC_BASE_ADDR + 0x800) | (1<<16)), MIPI_HSC_BASE_ADDR + 0x800);
+ writel((readl(MIPI_HSC_BASE_ADDR + 0x0) | (1<<10)), MIPI_HSC_BASE_ADDR + 0x0);
+
+ /* simulate spi interface to access LCD regs */
+ epson_lcd_spi_simulate();
+ epson_lcd_rst();
+
+ /* enable chip select */
+ gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT);
+ gpio_write_data(GPIO_PORT3, 4, 0);
+ hal_delay_us(300);
+
+ writel(MADCTL, IPU_CTRL_BASE_ADDR);
+ writel(0x0100, IPU_CTRL_BASE_ADDR);
+
+ writel(GAMSET, IPU_CTRL_BASE_ADDR);
+ writel(0x0101, IPU_CTRL_BASE_ADDR);
+
+ writel(COLMOD, IPU_CTRL_BASE_ADDR);
+ writel(0x0160, IPU_CTRL_BASE_ADDR);
+
+ writel(SLPOUT, IPU_CTRL_BASE_ADDR); // SLEEP OUT
+ hal_delay_us(300);
+
+ writel(DISON, IPU_CTRL_BASE_ADDR); // Display ON
+ hal_delay_us(300);
+
+ /* disable chip select */
+ gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT);
+ gpio_write_data(GPIO_PORT3, 4, 1);
+
+ ipu_write_field(IPU_IPU_CONF__DI0_EN, 0);
+ ipu_write_field(IPU_IPU_CONF__DP_EN, 0);
+ ipu_write_field(IPU_IPU_CONF__DC_EN, 0);
+ ipu_write_field(IPU_IPU_CONF__DMFC_EN, 0);
+ hal_delay_us(300);
+}
--- /dev/null
+//==========================================================================
+//
+// mx51_fastlogo.c
+//
+// MX51 Fast Logo Implementation
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+
+// DI counter definitions
+#define DI_COUNTER_BASECLK 0
+#define DI_COUNTER_IHSYNC 1
+#define DI_COUNTER_OHSYNC 2
+#define DI_COUNTER_OVSYNC 3
+#define DI_COUNTER_ALINE 4
+#define DI_COUNTER_ACLOCK 5
+
+extern display_buffer_info_t display_buffer;
+
+void fastlogo_dma(void)
+{
+ ipu_channel_parameter_t ipu_channel_params;
+ ipu_idmac_channel_enable(DISPLAY_CHANNEL, 0);
+
+ ipu_idmac_params_init(&ipu_channel_params);
+ ipu_channel_params.channel = DISPLAY_CHANNEL;
+ ipu_channel_params.eba0 = (unsigned int)(display_buffer.startAddr) / 8;
+ ipu_channel_params.fw = display_buffer.width - 1; //frame width
+ ipu_channel_params.fh = display_buffer.height - 1; //frame height
+ ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1;
+ ipu_channel_params.npb = 31; //16 pixels per burst
+ ipu_channel_params.pfs = 7; //1->4:2:2 non-interleaved, 7->rgb
+
+ switch(display_buffer.bpp) {
+ case 32:
+ ipu_channel_params.bpp = 0;
+ break;
+ case 24:
+ ipu_channel_params.bpp = 1;
+ break;
+ case 18:
+ ipu_channel_params.bpp = 2;
+ break;
+ case 16:
+ ipu_channel_params.bpp = 3;
+ break;
+ default:
+ diag_printf("data bpp format not supported!\n");
+ }
+
+ switch(display_buffer.dataFormat) {
+ case RGB565:
+ ipu_channel_params.wid0 = 5 - 1; //bits
+ ipu_channel_params.wid1 = 6 - 1; //bits;
+ ipu_channel_params.wid2 = 5 - 1; //bits;
+ ipu_channel_params.wid3 = 0; //bits;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 5;
+ ipu_channel_params.ofs2 = 11;
+ ipu_channel_params.ofs3 = 16;
+ break;
+
+ case RGB666:
+ ipu_channel_params.wid0 = 6 - 1; //bits
+ ipu_channel_params.wid1 = 6 - 1; //bits;
+ ipu_channel_params.wid2 = 6 - 1; //bits;
+ ipu_channel_params.wid3 = 0; //bits;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 6;
+ ipu_channel_params.ofs2 = 12;
+ ipu_channel_params.ofs3 = 18;
+ break;
+ case RGB888:
+ ipu_channel_params.wid0 = 8 - 1; //bits
+ ipu_channel_params.wid1 = 8 - 1; //bits;
+ ipu_channel_params.wid2 = 8 - 1; //bits;
+ ipu_channel_params.wid3 = 0; //bits;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 8;
+ ipu_channel_params.ofs2 = 16;
+ ipu_channel_params.ofs3 = 24;
+ break;
+ case RGBA8888:
+ ipu_channel_params.wid0 = 8 - 1; //bits
+ ipu_channel_params.wid1 = 8 - 1; //bits;
+ ipu_channel_params.wid2 = 8 - 1; //bits;
+ ipu_channel_params.wid3 = 8 - 1; //bits;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 8;
+ ipu_channel_params.ofs2 = 16;
+ ipu_channel_params.ofs3 = 24;
+ break;
+ default:
+ diag_printf("data format not supported!\n");
+ }
+ ipu_channel_params.bm = 0;
+ ipu_channel_params.hf = 0;
+ ipu_channel_params.vf = 1;
+ ipu_channel_params.id = 0;
+ ipu_idmac_interleaved_channel_config(ipu_channel_params);
+
+ ipu_idmac_channel_mode_sel(DISPLAY_CHANNEL, 0);
+ ipu_idmac_channel_enable(DISPLAY_CHANNEL, 1);
+}
+
+void fastlogo_dmfc(void)
+{
+ ipu_dmfc_fifo_allocate(DISPLAY_CHANNEL, 1, 0, 4);
+}
+
+void fastlogo_dc(void)
+{
+ //***************************************************/
+ //DI CONFIGURATION
+ //****************************************************/
+ //MICROCODE
+ dc_microcode_t microcode;
+ microcode.addr = 4;
+ microcode.stop = 1;
+ microcode.opcode = "WROD";
+ microcode.lf = 0;
+ microcode.af = 0;
+ microcode.operand = 0;
+ microcode.mapping = 2;
+ microcode.waveform = 1;
+ microcode.gluelogic = 0;
+ microcode.sync = 5;
+ ipu_dc_microcode_config(microcode);
+
+ ipu_dc_microcode_event(1, "NEW_DATA", 1, 4);
+
+ //WRITE_CHAN
+ ipu_dc_write_channel_config(DISPLAY_CHANNEL, 2, 0, 0);
+
+ //DISP_CONF
+ ipu_dc_display_config(2, 2 /*paralell */ , 0, display_buffer.width);
+
+ //DC_MAP
+ ipu_dc_map(1, RGB666);
+}
+
+void fastlogo_di(void)
+{
+ di_sync_wave_gen_t syncWaveformGen = { 0 };
+ int clkUp, clkDown;
+ int hSyncStartWidth = 80;
+ int hSyncWidth = 20;
+ int hSyncEndWidth = 41;
+ int delayH2V = 480;
+ int hDisp = 480;
+ int vSyncStartWidth = 20;
+ int vSyncWidth = 10;
+ int vSyncEndWidth = 5;;
+ int vDisp = 640;
+ int ipuClk = 133000000; // ipu clk is 133M
+ int typPixClk = 24000000; // typical value of pixel clock
+ int div = (int)((float)ipuClk / (float)typPixClk + 0.5); // get the nearest value of typical pixel clock
+ int pixClk = 133000000 / div;
+
+ //DI0_SCR, set the screen height
+ ipu_di_screen_set(0, vDisp + vSyncStartWidth + vSyncEndWidth - 1);
+
+ /* set DI_PIN15 to be waveform according to DI data wave set 3 */
+ ipu_di_pointer_config(0, 0, div - 1, div - 1, 0, 0, 0, 0, 0, 2, 0, 0);
+
+ /*set the up & down of data wave set 3. */
+ ipu_di_waveform_config(0, 0, 2, 0, div * 2); // one bit for fraction part
+
+ /* set clk for DI0, generate the base clock of DI0. */
+ clkUp = div - 2;
+ clkDown = clkUp * 2;
+ ipu_di_bsclk_gen(0, div << 4, clkUp, clkDown);
+
+ /*
+ DI0 configuration:
+ hsync - DI0 pin 3
+ vsync - DI0 pin 2
+ data_en - DI0 pin 15
+ clk - DI0 disp clk
+ COUNTER 2 for VSYNC
+ COUNTER 3 for HSYNC
+ */
+ /*internal HSYNC */
+ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = 0;
+ syncWaveformGen.offsetResolution = 0;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 1;
+ ipu_di_sync_config(0, DI_COUNTER_IHSYNC, syncWaveformGen);
+
+ /*OUTPUT HSYNC */
+ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = delayH2V;
+ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = div * hSyncWidth;
+ ipu_di_sync_config(0, DI_COUNTER_OHSYNC, syncWaveformGen);
+
+ /*Output Vsync */
+ syncWaveformGen.runValue = vDisp + vSyncStartWidth + vSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_IHSYNC + 1;
+ syncWaveformGen.offsetValue = 0;
+ syncWaveformGen.offsetResolution = 0;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 1;
+ syncWaveformGen.cntPolarityTrigSel = 2;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = vSyncWidth;
+ ipu_di_sync_config(0, DI_COUNTER_OVSYNC, syncWaveformGen);
+
+ /*Active Lines start points */
+ syncWaveformGen.runValue = 0;
+ syncWaveformGen.runResolution = DI_COUNTER_OHSYNC + 1;
+ syncWaveformGen.offsetValue = vSyncWidth;
+ syncWaveformGen.offsetResolution = DI_COUNTER_OHSYNC + 1;
+ syncWaveformGen.cntAutoReload = 0;
+ syncWaveformGen.stepRepeat = vDisp;
+ syncWaveformGen.cntClrSel = DI_COUNTER_OVSYNC + 1;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 0;
+ ipu_di_sync_config(0, DI_COUNTER_ALINE, syncWaveformGen);
+
+ /*Active clock start points */
+ syncWaveformGen.runValue = 0;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = hSyncWidth;
+ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.cntAutoReload = 0;
+ syncWaveformGen.stepRepeat = hDisp;
+ syncWaveformGen.cntClrSel = DI_COUNTER_ALINE + 1;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 0;
+ ipu_di_sync_config(0, DI_COUNTER_ACLOCK, syncWaveformGen);
+
+ ipu_di_general_set(0, 1, 2, 1, 0);
+
+}
+
#endif
RedBoot_config_option("Board specifics",
- brd_specs,
- ALWAYS_ENABLED,
- true,
- CONFIG_INT,
- 0
- );
+ brd_specs,
+ ALWAYS_ENABLED,
+ true,
+ CONFIG_INT,
+ 0
+ );
#endif //CYGSEM_REDBOOT_FLASH_CONFIG
-char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
-
-static void runImg(int argc, char *argv[]);
-
-RedBoot_cmd("run",
- "Run an image at a location with MMU off",
- "[<virtual addr>]",
- runImg
- );
-
-void launchRunImg(unsigned long addr)
-{
- asm volatile ("mov r12, r0;");
- HAL_CACHE_FLUSH_ALL();
- HAL_DISABLE_L2();
- HAL_MMU_OFF();
- asm volatile (
- "mov r0, #0;"
- "mov r1, r12;"
- "mov r11, #0;"
- "mov r12, #0;"
- "mrs r10, cpsr;"
- "bic r10, r10, #0xF0000000;"
- "msr cpsr_f, r10;"
- "mov pc, r1"
- );
-}
-
-extern unsigned long entry_address;
-
-static void runImg(int argc,char *argv[])
-{
- unsigned int virt_addr, phys_addr;
-
- // Default physical entry point for Symbian
- if (entry_address == 0xFFFFFFFF)
- virt_addr = 0x800000;
- else
- virt_addr = entry_address;
-
- if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
- OPTION_ARG_TYPE_NUM, "virtual address"))
- return;
-
- if (entry_address != 0xFFFFFFFF)
- diag_printf("load entry_address=0x%lx\n", entry_address);
- HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
-
- diag_printf("virt_addr=0x%x\n",virt_addr);
- diag_printf("phys_addr=0x%x\n",phys_addr);
-
- launchRunImg(phys_addr);
-}
+char HAL_PLATFORM_EXTRA[40] = "PASS x.x [x32 DDR]";
#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
RedBoot_cmd("romupdate",
- "Update Redboot with currently running image",
- "",
- romupdate
- );
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
extern int flash_erase(void *addr, int len, void **err_addr);
extern char *flash_errmsg(int err);
extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+extern cyg_uint32 emmc_set_boot_partition (cyg_uint32 *src_ptr, cyg_uint32 length);
+extern cyg_uint32 esd_set_boot_partition(cyg_uint32 *src_ptr, cyg_uint32 length);
+extern cyg_uint32 mmc_data_write(cyg_uint32 *src_ptr, cyg_uint32 length, cyg_uint32 offset);
+extern cyg_uint32 mmc_data_read(cyg_uint32 *dest_ptr, cyg_uint32 length, cyg_uint32 offset);
#ifdef CYGPKG_IO_FLASH
void romupdate(int argc, char *argv[])
{
- void *err_addr, *base_addr;
- int stat;
- unsigned int nfc_config3_reg, temp;
-
- if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
- diag_printf("Updating ROM in MMC/SD flash\n");
- /* eMMC 4.3 and eSD 2.1 supported only on TO 2.0 */
- if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
- if(!emmc_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
- /* eMMC 4.3 */
- diag_printf("Card supports MMC-4.3, programming for boot operation.\n");
- return;
- } else if(!esd_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
- /* eSD 2.1 */
- diag_printf("Card supports SD-2.1, programming for boot operation.\n");
- return;
- }
- }
- base_addr = (void*)0;
- /* Read the first 1K from the card */
- mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
- diag_printf("Programming Redboot to MMC/SD flash\n");
- mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
-
- return;
- } else if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) {
- diag_printf("Updating ROM in NAND flash\n");
- base_addr = (void*)0;
- nfc_config3_reg = readl(NFC_FLASH_CONFIG3_REG);
- temp = nfc_config3_reg & (~ 0x7003);
- writel(temp, NFC_FLASH_CONFIG3_REG);
- } else {
- diag_printf("romupdate not supported\n");
- diag_printf("Use \"factive [NAND|MMC]\" to select either NAND or MMC flash\n");
- }
-
- // Erase area to be programmed
- if ((stat = flash_erase((void *)base_addr,
- CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
- (void **)&err_addr)) != 0) {
- diag_printf("Can't erase region at %p: %s\n",
- err_addr, flash_errmsg(stat));
- return;
- }
- // Now program it
- if ((stat = flash_program((void *)base_addr, (void *)ram_end,
- CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
- (void **)&err_addr)) != 0) {
- diag_printf("Can't program region at %p: %s\n",
- err_addr, flash_errmsg(stat));
- }
- if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND())
- writel(nfc_config3_reg, NFC_FLASH_CONFIG3_REG);
+ void *err_addr, *base_addr;
+ int stat;
+ unsigned int nfc_config3_reg = 0, temp;
+
+ if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
+ diag_printf("Updating ROM in MMC/SD flash\n");
+ /* eMMC 4.3 and eSD 2.1 supported only on TO 2.0 and higher */
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2) {
+ if(!emmc_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eMMC 4.3 */
+ diag_printf("Card supports MMC-4.3, programming for boot operation.\n");
+ return;
+ } else if(!esd_set_boot_partition((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eSD 2.1 */
+ diag_printf("Card supports SD-2.1, programming for boot operation.\n");
+ return;
+ }
+ }
+ base_addr = NULL;
+ /* Read the first 1K from the card */
+ mmc_data_read((cyg_uint32*)ram_end, 0x400, (cyg_uint32)base_addr);
+ diag_printf("Programming Redboot to MMC/SD flash\n");
+ mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+
+ return;
+ } else if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND()) {
+ diag_printf("Updating ROM in NAND flash\n");
+ base_addr = NULL;
+ nfc_config3_reg = readl(NFC_FLASH_CONFIG3_REG);
+ temp = nfc_config3_reg & ~0x7003;
+ writel(temp, NFC_FLASH_CONFIG3_REG);
+ } else if (IS_BOOTING_FROM_SPI_NOR() || IS_FIS_FROM_SPI_NOR()) {
+ diag_printf("Updating ROM in SPI-NOR flash\n");
+ base_addr = NULL;
+ } else {
+ diag_printf("romupdate not supported\n");
+ diag_printf("Use \"factive [NAND|MMC|SPI]\" to select either NAND, MMC or SPI flash\n");
+ }
+
+ // Erase area to be programmed
+ if ((stat = flash_erase(base_addr,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+ (void **)&err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+ if (IS_FIS_FROM_NAND() || IS_BOOTING_FROM_NAND())
+ writel(nfc_config3_reg, NFC_FLASH_CONFIG3_REG);
}
RedBoot_cmd("factive",
- "Enable one flash media for Redboot",
- "[NAND | MMC]",
- factive
- );
+ "Enable one flash media for Redboot",
+ "[NAND | MMC | SPI]",
+ factive
+ );
typedef void reset_func_t(void);
extern reset_func_t reset_vector;
+static void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r1, r0;");
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
void factive(int argc, char *argv[])
{
- unsigned long phys_addr;
- unsigned int *fis_addr = IRAM_BASE_ADDR;
-
- if (argc != 2) {
- diag_printf("Invalid factive cmd\n");
- return;
- }
-
- if (strcasecmp(argv[1], "NOR") == 0) {
- diag_printf("Not supported\n");
- return;
- } else if (strcasecmp(argv[1], "NAND") == 0) {
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ if (argc != 2) {
+ diag_printf("Invalid factive cmd\n");
+ return;
+ }
+
+ if (strcasecmp(argv[1], "NOR") == 0) {
+ diag_printf("Not supported\n");
+ return;
+ } else if (strcasecmp(argv[1], "NAND") == 0) {
#ifndef MXCFLASH_SELECT_NAND
- diag_printf("Not supported\n");
- return;
+ diag_printf("Not supported\n");
+ return;
#endif
- *fis_addr = FROM_NAND_FLASH;
- } else if (strcasecmp(argv[1], "MMC") == 0) {
+ *fis_addr = FROM_NAND_FLASH;
+ } else if (strcasecmp(argv[1], "MMC") == 0) {
#ifndef MXCFLASH_SELECT_MMC
- diag_printf("Not supported\n");
- return;
+ diag_printf("Not supported\n");
+ return;
+#else
+ *fis_addr = FROM_MMC_FLASH;
+#endif
+ } else if (strcasecmp(argv[1], "SPI") == 0) {
+#ifndef IMXFLASH_SELECT_SPI_NOR
+ diag_printf("Not supported\n");
+ return;
#else
- *fis_addr = FROM_MMC_FLASH;
+ *fis_addr = FROM_SPI_NOR_FLASH;
#endif
- } else {
- diag_printf("Invalid command: %s\n", argv[1]);
- return;
- }
+ } else {
+ diag_printf("Invalid command: %s\n", argv[1]);
+ return;
+ }
- //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
- launchRunImg(reset_vector);
+ //HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+ launchRunImg((unsigned long)reset_vector);
}
#endif //CYGPKG_IO_FLASH
#endif /* CYG_HAL_STARTUP_ROMRAM */
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MX51 Babbage\""
- puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2000"
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2125"
puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
}
display "Global compiler flags"
flavor data
no_define
- default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+ default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
.macro flash_header
b reset_vector
.org 0x400
-app_code_jump_v: .long reset_vector
-app_code_barker: .long 0xB1
-app_code_csf: .long 0
-dcd_ptr_ptr: .long dcd_ptr
-super_root_key: .long 0
-dcd_ptr: .long dcd_data
-app_dest_ptr: .long 0xAFF00000
+app_code_jump_v: .long reset_vector
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+dcd_ptr_ptr: .long dcd_ptr
+super_root_key: .long 0
+dcd_ptr: .long dcd_data
+app_dest_ptr: .long 0xAFF00000
-dcd_data: .long 0xB17219E9 // Fixed. can't change.
-dcd_len: .long (20*12)
+dcd_data: .long 0xB17219E9 // Fixed. can't change.
+dcd_len: .long (56*12)
//DCD
- // ldr r0, ESDCTL_BASE_W
- // /* Set CSD0 */
- // ldr r1, =0x80000000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
- // /* Precharge command */
- // ldr r1, SDRAM_0x04008008
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
- // /* 2 refresh commands */
- // ldr r1, SDRAM_0x00008010
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
- // /* LMR with CAS=3 and BL=3 */
- // ldr r1, SDRAM_0x00338018
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
- // /* 14 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
- // ldr r1, SDRAM_0xB2220000
- // str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000)
- // /* Timing parameters */
- // ldr r1, SDRAM_0xB02567A9
- // str r1, [r0, #ESDCTL_ESDCFG0]
-DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB08567A9)
- // /* MDDR enable, RLAT=2 */
- // ldr r1, SDRAM_0x000A0104
- // str r1, [r0, #ESDCTL_ESDMISC]
-DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
- // /* Normal mode */
- // ldr r1, =0x00000000
- // str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
-
-//////////////////// csd1 //////////////////
-DCDGEN(10, 4, 0x83fd9008, 0x80000000)
- //Precharge command
- //setmem /32 0x83fd9014 = 0x0400800C // [MK]
-DCDGEN(11, 4, 0x83fd9014, 0x0400800C)
- //2 Refresh commands
- //setmem /32 0x83fd9014 = 0x00008014 // [MK]
-DCDGEN(12, 4, 0x83fd9014, 0x00008014)
- //setmem /32 0x83fd9014 = 0x00008014 // [MK]
-DCDGEN(13, 4, 0x83fd9014, 0x00008014)
- //LMR with CAS=3 and BL=3
- //setmem /32 0x83fd9014 = 0x0033801C // [MK]
-DCDGEN(14, 4, 0x83fd9014, 0x0033801C)
- //14 ROW, 10 COL, 32Bit, SREF=8 Micron Model
- //setmem /32 0x83fd9008 = 0xC3220000
-DCDGEN(15, 4, 0x83fd9008, 0xC3220000)
- //Timing parameters
- //setmem /32 0x83fd900C = 0xB08567A9
-DCDGEN(16, 4, 0x83fd900C, 0xB08567A9)
- //MDDR enable, RLAT=2
- //setmem /32 0x83fd9010 = 0x000a0104
-DCDGEN(17, 4, 0x83fd9010, 0x000a0104)
- //Normal mode
- //setmem /32 0x83fd9014 = 0x00000004 // [DB]
-DCDGEN(18, 4, 0x83fd9014, 0x00000004)
- //setmem /32 0x90000000 = 0x00000000
-DCDGEN(19, 4, 0x90000000, 0x00000000)
- //setmem /32 0xA0000000 = 0x00000000
-DCDGEN(20, 4, 0xA0000000, 0x00000000)
+//DDR2 IOMUX configuration
+DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+//Set drive strength to HIGH
+DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x4)
+DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x4)
+DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x4)
+DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x4)
+//13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
+//CAS=3, BL=4
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x3F3584AB)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x3F3584AB)
+// Init DRAM on CS0
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+
+// Init DRAM on CS1
+DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+
+DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
image_len: .long 256*1024
FSL_BOARD_SETUP_START:
// mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
// mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+
+ ldr r0, GPIO1_BASE_ADDR_W
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x4]
+
#ifdef ENABLE_IMPRECISE_ABORT
- mrs r1, spsr // save old spsr
- mrs r0, cpsr // read out the cpsr
- bic r0, r0, #0x100 // clear the A bit
- msr spsr, r0 // update spsr
- add lr, pc, #0x8 // update lr
- movs pc, lr // update cpsr
- nop
- nop
- nop
- nop
- msr spsr, r1 // restore old spsr
+ mrs r1, spsr // save old spsr
+ mrs r0, cpsr // read out the cpsr
+ bic r0, r0, #0x100 // clear the A bit
+ msr spsr, r0 // update spsr
+ add lr, pc, #0x8 // update lr
+ movs pc, lr // update cpsr
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 // restore old spsr
#endif
// explicitly disable L2 cache
mrc 15, 0, r0, c1, c0, 1
// reconfigure L2 cache aux control reg
mov r0, #0xC0 // tag RAM
add r0, r0, #0x4 // data RAM
- orr r0, r0, #(1 << 25) // disable write combine
orr r0, r0, #(1 << 24) // disable write allocate delay
orr r0, r0, #(1 << 23) // disable write allocate combine
orr r0, r0, #(1 << 22) // disable write allocate
+ ldr r1, =ROM_BASE_ADDRESS
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs
+
mcr 15, 1, r0, c9, c0, 2
-init_spba_start:
- init_spba
init_aips_start:
init_aips
-init_max_start:
- init_max
init_m4if_start:
init_m4if
-init_iomux_start:
-// init_iomux
-
- // disable wdog
- ldr r0, =0x30
- ldr r1, WDOG1_BASE_W
- strh r0, [r1]
-
-init_clock_start:
- init_clock
-
#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
- /* Copy image from flash to SDRAM first */
+ /* Check if need to copy image to Redboot ROM space */
ldr r0, =0xFFFFF000
and r0, r0, pc
ldr r1, MXC_REDBOOT_ROM_START
#endif /* CYG_HAL_STARTUP_ROMRAM */
HWInitialise_skip_SDRAM_copy:
+ /* Skip clock setup if already booted up */
+ ldr r0, =IRAM_BASE_ADDR
+ ldr r0, [r0]
+ ldr r1, =FROM_SPI_NOR_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+ ldr r1, =FROM_MMC_FLASH
+ cmp r0, r1
+ beq Normal_Boot_Continue
+
+init_clock_start:
+ init_clock
-init_cs1_start:
-// init_cs1 -- moved to plf_hardware_init()
+Normal_Boot_Continue:
/*
* Note:
// Create MMU tables
bl hal_mmu_init
+ /* Workaround for arm errata #709718 */
+ //Setup PRRR so device is always mapped to non-shared
+ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
+ bic r1, #(3 << 16)
+ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
+
// Enable MMU
ldr r2, =10f
- ldr r0, =ROM_BASE_ADDRESS
- ldr r3, [r0, #ROM_SI_REV_OFFSET]
- cmp r3, #0x1
- bne skip_L1_workaround
- // Workaround for L1 cache issue
- mrc MMU_CP, 0, r1, c10, c2, 1 // Read normal memory remap register
- bic r1, r1, #(3 << 14) // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
- bic r1, r1, #(3 << 6) // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
- bic r1, r1, #(3 << 4) // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
- mcr MMU_CP, 0, r1, c10, c2, 1 // Write normal memory remap register
-skip_L1_workaround:
- mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
+ mrc MMU_CP, 0, r1, MMU_Control, c0
orr r1, r1, #7 // enable MMU bit
- orr r1, r1, #0x800 // enable z bit
- orrne r1, r1, #(1 << 28) // Enable TEX remap, workaround for L1 cache issue
+ orr r1, r1, #0x800 // enable z bit
+ orr r1, r1, #(1 << 28) // Enable TEX remap
mcr MMU_CP, 0, r1, MMU_Control, c0
+
+ /* Workaround for arm errata #621766 */
+ mrc MMU_CP, 0, r1, MMU_Control, c0, 1
+ orr r1, r1, #(1 << 5) // enable L1NEON bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0, 1
+
mov pc,r2 /* Change address spaces */
nop
nop
#define PLATFORM_SETUP1
#endif
- /* Do nothing */
- .macro init_spba
- .endm /* init_spba */
-
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
.macro init_aips
/*
.endm /* init_aips */
- /* MAX (Multi-Layer AHB Crossbar Switch) setup */
- .macro init_max
- .endm /* init_max */
-
.macro init_clock
ldr r0, CCM_BASE_ADDR_W
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Disable IPU and HSC dividers */
mov r1, #0x60000
str r1, [r0, #CLKCTL_CCDR]
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, CCM_VAL_0x19239145
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
setup_pll PLL1, 800
+ setup_pll PLL3, 665
/* Switch peripheral to PLL 3 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x0000D3C0
+ ldr r1, CCM_VAL_0x000010C0
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, CCM_VAL_0x033B9145
+ ldr r1, CCM_VAL_0x13239145
str r1, [r0, #CLKCTL_CBCDR]
setup_pll PLL2, 665
/* Switch peripheral to PLL 2 */
ldr r0, CCM_BASE_ADDR_W
- ldr r1, CCM_VAL_0x013B9145
+ ldr r1, CCM_VAL_0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, CCM_VAL_0x0000E3C0
+ ldr r1, CCM_VAL_0x000020C0
str r1, [r0, #CLKCTL_CBCMR]
setup_pll PLL3, 216
ldr r1, PLATFORM_CLOCK_DIV_W
str r1, [r0, #PLATFORM_ICGC]
- /* Switch ARM back to PLL 1. */
ldr r0, CCM_BASE_ADDR_W
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r1, =ROM_BASE_ADDRESS
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
- mov r1, #0
- str r1, [r0, #CLKCTL_CACRR]
-
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, CCM_VAL_0x0000E3C2
+ ldr r1, CCM_VAL_0x000020C2
str r1, [r0, #CLKCTL_CBCMR]
- // emi=ahb, all perclk dividers are 1 since using 24MHz
- // DDR divider=6 to have 665/6=110MHz
- ldr r1, CCM_VAL_0x013D9100
+ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+ ldr r1, CCM_VAL_0x59239100
str r1, [r0, #CLKCTL_CBCDR]
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, CCM_VAL_0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
/* Now restart PLL */
ldr r1, PLL_VAL_0x1232
str r1, [r0, #PLL_DP_CTL]
-wait_pll_lock\pll_nr:
+wait_pll_lock\pll_nr\mhz:
ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
- beq wait_pll_lock\pll_nr
+ beq wait_pll_lock\pll_nr\mhz
.endm
/* M4IF setup */
.macro init_m4if
- /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
- IPU accesses with ID=0x1 given highest priority (=0xA) */
ldr r1, M4IF_BASE_W
- ldr r0, M4IF_0x00000a01
- str r0, [r1, #M4IF_FIDBP]
-
- ldr r0, M4IF_0x00000404
+ ldr r0, M4IF_0x00000203
str r0, [r1, #M4IF_FBPM0]
- .endm /* init_m4if */
- .macro init_iomux
- // do nothing
- .endm /* init_iomux */
+ ldr r0, =0x0
+ str r0, [r1, #M4IF_FBPM1]
+
+ ldr r0, M4IF_0x00120125
+ str r0, [r1, #M4IF_FPWC]
+
+ ldr r0, M4IF_0x001901A3
+ str r0, [r1, #M4IF_MIF4]
+ .endm /* init_m4if */
#define PLATFORM_VECTORS _platform_vectors
.macro _platform_vectors
_board_CFG: .long 0 // Board Configuration (read at RESET)
.endm
-WDOG1_BASE_W: .word WDOG1_BASE_ADDR
-IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
AIPS1_PARAM_W: .word 0x77777777
-MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
-MAX_PARAM1: .word 0x00302154
-ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
M4IF_BASE_W: .word M4IF_BASE_ADDR
-M4IF_0x00000a01: .word 0x00000a01
-M4IF_0x00000404: .word 0x00000404
-NFC_BASE_W: .word NFC_BASE_ADDR_AXI
-NFC_IP_BASE_W: .word NFC_IP_BASE
-IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
+M4IF_0x00120125: .word 0x00120125
+M4IF_0x001901A3: .word 0x001901A3
+M4IF_0x00000203: .word 0x00000203
MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
-CONST_0x0FFF: .word 0x0FFF
+GPIO1_BASE_ADDR_W: .word GPIO1_BASE_ADDR
CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-CCM_VAL_0x0000E3C2: .word 0x0000E3C2
-CCM_VAL_0x013D9100: .word 0x013D9100
+CCM_VAL_0x000020C2: .word 0x000020C2
+CCM_VAL_0x59239100: .word 0x59239100
+CCM_VAL_0x19239145: .word 0x19239145
CCM_VAL_0xA5A2A020: .word 0xA5A2A020
CCM_VAL_0x00C30321: .word 0x00C30321
-CCM_VAL_0x0000D3C0: .word 0x0000D3C0
-CCM_VAL_0x033B9145: .word 0x033B9145
-CCM_VAL_0x013B9145: .word 0x013B9145
-CCM_VAL_0x0000E3C0: .word 0x0000E3C0
+CCM_VAL_0x000010C0: .word 0x000010C0
+CCM_VAL_0x13239145: .word 0x13239145
+CCM_VAL_0x000020C0: .word 0x000020C0
PLL_VAL_0x222: .word 0x222
PLL_VAL_0x232: .word 0x232
BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_700: .word DP_OP_700
-W_DP_MFD_700: .word DP_MFD_700
-W_DP_MFN_700: .word DP_MFN_700
-W_DP_OP_400: .word DP_OP_400
-W_DP_MFD_400: .word DP_MFD_400
-W_DP_MFN_400: .word DP_MFN_400
-W_DP_OP_532: .word DP_OP_532
-W_DP_MFD_532: .word DP_MFD_532
-W_DP_MFN_532: .word DP_MFN_532
W_DP_OP_665: .word DP_OP_665
W_DP_MFD_665: .word DP_MFD_665
W_DP_MFN_665: .word DP_MFN_665
W_DP_MFD_216: .word DP_MFD_216
W_DP_MFN_216: .word DP_MFN_216
PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W: .word 0x00000725
-_nand_pg_sz: .word 0
+PLATFORM_CLOCK_DIV_W: .word 0x00000124
/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
- if ( _v_ < SDRAM_SIZE ) /* SDRAM */ \
+ if ( _v_ < SDRAM_SIZE - 0x100000) /* SDRAM */ \
_v_ += SDRAM_BASE_ADDR; \
else /* Rest of it */ \
/* no change */ ; \
package -hardware CYGPKG_IO_FLASH current ;
package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
package -hardware CYGPKG_DEVS_IMX_SPI current ;
+ package -hardware CYGPKG_IMX_CMDS current ;
package -template CYGPKG_HAL current ;
package -template CYGPKG_INFRA current ;
package -template CYGPKG_REDBOOT current ;
};
cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200904"
+ user_value 1 "FSL 200938"
};
/*FEC_MDIO*/
writel(0x3, IOMUXC_BASE_ADDR + 0x0D4);
- writel(0x1FD, IOMUXC_BASE_ADDR + 0x0470);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B0);
+ writel(0x1FD, IOMUXC_BASE_ADDR + 0x0468);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0954);
- /*FEC_RDATA1*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0D8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0474);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B8);
-
- /*FEC_RDATA2*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09BC);
+ /*FEC_MDC*/
+ writel(0x2, IOMUXC_BASE_ADDR + 0x13C);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0524);
- /*FEC_RDATA3*/
+ /* FEC RDATA[3] */
writel(0x3, IOMUXC_BASE_ADDR + 0x0EC);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C0);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0480);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0964);
- /*FEC_RX_ERR*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0F0);
- writel(0x180, IOMUXC_BASE_ADDR + 0x048C);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09CC);
-
- /*FEC_CRS*/
- writel(0x3, IOMUXC_BASE_ADDR + 0x0F4);
- writel(0x180, IOMUXC_BASE_ADDR + 0x0490);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09AC);
-
- /*FEC_COL*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05CC);
- writel(0x0, IOMUXC_BASE_ADDR + 0x9A8);
-
- /*FEC_RX_CLK*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05D0);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C4);
-
- /*FEC_RX_DV*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x012C);
- writel(0x180, IOMUXC_BASE_ADDR + 0x05D4);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09C8);
+ /* FEC RDATA[2] */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0E8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x047C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0960);
- /*FEC_RDATA0*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0134);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x05DC);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09B4);
+ /* FEC RDATA[1] */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0d8);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x046C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x095C);
- /*FEC_TDATA0*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0138);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x5E0);
+ /* FEC RDATA[0] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x016C);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0554);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0958);
- /*FEC_TX_ERR*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0144);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05EC);
+ /* FEC TDATA[3] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x148);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0530);
- /*FEC_MDC*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0148);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F0);
+ /* FEC TDATA[2] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x144);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x052C);
- /*FEC_TDATA1*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x014C);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F4);
+ /* FEC TDATA[1] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x140);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0528);
- /*FEC_TDATA2*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0150);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05F8);
+ /* FEC TDATA[0] */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0170);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0558);
- /*FEC_TDATA3*/
- writel(0x2, IOMUXC_BASE_ADDR + 0x0154);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x05FC);
+ /* FEC TX_EN */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x014C);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0534);
- /*FEC_TX_EN*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x0158);
- writel(0x2004, IOMUXC_BASE_ADDR + 0x0600);
+ /* FEC TX_ER */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x0138);
+ writel(0x2004, IOMUXC_BASE_ADDR + 0x0520);
- /*FEC_TX_CLK*/
- writel(0x1, IOMUXC_BASE_ADDR + 0x015C);
- writel(0x2180, IOMUXC_BASE_ADDR + 0x0604);
- writel(0x0, IOMUXC_BASE_ADDR + 0x09D0);
+ /* FEC TX_CLK */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0150);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0538);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0974);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg &= ~0x4000; // Lower reset line
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ /* FEC COL */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0124);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0500);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x094c);
- reg = readl(GPIO2_BASE_ADDR + 0x4);
- reg |= 0x4000; // configure GPIO lines as output
- writel(reg, GPIO2_BASE_ADDR + 0x4);
+ /* FEC RX_CLK */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0128);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x0504);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0968);
- /* Reset the ethernet controller over GPIO */
- writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
+ /* FEC CRS */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0f4);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0488);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0950);
- hal_delay_us(200);
+ /* FEC RX_ER */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x0f0);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x0484);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x0970);
- reg = readl(GPIO2_BASE_ADDR + 0x0);
- reg |= 0x4000;
- writel(reg, GPIO2_BASE_ADDR + 0x0);
+ /* FEC RX_DV */
+ writel(0x2, IOMUXC_BASE_ADDR + 0x164);
+ writel(0x2180, IOMUXC_BASE_ADDR + 0x054C);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x096C);
}
#include <cyg/io/imx_spi.h>
freq : 25000000,
ss_pol : IMX_SPI_ACTIVE_HIGH,
ss : 0, // slave select 0
- fifo_sz : 64 * 4,
+ fifo_sz : 32,
reg : &spi_pmic_reg,
};
freq : 25000000,
ss_pol : IMX_SPI_ACTIVE_LOW,
ss : 1, // slave select 1
- fifo_sz : 64 * 4,
+ fifo_sz : 32,
us_delay: 0,
reg : &spi_nor_reg,
};
//
// Platform specific initialization
//
+static void babbage_power_init(void);
void plf_hardware_init(void)
{
unsigned int reg;
- /* Disable IPU and HSC dividers */
- writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
- /* Change the DDR divider to run at 166MHz on CPU 2 */
- reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- reg = (reg & (~0x70000)) | 0x40000;
- writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
- /* make sure divider effective */
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+
+ spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+ spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ spi_pmic_init(&imx_spi_pmic);
+
+ babbage_power_init();
// UART1
//RXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x234);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
//TXD
- writel(0x0, IOMUXC_BASE_ADDR + 0x238);
- writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
+ writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
//RTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
//CTS
- writel(0x0, IOMUXC_BASE_ADDR + 0x240);
- writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
-
+ writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+ writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
// enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
- writel(0x00000004, 0x73fa83F4);
- writel(0x00000004, 0x73fa83F0);
+ writel(0x00000004, 0x73fa83E8);
+ writel(0x00000004, 0x73fa83Ec);
+
// enable ARM clock div by 8
writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
- spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
- spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ /* Configure UART3_RXD pin for GPIO */
+ writel(0x3, IOMUXC_BASE_ADDR + 0x240);
+ reg = readl(GPIO1_BASE_ADDR + 0x4);
+ reg &= ~0x400000; // configure GPIO lines as input
+ writel(reg, GPIO1_BASE_ADDR + 0x4);
- spi_pmic_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
- spi_pmic_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+ if ((readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) {
+ /* Babbage 2.5 */
+ system_rev |= 0x1 << BOARD_VER_OFFSET;
+ HAL_PLATFORM_EXTRA[32] = '5';
+ }
}
void mxc_mmc_init(unsigned int base_address)
{
switch(base_address) {
case MMC_SDHC1_BASE_ADDR:
- //diag_printf("Configure IOMUX of ESDHC1 on i.MX51\n");
/* SD1 CMD, SION bit */
- writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
-
- /* SD1 CD, as gpio1_0 */
- writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
+ writel(0x10, IOMUXC_BASE_ADDR + 0x394);
/* Configure SW PAD */
/* SD1 CMD */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x79C);
/* SD1 CLK */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0);
/* SD1 DAT0 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4);
/* SD1 DAT1 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8);
/* SD1 DAT2 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC);
/* SD1 DAT3 */
- writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
- /* SD1 CD as gpio1_0 */
- writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
+ writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0);
break;
+ case MMC_SDHC2_BASE_ADDR:
+ /* SD2 CMD, SION bit */
+ writel(0x10, IOMUXC_BASE_ADDR + 0x3b4);
+ /* Configure SW PAD */
+ /* SD2 CMD */
+ writel(0x20f4, IOMUXC_BASE_ADDR + 0x7bc);
+ /* SD2 CLK */
+ writel(0x20d4, IOMUXC_BASE_ADDR + 0x7c0);
+ /* SD2 DAT0 */
+ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7c4);
+ /* SD2 DAT1 */
+ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7c8);
+ /* SD2 DAT2 */
+ writel(0x21d4, IOMUXC_BASE_ADDR + 0x7cc);
+ /* SD2 DAT3 */
+ writel(0x20e4, IOMUXC_BASE_ADDR + 0x7d0);
default:
break;
}
static void babbage_power_init(void)
{
unsigned int val;
+ volatile unsigned int reg;
- /* power up the system first */
- pmic_reg(34, 0x00200000, 1);
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg(34, 0, 0);
+ val &= ~0x10000;
+ pmic_reg(34, val, 1);
- if (pll_clock(PLL1) > 800000000) {
- /* Set core voltage to 1.175V */
+ /* Write needed to update Charger 0 */
+ pmic_reg(48, 0x0023807F, 1);
+
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
+ /* Set core voltage to 1.1V */
val = pmic_reg(24, 0, 0);
- val = val & (~0x1F) | 0x17;
+ val = val & (~0x1F) | 0x14;
pmic_reg(24, val, 1);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg(25, 0, 0);
+ val = val & (~0x1F) | 0x1A;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg(26, 0, 0);
+ val = val & (~0x1F) | 0x1A;
+ pmic_reg(26, val, 1);
+ hal_delay_us(50);
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+ } else {
+ /* TO 3.0 */
+ /* Setup VCC (SW2) to 1.225 */
+ val = pmic_reg(25, 0, 0);
+ val = val & (~0x1F) | 0x19;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.2 */
+ val = pmic_reg(26, 0, 0);
+ val = val & (~0x1F) | 0x18;
+ pmic_reg(26, val, 1);
+ }
+
+ if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) {
+ /* Set switchers in PWM mode for Atlas 2.0 and lower */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg(28, 0, 0);
+ val = val & (~0x3C0F) | 0x1405;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val = val & (~0xF0F) | 0x505;
+ pmic_reg(29, val, 1);
+ } else {
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+ /* Setup the switcher mode for SW1 & SW2*/
+ val = pmic_reg(28, 0, 0);
+ val = val & (~0x3C0F) | 0x2008;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val = val & (~0xF0F) | 0x808;
+ pmic_reg(29, val, 1);
}
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
val |= 0x10020;
pmic_reg(30, val, 1);
- /* Set VVIDEO to 2.775V, VAUDIO to 2.775V, VSD to 3.15V */
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
val = pmic_reg(31, 0, 0);
val &= ~0x1FC;
val |= 0x1F4;
pmic_reg(33, val, 1);
hal_delay_us(200);
- /* Enable VGEN1 regulator */
- val = pmic_reg(32, val, 0);
- val |= 0x1;
- pmic_reg(32, val, 1);
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg &= ~0x4000; // Lower reset line
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x4);
+ reg |= 0x4000; // configure GPIO lines as output
+ writel(reg, GPIO2_BASE_ADDR + 0x4);
+
+ /* Reset the ethernet controller over GPIO */
+ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = 0x49249;
pmic_reg(33, val, 1);
- hal_delay_us(200);
+ hal_delay_us(500);
+
+ reg = readl(GPIO2_BASE_ADDR + 0x0);
+ reg |= 0x4000;
+ writel(reg, GPIO2_BASE_ADDR + 0x0);
/* Setup the FEC after enabling the regulators */
mxc_fec_setup();
}
-RedBoot_init(babbage_power_init, RedBoot_INIT_PRIO(900));
-
void io_cfg_spi(struct imx_spi_dev *dev)
{
switch (dev->base) {
case CSPI1_BASE_ADDR:
// 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1
- writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6CC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x210);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x600);
// 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x220);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6D0);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x214);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x604);
if (dev->ss == 0) {
// de-select SS1 of instance: ecspi1.
- writel(0x3, IOMUXC_BASE_ADDR + 0x228);
- writel(0x85, IOMUXC_BASE_ADDR + 0x6D8);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x60C);
// 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x224);
- writel(0x185, IOMUXC_BASE_ADDR + 0x6D4);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x218);
+ writel(0x185, IOMUXC_BASE_ADDR + 0x608);
} else if (dev->ss == 1) {
// de-select SS0 of instance: ecspi1.
- writel(0x3, IOMUXC_BASE_ADDR + 0x224);
- writel(0x85, IOMUXC_BASE_ADDR + 0x6D4);
+ writel(0x3, IOMUXC_BASE_ADDR + 0x218);
+ writel(0x85, IOMUXC_BASE_ADDR + 0x608);
// 000: Select mux mode: ALT0 mux port: SS1 of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x228);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6D8);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x21C);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x60C);
}
// 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x22C);
- writel(0x180, IOMUXC_BASE_ADDR + 0x6DC);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x220);
+ writel(0x180, IOMUXC_BASE_ADDR + 0x610);
// 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
- writel(0x0, IOMUXC_BASE_ADDR + 0x230);
- writel(0x105, IOMUXC_BASE_ADDR + 0x6E0);
+ writel(0x0, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x105, IOMUXC_BASE_ADDR + 0x614);
break;
case CSPI2_BASE_ADDR:
default:
);
#endif //CYGSEM_REDBOOT_FLASH_CONFIG
-char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]";
-
-static void runImg(int argc, char *argv[]);
-
-RedBoot_cmd("run",
- "Run an image at a location with MMU off",
- "[<virtual addr>]",
- runImg
- );
-
-void launchRunImg(unsigned long addr)
-{
- asm volatile ("mov r12, r0;");
- HAL_CACHE_FLUSH_ALL();
- HAL_DISABLE_L2();
- HAL_MMU_OFF();
- asm volatile (
- "mov r0, #0;"
- "mov r1, r12;"
- "mov r11, #0;"
- "mov r12, #0;"
- "mrs r10, cpsr;"
- "bic r10, r10, #0xF0000000;"
- "msr cpsr_f, r10;"
- "mov pc, r1"
- );
-}
-
-extern unsigned long entry_address;
-
-static void runImg(int argc,char *argv[])
-{
- unsigned int virt_addr, phys_addr;
-
- // Default physical entry point for Symbian
- if (entry_address == 0xFFFFFFFF)
- virt_addr = 0x800000;
- else
- virt_addr = entry_address;
-
- if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
- OPTION_ARG_TYPE_NUM, "virtual address"))
- return;
-
- if (entry_address != 0xFFFFFFFF)
- diag_printf("load entry_address=0x%lx\n", entry_address);
- HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
-
- diag_printf("virt_addr=0x%x\n",virt_addr);
- diag_printf("phys_addr=0x%x\n",phys_addr);
-
- launchRunImg(phys_addr);
-}
+char HAL_PLATFORM_EXTRA[40] = "PASS x.x [x32 DDR]. Board Rev 2.0";
#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
extern cyg_uint32 mmc_data_read (cyg_uint32 *,cyg_uint32 ,cyg_uint32);
extern int spi_nor_erase_block(void* block_addr, unsigned int block_size);
extern int spi_nor_program_buf(void *addr, void *data, int len);
+extern void __attribute__((__noinline__)) launchRunImg(unsigned long addr);
#ifdef CYGPKG_IO_FLASH
void romupdate(int argc, char *argv[])
if (IS_FIS_FROM_MMC() || IS_BOOTING_FROM_MMC()) {
diag_printf("Updating ROM in MMC/SD flash\n");
+ /* eMMC 4.3 and eSD 2.1 supported on TO 2.0 and higher */
+ if(!emmc_set_boot_partition((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eMMC 4.3 */
+ diag_printf("Card supports MMC-4.3, programming for boot operation.\n");
+ return;
+ } else if(!esd_set_boot_partition((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000), CYGBLD_REDBOOT_MIN_IMAGE_SIZE)) {
+ /* eSD 2.1 */
+ diag_printf("Card supports SD-2.1, programming for boot operation.\n");
+ return;
+ }
+
base_addr = (void*)0;
/* Read the first 1K from the card */
mmc_data_read((cyg_uint32*)(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000),
void factive(int argc, char *argv[])
{
- unsigned long phys_addr;
unsigned int *fis_addr = IRAM_BASE_ADDR;
if (argc != 2) {
#define POST_SIZE 0x100000
#define POST_MAGIC_MARKER 0x43
-
void imx_launch_post(void)
{
mmc_data_read(0x100000, // ram location
0x40000, // length
0x100000); // from MMC/SD offset 0x100000
+ /* Need this to recognize the SPI-NOR part */
+ if (spi_norflash_hwr_init() != 0)
+ return;
+
spi_nor_erase_block(0, 0x10000);
spi_nor_erase_block(0x10000, 0x10000);
spi_nor_erase_block(0x20000, 0x10000);
spi_nor_erase_block(0x30000, 0x10000);
// save the redboot to SPI-NOR
- spi_nor_program_buf(0, 0x100000, 0x40000);
+ if (spi_nor_program_buf(0, 0x100000, 0x40000) != 0)
+ return;
diag_printf("Reading POST from MMC to SDRAM...\n");
mmc_data_read(SDRAM_BASE_ADDR + POST_SDRAM_START_OFFSET, // ram location
--- /dev/null
+# ====================================================================
+#
+# hal_arm_tx51.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_TX51KARO {
+ display "Ka-Ro TX51 module"
+ parent CYGPKG_HAL_ARM_MX51
+ requires CYGINT_ISO_CTYPE
+ hardware
+ include_dir cyg/hal
+ define_header hal_arm_tx51.h
+ description "
+ This HAL platform package provides generic
+ support for the Ka-Ro electronics TX51 module."
+
+ compile tx51_misc.c
+ implements CYGINT_HAL_DEBUG_GDB_STUBS
+ implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+ implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+ implements CYGHWR_HAL_ARM_SOC_UART1
+ implements CYGHWR_HAL_ARM_SOC_UART2
+ implements CYGHWR_HAL_ARM_SOC_UART3
+ implements CYGHWR_HAL_ARM_SOC_UART4
+
+ requires {CYGBLD_BUILD_REDBOOT == 1}
+
+ define_proc {
+ puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_soc.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_tx51.h>"
+ puts $::cdl_system_header "#define CYGBLD_HAL_PLF_DEFS_H <cyg/hal/karo_tx51.h>"
+ puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX51 based\""
+ puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Ka-Ro TX51 processor module\""
+ puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 2529"
+ puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK tx51_program_new_stack"
+ }
+
+ cdl_component CYG_HAL_STARTUP {
+ display "Startup type"
+ flavor data
+ default_value { "ROMRAM" }
+ legal_values { "ROMRAM" }
+ no_define
+ define -file system.h CYG_HAL_STARTUP
+ description "
+ The only startup type allowed is ROMRAM, since this will allow
+ the program to exist in ROM, but be copied to RAM during startup
+ which is required to boot from NAND flash."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+ display "Diagnostic serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the console port.
+ Note: this should match the value chosen for the GDB port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+ display "GDB serial port baud rate"
+ flavor data
+ legal_values 9600 19200 38400 57600 115200
+ default_value 115200
+ description "
+ This option selects the baud rate used for the GDB port.
+ Note: this should match the value chosen for the console port if the
+ console and GDB port are the same."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+ display "Number of communication channels on the TX51"
+ flavor data
+ calculated 3
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+ display "Debug serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value 0
+ description "
+ The TX51 provides access to three serial ports. This option
+ chooses which port will be used to connect to a host
+ running GDB."
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+ display "Default console channel."
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ calculated 0
+ }
+
+ cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+ display "Console serial port"
+ active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+ flavor data
+ legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+ default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+ description "
+ The TX51 provides access to three serial ports. This option
+ chooses which port will be used for console output."
+ }
+
+ cdl_component CYGBLD_GLOBAL_OPTIONS {
+ display "Global build options"
+ flavor none
+ no_define
+ description "
+ Global build options including control over
+ compiler flags, linker flags and choice of toolchain."
+
+
+ parent CYGPKG_NONE
+
+ cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+ display "Global command prefix"
+ flavor data
+ no_define
+ default_value { "arm-926ejs-linux-gnu" }
+ description "
+ This option specifies the command prefix used when
+ invoking the build tools."
+ }
+
+ cdl_option CYGBLD_GLOBAL_CFLAGS {
+ display "Global compiler flags"
+ flavor data
+ no_define
+ requires CYGBLD_INFRA_CFLAGS_WARNINGS_AS_ERRORS
+ default_value { "-march=armv5 -mabi=apcs-gnu -Wall -Wno-pointer-sign -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -O2 -ffunction-sections -fdata-sections -fno-exceptions -fvtable-gc -finit-priority -Werror -pipe" }
+ description "
+ This option controls the global compiler flags which are used to
+ compile all packages by default. Individual packages may define
+ options which override these global flags."
+ }
+
+ cdl_option CYGBLD_GLOBAL_LDFLAGS {
+ display "Global linker flags"
+ flavor data
+ no_define
+ default_value { "-Wl,--gc-sections -Wl,-static -O2 -nostdlib" }
+ description "
+ This option controls the global linker flags. Individual
+ packages may define options which override these global flags."
+ }
+ }
+
+ cdl_component CYGPKG_HAL_ARM_TX51_OPTIONS {
+ display "Ka-Ro electronics TX51 module build options"
+ flavor none
+ no_define
+ requires { CYGBLD_REDBOOT_FLASH_BOOT_OFFSET == 0 }
+ description "
+ Package specific build options including control over
+ compiler flags used only in building this package,
+ and details of which tests are built."
+
+ cdl_option CYGNUM_HAL_ARM_TX51_SDRAM_SIZE {
+ display "SDRAM size"
+ flavor data
+ legal_values { 0x08000000 0x04000000 }
+ default_value { 0x08000000 }
+# This is what I would like to do, but define_proc currently does not allow for
+# accessing variables
+# display "SDRAM size in MiB"
+# legal_values { 128 64 }
+# default_value { 128 }
+# define_proc {
+# puts $::cdl_header "#define CYGNUM_HAL_ARM_TX51_SDRAM_SIZE \
+# [format "0x%08x" [expr $CYGNUM_HAL_ARM_TX51_SDRAM_SIZE * 1048576]]"
+# }
+ description "
+ This option specifies the SDRAM size of the TX51 module."
+ }
+
+ cdl_option CYGOPT_HAL_ARM_TX51_DEBUG {
+ display "Enable low level debugging with LED"
+ flavor bool
+ default_value { false }
+ description "
+ This option enables low level debugging by blink codes
+ of the LED on STK5."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX51_CFLAGS_ADD {
+ display "Additional compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX51 HAL. These flags are used in addition
+ to the set of global flags."
+ }
+
+ cdl_option CYGPKG_HAL_ARM_TX51_CFLAGS_REMOVE {
+ display "Suppressed compiler flags"
+ flavor data
+ no_define
+ default_value { "" }
+ description "
+ This option modifies the set of compiler flags for
+ building the TX51 HAL. These flags are removed from
+ the set of global flags if present."
+ }
+
+ cdl_option CYGHWR_MX51_LCD_LOGO {
+ display "Show a splash screen from the FIS partition: 'logo'"
+ active_if { CYGPKG_DEVS_IMX_IPU }
+ default_value 0
+ description "
+ When this option is enabled, RedBoot will look for a flash partition
+ named 'logo' and display the contents of this partition as initial
+ screen on the LCD"
+ compile mx51_fastlogo.c
+ }
+ }
+
+ cdl_component CYGHWR_MEMORY_LAYOUT {
+ display "Memory layout"
+ flavor data
+ no_define
+ calculated { "arm_tx51_romram" }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+ display "Memory layout linker script fragment"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+ calculated { "<pkgconf/mlt_arm_tx51_romram.ldi>" }
+ }
+
+ cdl_option CYGHWR_MEMORY_LAYOUT_H {
+ display "Memory layout header file"
+ flavor data
+ no_define
+ define -file system.h CYGHWR_MEMORY_LAYOUT_H
+ calculated { "<pkgconf/mlt_arm_tx51_romram.h>" }
+ }
+ }
+
+ cdl_option CYGSEM_HAL_ROM_MONITOR {
+ display "Behave as a ROM monitor"
+ flavor bool
+ default_value 0
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+ description "
+ Enable this option if this program is to be used as a ROM monitor,
+ i.e. applications will be loaded into RAM on the TX51 module, and this
+ ROM monitor may process exceptions or interrupts generated from the
+ application. This enables features such as utilizing a separate
+ interrupt stack when exceptions are generated."
+ }
+
+ cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+ display "Work with a ROM monitor"
+ flavor booldata
+ legal_values { "Generic" "GDB_stubs" }
+ default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+ parent CYGPKG_HAL_ROM_MONITOR
+ requires { CYG_HAL_STARTUP == "RAM" }
+ description "
+ Support can be enabled for different varieties of ROM monitor.
+ This support changes various eCos semantics such as the encoding
+ of diagnostic output, or the overriding of hardware interrupt
+ vectors.
+ Firstly there is \"Generic\" support which prevents the HAL
+ from overriding the hardware vectors that it does not use, to
+ instead allow an installed ROM monitor to handle them. This is
+ the most basic support which is likely to be common to most
+ implementations of ROM monitor.
+ \"GDB_stubs\" provides support when GDB stubs are included in
+ the ROM monitor or boot ROM."
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+ display "Redboot HAL options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+ description "
+ This option lists the target's requirements for a valid Redboot
+ configuration."
+
+ compile -library=libextras.a redboot_cmds.c
+
+ cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+ display "Build Redboot ROM binary image"
+ active_if CYGBLD_BUILD_REDBOOT
+ default_value 1
+ no_define
+ description "This option enables the conversion of the Redboot ELF
+ image to a binary image suitable for ROM programming."
+
+ make -priority 325 {
+ <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+ $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+ $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+ $(OBJCOPY) -O binary $< $@
+ $(COMMAND_PREFIX)nm $< | awk 'NF == 3 {print}' | sort > $(<:.elf=.map)
+ }
+ }
+ }
+
+ cdl_component CYGPKG_REDBOOT_HAL_TX51_OPTIONS {
+ display "Redboot HAL variant options"
+ flavor none
+ no_define
+ parent CYGPKG_REDBOOT
+ active_if CYGPKG_REDBOOT
+
+ # RedBoot details
+ requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x90108000 }
+ define_proc {
+ puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+ }
+ }
+}
--- /dev/null
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+// hal_platform_setup.h
+//
+// Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#define REMOVE_THIS_CRAP
+//#define BORKED
+#define USE_DCD
+//#define USE_LED
+//#define MX51_3STACK
+
+#include <pkgconf/system.h> // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h> // MMU definitions
+#include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define TX51_NAND_PAGE_SIZE 2048
+#define TX51_NAND_BLKS_PER_PAGE 64
+
+#ifndef MX51_3STACK
+#define DEBUG_LED_BIT 10
+#define LED_GPIO_BASE GPIO4_BASE_ADDR
+#define LED_MUX_OFFSET 0x1d0
+#define LED_MUX_MODE 0x13
+#else
+#define DEBUG_LED_BIT 0
+#define LED_GPIO_BASE GPIO1_BASE_ADDR
+#define LED_MUX_OFFSET 0x3ac
+#define LED_MUX_MODE 0x11
+#endif
+
+#define LED_ON LED_CTRL #1
+#define LED_OFF LED_CTRL #0
+
+#ifndef CYGOPT_HAL_ARM_TX51_DEBUG
+ .macro LED_CTRL,val
+ .endm
+ .macro LED_BLINK,val
+ .endm
+ .macro DELAY,ms
+ .endm
+#else
+#define CYGHWR_LED_MACRO LED_BLINK #\x
+ .macro DELAY,ms
+ ldr r10, =\ms
+111:
+ subs r10, r10, #1
+ bmi 113f
+ ldr r9, =(3600 / 10)
+112:
+ subs r9, r9, #1
+ bne 112b
+ b 111b
+ .ltorg
+113:
+ .endm
+
+ .macro LED_CTRL,val
+ // switch user LED (GPIO4_10) on STK5
+ ldr r10, =LED_GPIO_BASE
+ // GPIO_DR
+ mov r9, \val
+ cmp r9, #0
+ movne r9, #(1 << DEBUG_LED_BIT) @ LED ON
+ moveq r9, #0 @ LED OFF
+ str r9, [r10, #GPIO_DR]
+ .endm
+
+ .macro LED_BLINK,val
+ mov r8, \val
+211:
+ subs r8, r8, #1
+ bmi 212f
+ LED_CTRL #1
+ DELAY 200
+ LED_CTRL #0
+ DELAY 300
+ b 211b
+212:
+ DELAY 1000
+ .endm
+#endif
+
+ .macro LED_INIT
+ // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
+ ldr r10, =LED_GPIO_BASE
+ // GPIO_GDIR
+ ldr r9, [r10, #GPIO_GDIR]
+ orr r9, r9, #(1 << DEBUG_LED_BIT)
+ str r9, [r10, #GPIO_GDIR]
+ // iomux
+ ldr r10, =IOMUXC_BASE_ADDR
+ mov r9, #LED_MUX_MODE
+ str r9, [r10, #LED_MUX_OFFSET]
+ // GPIO_DR
+ mov r9, #(1 << DEBUG_LED_BIT) @ LED ON
+ str r9, [r10, #GPIO_DR]
+ .endm
+
+#define DCDGEN(type, addr, data) .long type, addr, data
+
+#define PLATFORM_PREAMBLE flash_header
+
+// This macro represents the initial startup code for the platform
+ .macro _platform_setup1
+#ifndef BORKED
+KARO_TX51_SETUP_START:
+ mrs r0, CPSR
+ mov r0, #0x1f
+ orr r0, r0, #128
+ orr r0, r0, #64
+ msr CPSR_xc, r0
+
+ ldr r1, =ROM_BASE_ADDR
+ ldr r11, [r1, #ROM_SI_REV_OFFSET]
+
+ setup_sdram
+
+ ldr r0, =GPC_BASE_ADDR
+ cmp r11, #0x10 // r11 contains the silicon rev
+ ldrls r1, =0x1FC00000
+ ldrhi r1, =0x1A800000
+ str r1, [r0, #4]
+
+ // Explicitly disable L2 cache
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ // reconfigure L2 cache aux control reg
+ mov r0, #0xC0 // tag RAM
+ add r0, r0, #0x4 // data RAM
+ orr r0, r0, #(1 << 24) // disable write allocate delay
+ orr r0, r0, #(1 << 23) // disable write allocate combine
+ orr r0, r0, #(1 << 22) // disable write allocate
+
+ @ cc is still set from "cmp r11, #0x10" above
+ orrls r0, r0, #(1 << 25) @ disable write combine for TO 2 and lower revs
+
+ mcr 15, 1, r0, c9, c0, 2
+
+init_aips_start:
+ init_aips
+ LED_INIT
+init_m4if_start:
+ init_m4if
+
+#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+ LED_BLINK #1
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+init_clock_start:
+ init_clock
+
+Normal_Boot_Continue:
+/*
+ * Note:
+ * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
+ */
+STACK_Setup:
+ @ Set up a stack [for calling C code]
+ ldr r1, =__startup_stack
+ ldr r2, =RAM_BANK0_BASE
+ orr sp, r1, r2
+
+ @ Create MMU tables
+ bl hal_mmu_init
+ LED_BLINK #2
+
+ /* Workaround for arm erratum #709718 */
+ @ Setup PRRR so device is always mapped to non-shared
+ mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
+ bic r1, #(3 << 16)
+ mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
+
+ @ Enable MMU
+ ldr r2, =10f
+ mrc MMU_CP, 0, r1, MMU_Control, c0
+ orr r1, r1, #7 @ enable MMU bit
+ orr r1, r1, #0x800 @ enable z bit
+ orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
+ mcr MMU_CP, 0, r1, MMU_Control, c0
+
+ /* Workaround for arm errata #621766 */
+ mrc MMU_CP, 0, r1, MMU_Control, c0, 1
+ orr r1, r1, #(1 << 5) @ enable L1NEON bit
+ mcr MMU_CP, 0, r1, MMU_Control, c0, 1
+
+ mov pc, r2 @ Change address spaces
+ .align 5
+10:
+ LED_BLINK #3
+#endif // BORKED
+ .endm @ _platform_setup1
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ .macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_CTRL_BASE_ADDR
+ ldr r1, AIPS1_PARAM
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =AIPS2_CTRL_BASE_ADDR
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ .endm /* init_aips */
+
+ .macro WDOG_RESET
+ ldr r0, =WDOG_BASE_ADDR
+ mov r1, #0
+1:
+ strh r1, [r0]
+ b 1b
+ .endm
+
+ .macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, [r0, #CLKCTL_CCR]
+ tst r1, #(1 << 12)
+ bne osc_ok
+
+ orr r1, r1, #(1 << 12)
+ str r1, [r0, #CLKCTL_CCR]
+
+ ldr r1, [r0, #CLKCTL_CCSR]
+ bic r1, #(1 << 9) /* switch lp_apm to OSC */
+ str r1, [r0, #CLKCTL_CCSR]
+osc_ok:
+ /* Gate off clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, CCM_CBCDR_VAL1
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure divider effective */
+1:
+ ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ /* Switch ARM to step clock */
+ ldr r1, [r0, #CLKCTL_CCSR]
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1, 800
+ setup_pll PLL3, 665
+
+ /* Switch peripheral to PLL 3 */
+ ldr r1, CCM_CBCMR_VAL1
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ ldr r1, CCM_CBCDR_VAL2
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ setup_pll PLL2, 665
+
+ /* Switch peripheral to PLL 2 */
+ ldr r1, CCM_CBCDR_VAL1
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, CCM_CBCMR_VAL2
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ setup_pll PLL3, 216
+
+ /* Set the platform clock dividers */
+ ldr r2, =PLATFORM_BASE_ADDR
+ ldr r1, PLATFORM_CLOCK_DIV
+ str r1, [r2, #PLATFORM_ICGC]
+
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ cmp r11, #0x10
+ movls r1, #1
+ movhi r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+ ldr r1, CCM_CBCMR_VAL2
+ str r1, [r0, #CLKCTL_CBCMR]
+ @ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+ ldr r1, CCM_CBCDR_VAL3
+
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, CCM_VAL_0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, CCM_VAL_0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+1:
+ ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ @ for cko - for ARM div by 8
+ mov r1, #0x000A0000
+ orr r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+
+ ldr r1, [r0, #CLKCTL_CCR]
+ bic r1, #(1 << 8) /* switch off FPM */
+ str r1, [r0, #CLKCTL_CCR]
+end_clk_init:
+ .endm @ init_clock
+
+ .macro setup_pll pll_nr, mhz
+ ldr r2, BASE_ADDR_\pll_nr
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
+
+ ldr r1, W_DP_OP_\mhz
+ str r1, [r2, #PLL_DP_OP]
+ str r1, [r2, #PLL_DP_HFS_OP]
+
+ ldr r1, W_DP_MFD_\mhz
+ str r1, [r2, #PLL_DP_MFD]
+ str r1, [r2, #PLL_DP_HFS_MFD]
+
+ ldr r1, W_DP_MFN_\mhz
+ str r1, [r2, #PLL_DP_MFN]
+ str r1, [r2, #PLL_DP_HFS_MFN]
+
+ mov r1, #0x3
+ str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
+
+ @ Now restart PLL
+ ldr r1, PLL_VAL_0x1232
+ str r1, [r2, #PLL_DP_CTL]
+101:
+ ldr r1, [r2, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 101b
+ .endm
+
+ /* M3IF setup */
+ .macro init_m4if
+ ldr r1, =M4IF_BASE_ADDR
+ ldr r0, M4IF_M4IF4_VAL
+ str r0, [r1, #M4IF_MIF4]
+
+ /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
+ ldr r0, M4IF_FBPM0_VAL
+ str r0, [r1, #M4IF_FBPM0]
+ .endm /* init_m4if */
+
+ .macro setup_sdram
+ cmp r11, #0x10 // r11 contains the silicon rev
+ bls skip_setup
+#if 0
+ /* Decrease the DRAM SDCLK to HIGH Drive strength */
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x000000e5
+ str r1, [r0, #0x4b8]
+ /* Change the delay line configuration */
+ ldr r0, =ESDCTL_BASE_ADDR
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ ldr r1, =0x00f49a00
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ ldr r1, =0x00f49100
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ ldr r1, =0x00f48900
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY5]
+#endif
+skip_setup:
+ .endm
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+#define PLATFORM_VECTORS _platform_vectors
+ .macro _platform_vectors
+ .globl _KARO_MAGIC
+_KARO_MAGIC:
+ .ascii "KARO_CE6"
+ .globl _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+ .word 0 // reserve space structure length
+
+ .globl _KARO_CECFG_START
+_KARO_CECFG_START:
+ .rept 1024/4
+ .word 0 // reserve space for CE configuration
+ .endr
+
+ .globl _KARO_CECFG_END
+_KARO_CECFG_END:
+ .endm
+
+ .align 5
+ .ascii "KARO TX51 " __DATE__ " " __TIME__
+ .align
+
+/* SDRAM timing setup */
+#define RALAT 1
+#define LHD 0
+
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS 2 /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define SRT 0 /* 0: disabled *: 1: self refr. ... */
+#define PWDT 0 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define ESDCTL0_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
+
+#define tRFC 17 /* clks - 1 (0..15) */ // 17
+#define tXSR 19 /* clks - 1 (0..15) */ // 19
+#define tXP 0 /* clks - 1 (0..7) */ // N/A
+#define tWTR 0 /* clks - 1 (0..1) */ // N/A
+#define tRP 1 /* clks - 2 (0..3) */ // 1
+#define tMRD 1 /* clks - 1 (0..3) */ // 1
+#define tWR 0 /* clks - 2 (0..1) */ // 0
+#define tRAS 5 /* clks - 1 (0..15) */ // 5
+#define tRRD 1 /* clks - 1 (0..3) */ // 1
+#define tRCD 2 /* clks - 1 (0..7) */ // 2
+#define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
+
+#define ESDCFG0_VAL ((((tRFC) - 10) << 28) | ((tXSR) << 24) | ((tXP) << 21) | \
+ ((tWTR) << 20) | ((tRP) << 18) | ((tMRD) << 16) | \
+ ((tRAS) << 12) | ((tRRD) << 10) | ((tWR) << 7) | \
+ ((tRCD) << 4) | ((tRC) << 0))
+
+#define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
+#define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
+#define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
+#define ESDMISC_AP(n) (((n) & 0xf) << 16)
+#define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
+ (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
+
+ .macro flash_header
+ b reset_vector
+ .org 0x400
+app_start_addr:
+ .long reset_vector
+app_code_barker:
+ .long 0xB1
+app_code_csf:
+ .long 0 // 0x97f40000 - 0x1000
+dcd_ptr_ptr:
+ .long dcd_ptr
+super_root_key:
+ .long 0 // hab_super_root_key
+dcd_ptr:
+ .long dcd_data
+app_dest_ptr:
+#ifndef RAM_BANK1_SIZE
+ .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
+#else
+ .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
+#endif
+dcd_data:
+ .long 0xB17219E9 // Fixed. can't change.
+dcd_len:
+ .long dcd_end - dcd_start
+dcd_start:
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL0_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG0_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+dcd_end:
+image_len:
+ .long REDBOOT_IMAGE_SIZE
+ .endm
+
+SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
+WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
+AIPS1_PARAM: .word 0x77777777
+M4IF_M4IF4_VAL: .word 0x00000203
+M4IF_FIDBP_VAL: .word 0x00000a01
+M4IF_FBPM0_VAL: .word 0x00000404
+MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
+CCM_CBCDR_VAL1: .word 0x19239145
+CCM_CBCDR_VAL2: .word 0x13239145
+CCM_CBCDR_VAL3: .word 0x61E35100
+CCM_CBCMR_VAL1: .word 0x000010C0
+CCM_CBCMR_VAL2: .word 0x000020C0
+BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
+BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
+BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
+//PLL_VAL_0x222: .word 0x222
+//PLL_VAL_0x232: .word 0x232
+PLL_VAL_0x1232: .word 0x1232
+W_DP_OP_800: .word DP_OP_800
+W_DP_MFD_800: .word DP_MFD_800
+W_DP_MFN_800: .word DP_MFN_800
+W_DP_OP_700: .word DP_OP_700
+W_DP_MFD_700: .word DP_MFD_700
+W_DP_MFN_700: .word DP_MFN_700
+W_DP_OP_400: .word DP_OP_400
+W_DP_MFD_400: .word DP_MFD_400
+W_DP_MFN_400: .word DP_MFN_400
+W_DP_OP_532: .word DP_OP_532
+W_DP_MFD_532: .word DP_MFD_532
+W_DP_MFN_532: .word DP_MFN_532
+W_DP_OP_665: .word DP_OP_665
+W_DP_MFD_665: .word DP_MFD_665
+W_DP_MFN_665: .word DP_MFN_665
+W_DP_OP_216: .word DP_OP_216
+W_DP_MFD_216: .word DP_MFD_216
+W_DP_MFN_216: .word DP_MFN_216
+PLATFORM_CLOCK_DIV: .word 0x00000124
+
+#ifdef REMOVE_THIS_CRAP
+CCM_VAL_0xA5A2A020: .word 0xA5A2A020
+CCM_VAL_0x00C30321: .word 0x00C30321
+#endif
+
+/*----------------------------------------------------------------------*/
+/* end of hal_platform_setup.h */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
--- /dev/null
+#ifndef CYGONCE_KARO_TX51_H
+#define CYGONCE_KARO_TX51_H
+
+//=============================================================================
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+#define SZ_1K 0x00000400
+#define SZ_2K 0x00000800
+#define SZ_4K 0x00001000
+#define SZ_8K 0x00002000
+#define SZ_16K 0x00004000
+#define SZ_32K 0x00008000
+#define SZ_64K 0x00010000
+#define SZ_128K 0x00020000
+#define SZ_256K 0x00040000
+#define SZ_512K 0x00080000
+#define SZ_1M 0x00100000
+#define SZ_2M 0x00200000
+#define SZ_4M 0x00400000
+#define SZ_8M 0x00800000
+#define SZ_16M 0x01000000
+#define SZ_32M 0x02000000
+#define SZ_64M 0x04000000
+#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
+#define SZ_512M 0x20000000
+#define SZ_1G 0x40000000
+
+#define GPIO_DR 0x00
+#define GPIO_GDIR 0x04
+#define GPIO_PSR 0x08
+
+#define STK5_LED_MASK (1 << 10)
+#define STK5_LED_REG_ADDR (GPIO4_BASE_ADDR + GPIO_DR)
+
+#define LED_MAX_NUM 1
+
+#define SOC_FEC_MAC_BASE (IIM_BASE_ADDR + 0xc24)
+
+#define TX51_SDRAM_SIZE SDRAM_SIZE
+
+#define LED_IS_ON(n) ({ \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val & STK5_LED_MASK; \
+})
+
+#define TURN_LED_ON(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val |= STK5_LED_MASK; \
+ HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define TURN_LED_OFF(n) \
+ CYG_MACRO_START \
+ CYG_WORD32 __val; \
+ HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \
+ __val &= ~STK5_LED_MASK; \
+ HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \
+ CYG_MACRO_END
+
+#define BOARD_DEBUG_LED(n) \
+ CYG_MACRO_START \
+ if (n >= 0 && n < LED_MAX_NUM) { \
+ if (LED_IS_ON(n)) \
+ TURN_LED_OFF(n); \
+ else \
+ TURN_LED_ON(n); \
+ } \
+ CYG_MACRO_END
+
+#define BLINK_LED(l, n) \
+ CYG_MACRO_START \
+ int _i; \
+ for (_i = 0; _i < (n); _i++) { \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(200000); \
+ BOARD_DEBUG_LED(l); \
+ HAL_DELAY_US(300000); \
+ } \
+ HAL_DELAY_US(1000000); \
+ CYG_MACRO_END
+
+#if !defined(__ASSEMBLER__)
+#ifdef CYGOPT_HAL_ARM_TX51_DEBUG // REMOVE ME
+extern void plf_dumpmem(unsigned long addr, int len);
+#else
+static inline void plf_dumpmem(unsigned long addr, int len)
+{
+}
+#endif // CYGOPT_HAL_ARM_TX51_DEBUG
+
+enum {
+ BOARD_TYPE_TX51KARO,
+};
+
+#define gpio_tst_bit(grp, gpio) _gpio_tst_bit(grp, gpio, __FUNCTION__, __LINE__)
+static inline int _gpio_tst_bit(int grp, int gpio, const char *func, int line)
+{
+ if (grp < 1 || grp > 3) {
+ return 0;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return 0;
+ }
+ unsigned long val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_PSR);
+ return !!(val & (1 << gpio));
+}
+
+#include <cyg/infra/diag.h>
+static inline void gpio_set_bit(int grp, int gpio)
+{
+ unsigned long val;
+
+ if (grp < 1 || grp > 4) {
+ return;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
+ writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
+#if 0
+ if (grp != 2 || gpio != 17)
+ diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
+ grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val | (1 << gpio));
+#endif
+}
+
+static inline void gpio_clr_bit(int grp, int gpio)
+{
+ unsigned long val;
+
+ if (grp < 1 || grp > 4) {
+ return;
+ }
+ if (gpio < 0 || gpio > 31) {
+ return;
+ }
+ val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ writel(val & ~(1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
+ val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
+ writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
+#if 0
+ if (grp != 2 || gpio != 17)
+ diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
+ grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val & ~(1 << gpio));
+#endif
+}
+#endif /* __ASSEMBLER__ */
+
+#endif /* CYGONCE_KARO_TX51_H */
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_VARIANT_H
+#include CYGBLD_HAL_PLATFORM_H
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <pkgconf/redboot.h>
+
+#define SDRAM_BASE_ADDR CSD0_BASE_ADDR
+#define SDRAM_SIZE CYGNUM_HAL_ARM_TX51_SDRAM_SIZE
+
+#define UNCACHED_RAM_BASE_VIRT 0xF0000000
+
+#define SZ_128M 0x08000000
+#define RAM_BANK0_BASE CSD0_BASE_ADDR
+#define RAM_BANK1_BASE CSD1_BASE_ADDR
+#define RAM_BANK0_SIZE SZ_128M
+#if SDRAM_SIZE > RAM_BANK0_SIZE
+#define RAM_BANK1_SIZE (SDRAM_SIZE - RAM_BANK0_SIZE)
+#endif
+
+#define REDBOOT_IMAGE_SIZE CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+
+#ifndef REDBOOT_BOTTOM
+#define REDBOOT_OFFSET REDBOOT_IMAGE_SIZE
+#define CYGMEM_REGION_ram SDRAM_BASE_ADDR
+#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE)
+#else
+#define REDBOOT_OFFSET 0x00100000
+#define CYGMEM_REGION_ram (SDRAM_BASE_ADDR + REDBOOT_OFFSET)
+#define CYGMEM_REGION_rom SDRAM_BASE_ADDR
+#endif
+
+#define CYGMEM_REGION_ram_SIZE (SDRAM_SIZE - REDBOOT_OFFSET)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET
+#define CYGMEM_REGION_rom_ATTR CYGMEM_REGION_ATTR_R
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME(__heap1)[];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME(__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t)CYG_LABEL_NAME(__heap1))
--- /dev/null
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+#define __ASSEMBLER__
+#include CYGHWR_MEMORY_LAYOUT_H
+
+MEMORY
+{
+ ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE
+ rom : ORIGIN = CYGMEM_REGION_rom, LENGTH = CYGMEM_REGION_rom_SIZE
+}
+
+SECTIONS
+{
+ SECTIONS_BEGIN
+ SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA)
+ SECTION_RELOCS(rom, ALIGN (0x1), LMA_EQ_VMA)
+ SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+ SECTION_fixed_vectors (ram, CYGMEM_REGION_ram + 0x20, LMA_EQ_VMA)
+ SECTION_data (ram, CYGMEM_REGION_ram + 0x8000, FOLLOWING (.gcc_except_table))
+ SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+ CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+ SECTIONS_END
+}
--- /dev/null
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+// plf_io.h
+//
+// Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/karo_tx51.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \
+ CYG_MACRO_START \
+ { \
+ extern unsigned int system_rev; \
+ /* Next ATAG_MEM. */ \
+ _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_MEM; \
+ /* Round up so there's only one bit set in the memory size. \
+ * Don't double it if it's already a power of two, though. \
+ */ \
+ _p_->u.mem.size = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE); \
+ if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE) \
+ _p_->u.mem.size <<= 1; \
+ _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \
+ _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \
+ _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \
+ _p_->hdr.tag = ATAG_REVISION; \
+ _p_->u.revision.rev = system_rev; \
+ } \
+ CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
--- /dev/null
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+// plf_mmap.h
+//
+// Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+#include CYGHWR_MEMORY_LAYOUT_H
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \
+ (pagesize) = SZ_1M; \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+#if 1
+#define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr) \
+ CYG_MACRO_START \
+ (paddr) = hal_virt_to_phy(vaddr); \
+ CYG_MACRO_END
+#else
+#define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr) \
+ CYG_MACRO_START \
+ cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
+ if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
+ _v_ += SDRAM_BASE_ADDR; \
+ else /* Rest of it */ \
+ /* no change */ ; \
+ (paddr) = _v_; \
+ CYG_MACRO_END
+#endif
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+#ifndef RAM_BANK0_SIZE
+#warning using SDRAM_SIZE for RAM_BANK0_SIZE
+#define RAM_BANK0_SIZE SDRAM_SIZE
+#endif
+
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+ /* SDRAM mappings:
+ 90000000 -> 90000000
+ a0000000 -> 90000000 + (SDRAM_SIZE / 2)
+ */
+ if (((virt & 0xF0000000) == CSD0_BASE_ADDR) ||
+ ((virt & 0xF0000000) == UNCACHED_RAM_BASE_VIRT)) {
+ virt &= ~0xF0000000;
+ }
+ if (virt < SDRAM_SIZE) {
+ return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
+ }
+ if ((virt & 0xF0000000) == UNCACHED_RAM_BASE_VIRT) {
+ if (virt >= RAM_BANK0_SIZE) {
+ virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
+ }
+ }
+ return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+ /* (CSD0_BASE_ADDR + SZ_128M) .. (CSD0_BASE_ADDR + SZ_256M - 1) is
+ uncacheable memory space which is mapped to SDRAM */
+ if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
+ phy = (phy - CSD0_BASE_ADDR) | UNCACHED_RAM_BASE_VIRT;
+ }
+ if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
+ phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | UNCACHED_RAM_BASE_VIRT;
+ }
+ return phy;
+}
+
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
--- /dev/null
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+ description "RedBoot configuration for Ka-Ro TX51 processor module" ;
+
+ # These fields should not be modified.
+ hardware tx51karo ;
+ template redboot ;
+ package -hardware CYGPKG_HAL_ARM current ;
+ package -hardware CYGPKG_HAL_ARM_MX51 current ;
+ package -hardware CYGPKG_HAL_ARM_TX51KARO current ;
+ package -template CYGPKG_HAL current ;
+ package -template CYGPKG_INFRA current ;
+ package -template CYGPKG_REDBOOT current ;
+ package -template CYGPKG_ISOINFRA current ;
+ package -template CYGPKG_LIBC_STRING current ;
+ package -template CYGPKG_CRC current ;
+ package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+ package -hardware CYGPKG_DEVS_ETH_ARM_TX51 current ;
+ package -hardware CYGPKG_DEVS_ETH_FEC current ;
+ package -hardware CYGPKG_COMPRESS_ZLIB current ;
+ package -hardware CYGPKG_IO_FLASH current ;
+ package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+ package -hardware CYGPKG_DEVS_MXC_I2C current ;
+ package -hardware CYGPKG_DEVS_IMX_IPU current ;
+ package -template CYGPKG_MEMALLOC current ;
+ package -template CYGPKG_DEVS_ETH_PHY current ;
+ package -template CYGPKG_LIBC_I18N current ;
+ package -template CYGPKG_LIBC_STDLIB current ;
+ package -template CYGPKG_ERROR current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 {
+ inferred_value 1
+};
+
+cdl_option CYGIMP_LIBC_RAND_SIMPLE1 {
+ user_value 0
+};
+
+cdl_option CYGIMP_LIBC_RAND_KNUTH1 {
+ user_value 1
+};
+
+cdl_option CYGFUN_LIBC_STDLIB_CONV_LONGLONG {
+ user_value 0
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+ inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+ inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB {
+ inferred_value 0
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+ inferred_value 1 "Ka-Ro [exec date -I]"
+};
+
+cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+ inferred_value 1
+};
+
+cdl_option CYGBLD_BUILD_REDBOOT_WITH_WINCE_SUPPORT {
+ user_value 1
+};
+
+cdl_option CYGSEM_REDBOOT_NET_HTTP_DOWNLOAD {
+ user_value 0
+};
+
+cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_REDBOOT_PLF_ESA_VALIDATE {
+ inferred_value 1
+};
+
+cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE {
+ inferred_value 1024
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+ inferred_value 0x00040000
+};
+
+cdl_option CYGNUM_REDBOOT_FLASH_SCRIPT_SIZE {
+ inferred_value 2048
+};
+
+cdl_component CYGPKG_REDBOOT_DISK {
+ user_value 0
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION {
+ inferred_value 10
+};
+
+cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+ inferred_value 0xA0108000
+};
+
+cdl_option CYGBLD_ISO_CTYPE_HEADER {
+ inferred_value 1 <cyg/libc/i18n/ctype.inl>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER {
+ inferred_value 1 <cyg/error/codes.h>
+};
+
+cdl_option CYGBLD_ISO_ERRNO_HEADER {
+ inferred_value 1 <cyg/error/errno.h>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/atox.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/abs.inl>
+};
+
+cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER {
+ inferred_value 1 <cyg/libc/stdlib/div.inl>
+};
+
+cdl_option CYGBLD_ISO_STRERROR_HEADER {
+ inferred_value 1 <cyg/error/strerror.h>
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+ inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGSEM_IO_FLASH_READ_INDIRECT {
+ inferred_value 1
+};
+
+cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+ inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+ inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_IPU_3_EX {
+ inferred_value 1
+};
+
+cdl_component CYGHWR_FLASH_NAND_BBT_HEADER {
+ inferred_value 1 <cyg/io/tx51_nand_bbt.h>
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_MULTI {
+ inferred_value 0
+};
+
+cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO {
+ inferred_value 0
+};
+
--- /dev/null
+//==========================================================================
+//
+// mx51_fastlogo.c
+//
+// MX51 Fast Logo Implementation
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+
+// DI counter definitions
+#define DI_COUNTER_BASECLK 0
+#define DI_COUNTER_IHSYNC 1
+#define DI_COUNTER_OHSYNC 2
+#define DI_COUNTER_OVSYNC 3
+#define DI_COUNTER_ALINE 4
+#define DI_COUNTER_ACLOCK 5
+
+//extern display_buffer_info_t display_buffer;
+static display_buffer_info_t display_buffer;
+
+void fastlogo_init(display_buffer_info_t *di)
+{
+ display_buffer = *di;
+}
+
+void fastlogo_dma(void)
+{
+ ipu_channel_parameter_t ipu_channel_params;
+
+ ipu_idmac_channel_enable(display_buffer.channel, 0);
+
+ ipu_idmac_params_init(&ipu_channel_params);
+ ipu_channel_params.channel = display_buffer.channel;
+ ipu_channel_params.eba0 = display_buffer.startAddr / 8;
+ ipu_channel_params.fw = display_buffer.width - 1; /* frame width */
+ ipu_channel_params.fh = display_buffer.height - 1; /* frame height */
+ ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1;
+ ipu_channel_params.npb = 31; /* 16 pixels per burst */
+ ipu_channel_params.pfs = 7; /* 1->4:2:2 non-interleaved, 7->rgb */
+
+ switch (display_buffer.bpp) {
+ case 32:
+ ipu_channel_params.bpp = 0;
+ break;
+ case 24:
+ ipu_channel_params.bpp = 1;
+ break;
+ case 18:
+ ipu_channel_params.bpp = 2;
+ break;
+ case 16:
+ ipu_channel_params.bpp = 3;
+ break;
+ default:
+ diag_printf("%s: unsupported bpp value: %d\n", __FUNCTION__,
+ display_buffer.bpp);
+ return;
+ }
+
+ switch (display_buffer.dataFormat) {
+ case RGB565:
+ ipu_channel_params.wid0 = 5 - 1;
+ ipu_channel_params.wid1 = 6 - 1;
+ ipu_channel_params.wid2 = 5 - 1;
+ ipu_channel_params.wid3 = 0;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 5;
+ ipu_channel_params.ofs2 = 11;
+ ipu_channel_params.ofs3 = 16;
+ break;
+
+ case RGB666:
+ ipu_channel_params.wid0 = 6 - 1;
+ ipu_channel_params.wid1 = 6 - 1;
+ ipu_channel_params.wid2 = 6 - 1;
+ ipu_channel_params.wid3 = 0;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 6;
+ ipu_channel_params.ofs2 = 12;
+ ipu_channel_params.ofs3 = 18;
+ break;
+
+ case RGB888:
+ ipu_channel_params.wid0 = 8 - 1;
+ ipu_channel_params.wid1 = 8 - 1;
+ ipu_channel_params.wid2 = 8 - 1;
+ ipu_channel_params.wid3 = 0;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 8;
+ ipu_channel_params.ofs2 = 16;
+ ipu_channel_params.ofs3 = 24;
+ break;
+
+ case RGBA8888:
+ ipu_channel_params.wid0 = 8 - 1;
+ ipu_channel_params.wid1 = 8 - 1;
+ ipu_channel_params.wid2 = 8 - 1;
+ ipu_channel_params.wid3 = 8 - 1;
+ ipu_channel_params.ofs0 = 0;
+ ipu_channel_params.ofs1 = 8;
+ ipu_channel_params.ofs2 = 16;
+ ipu_channel_params.ofs3 = 24;
+ break;
+
+ default:
+ diag_printf("%s: unsupported data format: %d\n", __FUNCTION__,
+ display_buffer.dataFormat);
+ return;
+ }
+ ipu_channel_params.bm = 0;
+ ipu_channel_params.hf = 0;
+ ipu_channel_params.vf = 0;
+ ipu_channel_params.id = 0;
+ ipu_idmac_interleaved_channel_config(ipu_channel_params);
+
+ ipu_idmac_channel_mode_sel(display_buffer.channel, 0);
+ ipu_idmac_channel_enable(display_buffer.channel, 1);
+}
+
+void fastlogo_dmfc(void)
+{
+ ipu_dmfc_fifo_allocate(display_buffer.channel, 1, 0, 4);
+}
+
+void fastlogo_dc(void)
+{
+ const int display_port = 0;
+
+ //***************************************************/
+ //DI CONFIGURATION
+ //****************************************************/
+ /* MICROCODE */
+ dc_microcode_t microcode;
+ microcode.addr = 4;
+ microcode.stop = 1;
+ microcode.opcode = "WROD";
+ microcode.lf = 0;
+ microcode.af = 0;
+ microcode.operand = 0;
+ microcode.mapping = 2;
+ microcode.waveform = 1;
+ microcode.gluelogic = 0;
+ microcode.sync = 5;
+ ipu_dc_microcode_config(microcode);
+
+ ipu_dc_microcode_event(1, "NEW_DATA", 1, 4);
+
+ /* WRITE_CHAN */
+ ipu_dc_write_channel_config(display_buffer.channel, display_port, 0, 0);
+
+ /* DISP_CONF */
+ ipu_dc_display_config(display_port, 2 /* paralell */, 0,
+ display_buffer.width);
+
+ /* output data pixel format */
+ ipu_dc_map(1, RGB888);
+}
+
+void fastlogo_di(void)
+{
+ di_sync_wave_gen_t syncWaveformGen = { 0 };
+ int clkUp, clkDown;
+ int hSyncStartWidth = 36;
+ int hSyncWidth = 96;
+ int hSyncEndWidth = 76;
+ int delayH2V = display_buffer.width;
+ int hDisp = display_buffer.width;
+ int vSyncStartWidth = 11;
+ int vSyncWidth = 2;
+ int vSyncEndWidth = 32;
+ int vDisp = display_buffer.height;
+ int ipuClk = 133000000; // ipu clk is 133M
+ int typPixClk = 24000000;//25175000; // typical value of pixel clock
+ int div = (int)((float)ipuClk / (float)typPixClk + 0.5); // get the nearest value of typical pixel clock
+
+ /* DI0_SCR, set the screen height */
+ ipu_di_screen_set(0, vDisp + vSyncStartWidth + vSyncWidth + vSyncEndWidth - 1);
+
+ /* set DI_PIN15 to be waveform according to DI data wave set 3 */
+ ipu_di_pointer_config(0, 0, div - 1, div - 1, 0, 0, 0, 0, 0, 2, 0, 0);
+
+ /* set the up & down of data wave set 3. */
+ ipu_di_waveform_config(0, 0, 2, 0, div * 2); // one bit for fraction part
+
+ /* set clk for DI0, generate the base clock of DI0. */
+ clkUp = div - 2;
+ clkDown = clkUp * 2;
+ ipu_di_bsclk_gen(0, div << 4, clkUp, clkDown);
+
+ /*
+ DI0 configuration:
+ hsync - DI0 pin 3
+ vsync - DI0 pin 2
+ data_en - DI0 pin 15
+ clk - DI0 disp clk
+ COUNTER 2 for VSYNC
+ COUNTER 3 for HSYNC
+ */
+ /* internal HSYNC */
+ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncWidth + hSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = 0;
+ syncWaveformGen.offsetResolution = 0;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 1;
+ ipu_di_sync_config(0, DI_COUNTER_IHSYNC, syncWaveformGen);
+
+ /* OUTPUT HSYNC */
+ syncWaveformGen.runValue = hDisp + hSyncStartWidth + hSyncWidth + hSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = delayH2V;
+ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = div * hSyncWidth;
+ ipu_di_sync_config(0, DI_COUNTER_OHSYNC, syncWaveformGen);
+
+ /* Output Vsync */
+ syncWaveformGen.runValue = vDisp + vSyncStartWidth + vSyncWidth + vSyncEndWidth - 1;
+ syncWaveformGen.runResolution = DI_COUNTER_IHSYNC + 1;
+ syncWaveformGen.offsetValue = 0;
+ syncWaveformGen.offsetResolution = 0;
+ syncWaveformGen.cntAutoReload = 1;
+ syncWaveformGen.stepRepeat = 0;
+ syncWaveformGen.cntClrSel = 0;
+ syncWaveformGen.cntPolarityGenEn = 1;
+ syncWaveformGen.cntPolarityTrigSel = 2;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = vSyncWidth;
+ ipu_di_sync_config(0, DI_COUNTER_OVSYNC, syncWaveformGen);
+
+ /* Active Lines start points */
+ syncWaveformGen.runValue = 0;
+ syncWaveformGen.runResolution = DI_COUNTER_OHSYNC + 1;
+ syncWaveformGen.offsetValue = vSyncWidth;
+ syncWaveformGen.offsetResolution = DI_COUNTER_OHSYNC + 1;
+ syncWaveformGen.cntAutoReload = 0;
+ syncWaveformGen.stepRepeat = vDisp;
+ syncWaveformGen.cntClrSel = DI_COUNTER_OVSYNC + 1;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 0;
+ ipu_di_sync_config(0, DI_COUNTER_ALINE, syncWaveformGen);
+
+ /* Active clock start points */
+ syncWaveformGen.runValue = 0;
+ syncWaveformGen.runResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.offsetValue = hSyncWidth;
+ syncWaveformGen.offsetResolution = DI_COUNTER_BASECLK + 1;
+ syncWaveformGen.cntAutoReload = 0;
+ syncWaveformGen.stepRepeat = hDisp;
+ syncWaveformGen.cntClrSel = DI_COUNTER_ALINE + 1;
+ syncWaveformGen.cntPolarityGenEn = 0;
+ syncWaveformGen.cntPolarityTrigSel = 0;
+ syncWaveformGen.cntPolarityClrSel = 0;
+ syncWaveformGen.cntUp = 0;
+ syncWaveformGen.cntDown = 0;
+ ipu_di_sync_config(0, DI_COUNTER_ACLOCK, syncWaveformGen);
+
+ ipu_di_general_set(0, 1, 2, 1, 0);
+}
--- /dev/null
+//==========================================================================
+//
+// redboot_cmds.c
+//
+// Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+#endif //CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGPKG_IO_FLASH
+#include <cyg/io/flash.h>
+#endif
+
+char HAL_PLATFORM_EXTRA[40] = "PASS x.x [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+static void do_mem(int argc, char *argv[]);
+
+RedBoot_cmd("mem",
+ "Set a memory location",
+ "[-h|-b] [-n] [-a <address>] <data>",
+ do_mem
+ );
+
+RedBoot_cmd("run",
+ "Run an image at a location with MMU off",
+ "[<virtual addr>]",
+ runImg
+ );
+
+static void do_mem(int argc, char *argv[])
+{
+ struct option_info opts[4];
+ bool mem_half_word, mem_byte;
+ bool no_verify;
+ bool addr_set;
+ unsigned long address;
+ unsigned int value;
+ int ret;
+ init_opts(&opts[0], 'b', false, OPTION_ARG_TYPE_FLG,
+ &mem_byte, NULL, "write a byte");
+ init_opts(&opts[1], 'h', false, OPTION_ARG_TYPE_FLG,
+ &mem_half_word, NULL, "write a half-word");
+ init_opts(&opts[2], 'a', true, OPTION_ARG_TYPE_NUM,
+ &address, &addr_set, "address to write to");
+ init_opts(&opts[3], 'n', false, OPTION_ARG_TYPE_FLG,
+ &no_verify, NULL, "noverify");
+
+ ret = scan_opts(argc, argv, 1, opts, sizeof(opts) / sizeof(opts[0]),
+ &value, OPTION_ARG_TYPE_NUM, "value to be written");
+ if (ret == 0) {
+ return;
+ }
+ if (!addr_set) {
+ diag_printf("** Error: '-a <address>' must be specified\n");
+ return;
+ }
+ if (ret == argc + 1) {
+ diag_printf("** Error: non-option argument '<value>' must be specified\n");
+ return;
+ }
+ if (mem_byte && mem_half_word) {
+ diag_printf("** Error: Should not specify both byte and half-word access\n");
+ } else if (mem_byte) {
+ value &= 0xff;
+ *(volatile cyg_uint8*)address = (cyg_uint8)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%02X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%02X (result 0x%02X)\n",
+ address, value, (int)*(cyg_uint8*)address );
+ }
+ } else if (mem_half_word) {
+ if (address & 1) {
+ diag_printf("** Error: address for half-word access must be half-word aligned\n");
+ } else {
+ value &= 0xffff;
+ *(volatile cyg_uint16*)address = (cyg_uint16)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%04X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%04X (result 0x%04X)\n",
+ address, value, (int)*(cyg_uint16*)address);
+ }
+ }
+ } else {
+ if (address & 3) {
+ diag_printf("** Error: address for word access must be word aligned\n");
+ } else {
+ *(volatile cyg_uint32*)address = (cyg_uint32)value;
+ if (no_verify) {
+ diag_printf(" Set 0x%08lX to 0x%08X\n", address, value);
+ } else {
+ diag_printf(" Set 0x%08lX to 0x%08X (result 0x%08X)\n",
+ address, value, (int)*(cyg_uint32*)address);
+ }
+ }
+ }
+}
+
+void launchRunImg(unsigned long addr)
+{
+ asm volatile ("mov r1, r0;");
+ HAL_MMU_OFF();
+ asm volatile (
+ "mov r11, #0;"
+ "mov r12, #0;"
+ "mrs r10, cpsr;"
+ "bic r10, r10, #0xF0000000;"
+ "msr cpsr_f, r10;"
+ "mov pc, r1"
+ );
+}
+
+static void runImg(int argc,char *argv[])
+{
+ unsigned int virt_addr, phys_addr;
+
+ // Default physical entry point for Symbian
+ if (entry_address == 0xFFFFFFFF)
+ virt_addr = 0x800000;
+ else
+ virt_addr = entry_address;
+
+ if (!scan_opts(argc, argv, 1, 0, 0, &virt_addr,
+ OPTION_ARG_TYPE_NUM, "virtual address"))
+ return;
+
+ if (entry_address != 0xFFFFFFFF)
+ diag_printf("load entry_address=0x%lx\n", entry_address);
+ HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+ diag_printf("virt_addr=0x%x\n",virt_addr);
+ diag_printf("phys_addr=0x%x\n",phys_addr);
+
+ launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+ "Update Redboot with currently running image",
+ "",
+ romupdate
+ );
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+ void *err_addr, *base_addr;
+ int stat;
+
+ base_addr = (void*)(MXC_NAND_BASE_DUMMY + CYGBLD_REDBOOT_FLASH_BOOT_OFFSET);
+ diag_printf("Updating RedBoot in NAND flash\n");
+
+ // Erase area to be programmed
+ if ((stat = flash_erase(base_addr, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't erase region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ return;
+ }
+ // Now program it
+ if ((stat = flash_program(base_addr, ram_end,
+ CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) {
+ diag_printf("Can't program region at %p: %s\n",
+ err_addr, flash_errmsg(stat));
+ }
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
--- /dev/null
+//==========================================================================
+//
+// tx51_misc.c
+//
+// HAL misc board support code for the tx51
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <stdlib.h>
+#include <redboot.h>
+#include <string.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
+
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/mx51_iomux.h>
+#include <cyg/hal/karo_tx51.h> // Platform specifics
+
+#include <cyg/infra/diag.h> // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+
+/* MMU table definitions */
+#define SD_P0 (RAM_BANK0_BASE >> 20) /* physical RAM bank 0 address */
+#define SD_C0 SD_P0 /* virtual address for cached 1:1 mapping */
+#define SD_S0 (RAM_BANK0_SIZE >> 20) /* RAM bank 0 size */
+#define SD_U0 (UNCACHED_RAM_BASE_VIRT >> 20)
+#ifdef RAM_BANK1_SIZE
+#define SD_P1 (RAM_BANK1_BASE >> 20) /* physical RAM bank 1 address */
+#define SD_C1 (SD_P0 + SD_S0)
+#define SD_S1 (RAM_BANK1_SIZE >> 20) /* RAM bank 1 size */
+#define SD_U1 (SD_U0 + SD_S0)
+#define SD_HI (SD_P1 + (SD_S1 - 1))
+#endif
+
+static unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+
+void hal_mmu_init(void)
+{
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base));
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+ /* Physical Virtual Size Attributes access permissions Function */
+ /* Base Base MB cached? buffered? */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
+ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x600, 0x600, 0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
+ X_ARM_MMU_SECTION(SD_P0, 0x000, SD_S0, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(SD_P0, SD_C0, SD_S0, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(SD_P0, SD_U0, SD_S0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM (uncached) */
+#ifdef RAM_BANK1_SIZE
+ X_ARM_MMU_SECTION(SD_P1, SD_S0, SD_S1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(SD_P1, SD_C1, SD_S1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(SD_P1, SD_U1, SD_S1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ /* make sure the last MiB in the upper bank of SDRAM (where RedBoot resides)
+ * has a unity mapping (required when switching MMU on) */
+ X_ARM_MMU_SECTION(SD_HI, SD_HI, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RO_RO); /* SDRAM bank1 identity mapping */
+#endif
+ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x010, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control */
+ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+}
+
+static inline void set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
+{
+ CYG_WORD32 val;
+
+ HAL_READ_UINT32(addr, val);
+ val = (val & ~clr) | set;
+ HAL_WRITE_UINT32(addr, val);
+}
+
+#define GPIO_BASE(grp) (GPIO1_BASE_ADDR + (((grp) - 1) << 14))
+static inline void setup_gpio(int grp, int bit)
+{
+ set_reg(GPIO_BASE(grp) + GPIO_DR, 0, 1 << bit);
+ set_reg(GPIO_BASE(grp) + GPIO_GDIR, 1 << bit, 0);
+}
+
+//
+// Platform specific initialization
+//
+static void uart_gpio_init(void)
+{
+ writel(0, IOMUXC_SW_MUX_CTL_PAD_UART1_TXD);
+ writel(0, IOMUXC_SW_MUX_CTL_PAD_UART1_RXD);
+ /* pad_ctl: PKE | PUE | DSE_HIGH | SRE */
+ writel(0x0c5, IOMUXC_SW_PAD_CTL_PAD_UART1_TXD);
+ /* pad_ctl: HYS | PKE | PUE | DSE_HIGH | SRE */
+ writel(0x1c5, IOMUXC_SW_PAD_CTL_PAD_UART1_RXD);
+ /* pad_ctl: HYS | PKE | PUE | DSE_HIGH */
+ writel(0x1c4, IOMUXC_SW_PAD_CTL_PAD_UART1_RTS);
+ writel(0x1c4, IOMUXC_SW_PAD_CTL_PAD_UART1_CTS);
+}
+
+/* GPIOs to set up for TX51/Starterkit-5:
+ Function FCT GPIO Pad IOMUXC SW_PAD SW_PAD mode
+ OFFSET CTRL MUX
+FEC_MDC 2 GPIO3_19 NANDF_CS3 0x13c 0x524
+FEC_MDIO 3 GPIO2_22 EIM_EB2 0x0d4 0x468 0x954 0
+FEC_RX_CLK 1 GPIO3_11 NANDF_RB3 0x128 0x504 0x968 0
+FEC_RX_DV 2 GPIO3_29 NANDF_D11 0x164 0x54c 0x96c 0
+FEC_RXD0 2 GPIO3_31 NANDF_D9 0x16c 0x554 0x958 0
+FEC_RXD1 3 GPIO2_23 EIM_EB3 0x0d8 0x64c 0x95c 0
+FEC_RXD2 3 GPIO2_27 EIM_CS2 0x0e8 0x47c 0x960 0
+FEC_RXD3 3 GPIO2_28 EIM_CS3 0x0ec 0x480 0x964 0
+FEC_RX_ER 3 GPIO2_29 EIM_CS4 0x0f0 0x484 0x970 0
+FEC_TX_CLK 1 GPIO3_24 NANDF_RDY_INT 0x150 0x538 0x974 0
+FEC_TX_EN 1 GPIO3_23 NANDF_CS7 0x14c 0x534
+FEC_TXD0 2 GPIO4_0 NANDF_D8 0x170 0x558
+FEC_TXD1 2 GPIO3_20 NANDF_CS4 0x140 0x528
+FEC_TXD2 2 GPIO3_21 NANDF_CS5 0x144 0x52c
+FEC_TXD3 2 GPIO3_22 NANDF_CS6 0x148 0x530
+FEC_COL 1 GPIO3_10 NANDF_RB2 0x124 0x500 0x94c 0
+FEC_CRS 3 GPIO2_30 EIM_CS5 0x0f4 0x488 0x950 0
+FEC_TX_ER 2 GPIO3_18 NANDF_CS2 0x138 0x520 (INT)
+
+FEC_RESET# 1 GPIO2_14 EIM_A20 0x0ac 0x440
+FEC_ENABLE 0 GPIO1_3 GPIO1_3 0x3d0 0x7d8
+---
+OSC26M_ENABLE LP3972 GPIO2
+*/
+static void fec_gpio_init(void)
+{
+ /* setup GPIO data register to 0 and DDIR output for FEC PHY pins */
+ setup_gpio(3, 19);
+ setup_gpio(2, 22);
+ setup_gpio(3, 11);
+ setup_gpio(3, 29);
+ setup_gpio(3, 31);
+ setup_gpio(2, 23);
+ setup_gpio(2, 27);
+ setup_gpio(2, 28);
+ setup_gpio(2, 29);
+ setup_gpio(3, 24);
+ setup_gpio(3, 23);
+ setup_gpio(4, 0);
+ setup_gpio(3, 20);
+ setup_gpio(3, 21);
+ setup_gpio(3, 22);
+ setup_gpio(3, 10);
+ setup_gpio(2, 30);
+ setup_gpio(3, 18);
+
+ setup_gpio(2, 14);
+ setup_gpio(1, 3);
+
+ /* setup input mux for FEC pins */
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_MDI_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_COL_SELECT_INPUT, 0);
+ HAL_WRITE_UINT32(IOMUXC_FEC_FEC_CRS_SELECT_INPUT, 0);
+
+ /* setup FEC PHY pins for GPIO function (with SION set) */
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, 2 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, 3 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, 3 | 0x10);
+
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_EIM_A20, 1 | 0x10);
+ HAL_WRITE_UINT32(IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, 0 | 0x10);
+}
+
+#ifdef CYGHWR_MX51_LCD_LOGO
+void mxc_ipu_iomux_config(void)
+{
+ // configure display data0~17 for LCD panel
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2,0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10, 0x5);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16, 0x5);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17, 0x5);
+
+ // DI1_PIN2 and DI1_PIN3, configured to be HSYNC and VSYNC of LCD
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+
+ // PCLK - DISP_CLK
+ // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+ // DRDY - PIN15
+ // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+ // configure this pin to be the SER_DISP_CS
+
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT4);
+ CONFIG_PIN(IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS, 0x85);
+
+ // configure to be DISPB1_SER_RS
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP1, 0x85);
+ // configure to be SER_DISP1_CLK
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP2, 0x85);
+ // configure to be DISPB1_SER_DIO
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP3, 0xC5);
+ // configure to be DISPB1_SER_DIN
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP4, 0xC4);
+ //CS0
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS, 0x85);
+ // WR
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11, 0x85);
+ // RD
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12, 0x85);
+ // RS
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT1);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13, 0x85);
+
+ /* LCD Power Enable GPIO4_14 (active High) */
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT3);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC, 0x04);
+ gpio_set_bit(4, 14);
+
+ /* LCD Reset GPIO4_13 (active Low) */
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT3);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC, 0x04);
+ gpio_set_bit(4, 13);
+
+ /* LCD Backlight GPIO1_2 (PWM 0: full brightness 1: off) */
+ CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_2, IOMUX_PIN_SION_REGULAR | IOMUX_SW_MUX_CTL_ALT0);
+ CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_GPIO1_2, 0x04);
+ gpio_clr_bit(1, 2);
+}
+RedBoot_init(mxc_ipu_iomux_config, RedBoot_INIT_SECOND);
+#endif
+
+//
+// Platform specific initialization
+//
+
+void plf_hardware_init(void)
+{
+#ifdef RAM_BANK1_SIZE
+ /* destroy mapping for high area in SDRAM */
+ X_ARM_MMU_SECTION(SD_HI, 0, 0, 0, 0, ARM_ACCESS_PERM_NONE_NONE);
+#endif
+ uart_gpio_init();
+ fec_gpio_init();
+
+ /* NFC setup */
+ writel(readl(NFC_FLASH_CONFIG3_REG) |
+ (1 << 15) | /* assert RBB_MODE (see Errata: ENGcm09970) */
+ (1 << 20) | /* assert NO_SDMA */
+ (1 << 3), /* set bus width to 8bit */
+ NFC_FLASH_CONFIG3_REG);
+
+ /* configure MIPI-HSC legacy mode required to get data on DISP1_DAT[0..5] */
+ writel(0xf00, MIPI_HSC_BASE_ADDR);
+ /* bypass MDT and enable legacy CSI interface */
+ writel((3 << 16) | (2 << 2) | (2 << 0), MIPI_HSC_BASE_ADDR + 0x800);
+}
+
+static int lp3972_reg_read(cyg_uint8 reg)
+{
+ int ret;
+ ret = -ENOSYS;
+ return ret;
+}
+
+static int lp3972_reg_write(cyg_uint8 reg, cyg_uint8 val)
+{
+ int ret;
+ ret = -ENOSYS;
+ return ret;
+}
+
+int tx51_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
+{
+ int ret = 0;
+ int i;
+
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ unsigned char fuse = readl(SOC_FEC_MAC_BASE +
+ ETHER_ADDR_LEN * 4 - ((i + 1) << 2));
+
+ if ((fuse | mac_addr[i]) != mac_addr[i]) {
+ diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
+ i, fuse, mac_addr[i]);
+ return -1;
+ }
+ if (fuse != mac_addr[i]) {
+ ret = 1;
+ }
+ }
+ if (ret == 0) {
+ return ret;
+ }
+ ret = lp3972_reg_write(0x39, 0xf0);
+ if (ret < 0) {
+ diag_printf("Failed to switch fuse programming voltage: %d\n", ret);
+ return ret;
+ }
+ ret = lp3972_reg_read(0x39);
+ if (ret != 0xf0) {
+ diag_printf("Failed to switch fuse programming voltage: %d\n", ret);
+ return ret;
+ }
+ for (i = 0; i < ETHER_ADDR_LEN; i++) {
+ int bit;
+ unsigned char fuse = readl(SOC_FEC_MAC_BASE +
+ ETHER_ADDR_LEN * 4 - ((i + 1) << 2));
+
+ for (bit = 0; bit < 8; bit++) {
+ if (((mac_addr[i] >> bit) & 0x1) == 0)
+ continue;
+ if (((mac_addr[i] >> bit) & 1) == ((fuse >> bit) & 1)) {
+ continue;
+ }
+ if (fuse_blow(SOC_MAC_ADDR_FUSE_BANK,
+ SOC_MAC_ADDR_FUSE + ETHER_ADDR_LEN - 1 - i,
+ bit)) {
+ diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
+ i, bit);
+ ret = -1;
+ goto out;
+ }
+ }
+ }
+#ifdef SOC_MAC_ADDR_LOCK_BIT
+ fuse_blow(SOC_MAC_ADDR_FUSE_BANK, SOC_MAC_ADDR_LOCK_FUSE,
+ SOC_MAC_ADDR_LOCK_BIT);
+#endif
+out:
+ lp3972_reg_write(0x39, 0);
+ return ret;
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void tx51_program_new_stack(void *func)
+{
+ register CYG_ADDRESS stack_ptr asm("sp");
+ register CYG_ADDRESS old_stack asm("r4");
+ register code_fun *new_func asm("r0");
+ old_stack = stack_ptr;
+ stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+ new_func = (code_fun*)func;
+ new_func();
+ stack_ptr = old_stack;
+}
+
+void increase_core_voltage(bool i)
+{
+ int ret;
+
+ ret = lp3972_reg_read(0x23);
+ if (ret < 0) {
+ diag_printf("Failed to read core voltage: %d\n", ret);
+ }
+
+ if (i) {
+ /* Set core voltage to 1.175V */
+ ret = 0x12;
+ } else {
+ /* Set core voltage to 1.05V */
+ ret = 0x0d;
+ }
+
+ ret = lp3972_reg_write(0x23, ret);
+ if (ret < 0) {
+ diag_printf("Failed to write core voltage: %d\n", ret);
+ }
+}
+
+static unsigned long random;
+/* provide at least _some_ sort of randomness */
+#define MAX_LOOPS 100
+extern int hal_timer_count(void);
+
+static void random_init(void)
+{
+ unsigned long timer;
+
+ int loops = MAX_LOOPS;
+
+ do {
+ timer = hal_timer_count();
+ srand(random + timer);
+ random = rand();
+ } while ((timer < 5) || ((timer & (random >> (random & 0x1f))) && --loops > 0));
+}
+RedBoot_init(random_init, RedBoot_INIT_FIRST);
+
+#define WDOG_WRSR ((CYG_WORD16 *)0x10002004)
+static void display_board_type(void)
+{
+ CYG_WORD32 reset_cause;
+ const char *dlm = "";
+
+ diag_printf("\nBoard Type: Ka-Ro TX51\n");
+ diag_printf("Last RESET cause: ");
+ HAL_READ_UINT32(SRC_BASE_ADDR + 8, reset_cause);
+
+ if ((reset_cause & 9) == 1) {
+ diag_printf("%sPOWER_ON RESET", dlm);
+ dlm = " | ";
+ } else if ((reset_cause & 9) == 9) {
+ diag_printf("%sUSER RESET", dlm);
+ dlm = " | ";
+ }
+ if ((reset_cause & 0x11) == 0x11) {
+ diag_printf("%sWATCHDOG RESET", dlm);
+ dlm = " | ";
+ } else if ((reset_cause & 0x11) == 0x10) {
+ diag_printf("%sSOFT RESET", dlm);
+ dlm = " | ";
+ }
+ if (*dlm == '\0') {
+ diag_printf("UNKNOWN: %08x\n", reset_cause);
+ } else {
+ diag_printf("\n");
+ }
+}
+
+static void display_board_info(void)
+{
+ display_board_type();
+}
+RedBoot_init(display_board_info, RedBoot_INIT_LAST);
+
+void mxc_i2c_init(unsigned int module_base)
+{
+ switch (module_base) {
+ case I2C_BASE_ADDR:
+ writel(0x11, IOMUXC_BASE_ADDR + 0x210);
+ writel(0x1ad, IOMUXC_BASE_ADDR + 0x600);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x9B4);
+
+ writel(0x11, IOMUXC_BASE_ADDR + 0x224);
+ writel(0x1ad, IOMUXC_BASE_ADDR + 0x614);
+ writel(0x1, IOMUXC_BASE_ADDR + 0x9B0);
+ break;
+ case I2C2_BASE_ADDR:
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
+
+ writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+ writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
+ writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
+ break;
+ default:
+ diag_printf("Invalid I2C base: 0x%x\n", module_base);
+ return;
+ }
+}
puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
}
}
+
+ cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+ display "FEC ethernet driver required"
+ }
+
+ implements CYGINT_DEVS_ETH_FEC_REQUIRED
}
cdl_option CYGHWR_MX51_TO2 {
display "MX51 Tapeout 2.0 support"
- default_value 0
+ default_value 1
description "
When this option is enabled, it indicates support for
MX51 Tapeout 2.0"
}
}
+ cdl_option CYGHWR_MX51_MDDR {
+ display "MX51 mDDR memory support"
+ default_value 0
+ description "
+ When this option is enabled, it indicates support for
+ mDDR memory on MX51"
+ define_proc {
+ puts $::cdl_system_header "#define IMX51_MDDR"
+ }
+ }
+
cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
display "Processor clock rate"
active_if { CYG_HAL_STARTUP == "ROM" }
interface allows a platform to indicate that the specified
serial port can be used as a diagnostic and/or debug channel."
}
-
- cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
- display "FEC ethernet driver required"
- }
-
- implements CYGINT_DEVS_ETH_FEC_REQUIRED
-
}
//=============================================================================
#include <cyg/infra/cyg_type.h>
-#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
+#include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
//-----------------------------------------------------------------------------
// Global control of data cache
// Enable the data cache
-#define HAL_DCACHE_ENABLE_L1() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15, 0, r1, c1, c0, 0;" \
- "orr r1, r1, #0x0007;" /* enable DCache (also ensures */ \
- /* the MMU, alignment faults, and */ \
- "mcr p15, 0, r1, c1, c0, 0" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_DCACHE_ENABLE_L1() \
+ CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x0007;" /* enable DCache (also ensures \
+ that MMU and alignment faults \
+ are enabled) */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+ CYG_MACRO_END
// Clean+invalidate the both D+I caches at L1 and L2 levels
-#define HAL_CACHE_FLUSH_ALL() \
-CYG_MACRO_START \
- asm volatile ( \
- "stmfd sp!, {r0-r5, r7, r9-r11};" \
- "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \
- "ands r3, r0, #0x7000000;" /*@ extract loc from clidr */ \
- "mov r3, r3, lsr #23;" /*@ left align loc bit field*/ \
- "beq 555f;" /* finished;" */ /*@ if loc is 0, then no need to clean*/ \
- "mov r10, #0;" /*@ start clean at cache level 0*/ \
- "111:" /*"loop1: */ \
- "add r2, r10, r10, lsr #1;" /*@ work out 3x current cache level*/ \
- "mov r1, r0, lsr r2;" /*@ extract cache type bits from clidr*/ \
- "and r1, r1, #7;" /*@ mask of the bits for current cache only*/ \
- "cmp r1, #2;" /*@ see what cache we have at this level*/ \
- "blt 444f;" /* skip;" */ /*@ skip if no cache, or just i-cache*/ \
- "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr*/ \
- "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \
- "mrc p15, 1, r1, c0, c0, 0;" /*@ read the new csidr*/ \
- "and r2, r1, #7;" /*@ extract the length of the cache lines*/ \
- "add r2, r2, #4;" /*@ add 4 (line length offset) */ \
- "ldr r4, =0x3ff;" \
- "ands r4, r4, r1, lsr #3;" /*@ find maximum number on the way size*/ \
- ".word 0xE16F5F14;" /*"clz r5, r4;" @ find bit position of way size increment*/ \
- "ldr r7, =0x7fff;" \
- "ands r7, r7, r1, lsr #13;" /*@ extract max number of the index size*/ \
- "222:" /* loop2:" */ \
- "mov r9, r4;" /*@ create working copy of max way size*/ \
- "333:" /* loop3:" */ \
- "orr r11, r10, r9, lsl r5;" /*@ factor way and cache number into r11*/ \
- "orr r11, r11, r7, lsl r2;" /*@ factor index number into r11*/ \
- "mcr p15, 0, r11, c7, c14, 2;" /*@ clean & invalidate by set/way */ \
- "subs r9, r9, #1;" /*@ decrement the way */ \
- "bge 333b;" /* loop3;" */ \
- "subs r7, r7, #1;" /*@ decrement the index */ \
- "bge 222b;" /* loop2;" */ \
- "444:" /* skip:" */ \
- "add r10, r10, #2;" /*@ increment cache number */ \
- "cmp r3, r10;" \
- "bgt 111b;" /*loop1;" */ \
- "555:" /* "finished:" */ \
- "mov r10, #0;" /*@ swith back to cache level 0 */ \
- "mcr p15, 2, r10, c0, c0, 0;" /*@ select current cache level in cssr */ \
- "mcr p15, 0, r10, c7, c5, 4;" /* @ isb to sych the new cssr&csidr */ \
- "ldmfd sp!, {r0-r5, r7, r9-r11};" \
- "666:" /* iflush:" */ \
- "mov r0, #0x0;" \
- "mcr p15, 0, r0, c7, c5, 0;" /* @ invalidate I+BTB */ \
- "mcr p15, 0, r0, c7, c10, 4;" /* @ drain WB */ \
- ); \
-CYG_MACRO_END
+#define HAL_CACHE_FLUSH_ALL() \
+ CYG_MACRO_START \
+ asm volatile ( \
+ "stmfd sp!, {r0-r5, r7, r9-r11};" \
+ "mrc p15, 1, r0, c0, c0, 1;" /* read clidr */ \
+ "ands r3, r0, #0x7000000;" /* extract loc from clidr */ \
+ "mov r3, r3, lsr #23;" /* left align loc bit field */ \
+ "beq 555f;" /* if loc is 0, then no need to clean */ \
+ "mov r10, #0;" /* start clean at cache level 0 */ \
+ "111:" \
+ "add r2, r10, r10, lsr #1;" /* work out 3x current cache level */ \
+ "mov r1, r0, lsr r2;"/* extract cache type bits from clidr */ \
+ "and r1, r1, #7;" /* mask of the bits for current cache only */ \
+ "cmp r1, #2;" /* see what cache we have at this level*/ \
+ "blt 444f;" /* skip if no cache, or just i-cache */ \
+ "mcr p15, 2, r10, c0, c0, 0;" /* select current cache level in cssr */ \
+ "mcr p15, 0, r10, c7, c5, 4;" /* isb to synch the new cssr & csidr */ \
+ "mrc p15, 1, r1, c0, c0, 0;" /* read the new csidr */ \
+ "and r2, r1, #7;" /* extract the length of the cache lines */ \
+ "add r2, r2, #4;" /* add 4 (line length offset) */ \
+ "ldr r4, =0x3ff;" \
+ "ands r4, r4, r1, lsr #3;" /* find maximum number on the way size */ \
+ "clz r5, r4;" /* find bit position of way size increment*/ \
+ "ldr r7, =0x7fff;" \
+ "ands r7, r7, r1, lsr #13;" /* extract max number of the index size */ \
+ "222:" \
+ "mov r9, r4;" /* create working copy of max way size */ \
+ "333:" \
+ "orr r11, r10, r9, lsl r5;" /* factor way and cache number into r11 */ \
+ "orr r11, r11, r7, lsl r2;" /* factor index number into r11 */ \
+ "mcr p15, 0, r11, c7, c14, 2;" /* clean & invalidate by set/way */ \
+ "subs r9, r9, #1;" /* decrement the way */ \
+ "bge 333b;" \
+ "subs r7, r7, #1;" /* decrement the index */ \
+ "bge 222b;" \
+ "444:" \
+ "add r10, r10, #2;" /* increment cache number */ \
+ "cmp r3, r10;" \
+ "bgt 111b;" \
+ "555:" \
+ "mov r10, #0;" /* swith back to cache level 0 */ \
+ "mcr p15, 2, r10, c0, c0, 0;" /* select current cache level in cssr */ \
+ "mcr p15, 0, r10, c7, c5, 4;" /* isb to synch the new cssr & csidr */ \
+ "ldmfd sp!, {r0-r5, r7, r9-r11};" \
+ "666:" \
+ "mov r0, #0x0;" \
+ "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I+BTB */ \
+ "mcr p15, 0, r0, c7, c10, 4;" /* drain WB */ \
+ : \
+ : \
+ : "r0" /* Clobber list */ \
+ ); \
+ CYG_MACRO_END
// Disable the data cache
-#define HAL_DCACHE_DISABLE_C1() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15, 0, r1, c1, c0, 0;" \
- "bic r1, r1, #0x0004;" /* disable DCache by clearing C bit */ \
- /* but not MMU and alignment faults */ \
- "mcr p15, 0, r1, c1, c0, 0" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_DCACHE_DISABLE_L1() \
+ CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "bic r1, r1, #0x0004;" /* disable DCache by clearing C bit, \
+ but not MMU and alignment faults */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+ CYG_MACRO_END
// Query the state of the data cache
-#define HAL_DCACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- register int reg; \
- asm volatile ( \
- "nop; " \
- "nop; " \
- "nop; " \
- "nop; " \
- "nop; " \
- "mrc p15, 0, %0, c1, c0, 0;" \
- : "=r"(reg) \
- : \
- ); \
- (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
-CYG_MACRO_END
+#define HAL_DCACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0;" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
+ CYG_MACRO_END
//-----------------------------------------------------------------------------
// Global control of Instruction cache
// Enable the instruction cache
-#define HAL_ICACHE_ENABLE_L1() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15, 0, r1, c1, c0, 0;" \
- "orr r1, r1, #0x1000;" \
- "orr r1, r1, #0x0003;" /* enable ICache (also ensures */ \
- /* that MMU and alignment faults */ \
- /* are enabled) */ \
- "mcr p15, 0, r1, c1, c0, 0" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_ICACHE_ENABLE_L1() \
+ CYG_MACRO_START \
+ asm volatile ( \
+ "mrc p15, 0, r1, c1, c0, 0;" \
+ "orr r1, r1, #0x1000;" \
+ "orr r1, r1, #0x0003;" /* enable ICache (also ensures \
+ that MMU and alignment faults \
+ are enabled) */ \
+ "mcr p15, 0, r1, c1, c0, 0" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+ CYG_MACRO_END
// Query the state of the instruction cache
-#define HAL_ICACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- register cyg_uint32 reg; \
- asm volatile ( \
- "mrc p15, 0, %0, c1, c0, 0" \
- : "=r"(reg) \
- : \
- ); \
- \
- (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
-CYG_MACRO_END
+#define HAL_ICACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ register cyg_uint32 reg; \
+ asm volatile ( \
+ "mrc p15, 0, %0, c1, c0, 0" \
+ : "=r"(reg) \
+ : \
+ ); \
+ (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
+ CYG_MACRO_END
// Disable the instruction cache
-#define HAL_ICACHE_DISABLE_L1() \
-CYG_MACRO_START \
- asm volatile ( \
- "mrc p15, 0, r1, c1, c0, 0;" \
- "bic r1, r1, #0x1000;" /* disable ICache (but not MMU, etc) */ \
- "mcr p15, 0, r1, c1, c0, 0;" \
- "mov r1, #0;" \
- "nop;" /* next few instructions may be via cache */ \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
+#define HAL_ICACHE_DISABLE_L1() \
+CYG_MACRO_START \
+ asm volatile ( \
+ /* prepare to disable ICache (but not MMU, etc) */ \
+ "mrc p15, 0, r2, c1, c0, 0;" \
+ "mov r1, #0;" \
+ "bic r2, r2, #0x1000;" \
+ /* align to cache line */ \
+ "b 1f;" \
+ ".align 5;" \
+ "1:;" \
+ /* flush icache */ \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ /* disable icache */ \
+ "mcr p15, 0, r2, c1, c0, 0;" \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1","r2" /* Clobber list */ \
+ ); \
CYG_MACRO_END
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL_L1()
#ifdef TODO
-#define HAL_ICACHE_INVALIDATE_ALL_L1() \
-CYG_MACRO_START \
- /* this macro can discard dirty cache lines (N/A for ICache) */ \
- asm volatile ( \
- "mov r1, #0;" \
- "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
- "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
- "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
- "nop;" /* next few instructions may be via cache */ \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- "nop;" \
- : \
- : \
- : "r1" /* Clobber list */ \
- ); \
-CYG_MACRO_END
+#define HAL_ICACHE_INVALIDATE_ALL_L1() \
+ CYG_MACRO_START \
+ /* this macro can discard dirty cache lines (N/A for ICache) */ \
+ asm volatile ( \
+ "mov r1, #0;" \
+ "mcr p15, 0, r1, c7, c5, 0;" /* flush ICache */ \
+ "mcr p15, 0, r1, c8, c5, 0;" /* flush ITLB only */ \
+ "mcr p15, 0, r1, c7, c5, 4;" /* flush prefetch buffer */ \
+ "nop;" /* next few instructions may be via cache */ \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ : \
+ : \
+ : "r1" /* Clobber list */ \
+ ); \
+ CYG_MACRO_END
#endif
// Synchronize the contents of the cache with memory.
// (which includes flushing out pending writes)
#define HAL_ICACHE_SYNC()
#ifdef TODO
-#define HAL_ICACHE_SYNC() \
-CYG_MACRO_START \
- HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
- HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
-CYG_MACRO_END
+#define HAL_ICACHE_SYNC() \
+ CYG_MACRO_START \
+ HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
+ HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
+ CYG_MACRO_END
#endif
#ifdef L2CC_ENABLED
// Query the state of the L2 cache
-#define HAL_L2CACHE_IS_ENABLED(_state_) \
-CYG_MACRO_START \
- register int reg; \
- asm volatile ( \
- "nop; " \
- "nop; " \
- "nop; " \
- "nop; " \
- "mrc p15, 0, %0, c1, c0, 1;" \
- : "=r"(reg) \
- : \
- ); \
- (_state_) = (0 != (2 & reg)); /* Bit 1 is L2 Cache enable */ \
-CYG_MACRO_END
+#define HAL_L2CACHE_IS_ENABLED(_state_) \
+ CYG_MACRO_START \
+ register int reg; \
+ asm volatile ( \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "nop;" \
+ "mrc p15, 0, %0, c1, c0, 1;" \
+ : "=r"(reg) \
+ ); \
+ (_state_) = (0 != (2 & reg)); /* Bit 1 is L2 Cache enable */ \
+ CYG_MACRO_END
-#define HAL_ENABLE_L2() \
-{ \
- asm("mrc 15, 0, r0, c1, c0, 1"); \
- asm("orr r0, r0, #0x2"); \
- asm("mcr 15, 0, r0, c1, c0, 1"); \
-}
+#define HAL_ENABLE_L2() \
+ CYG_MACRO_START \
+ asm volatile( \
+ "mrc 15, 0, r0, c1, c0, 1;" \
+ "orr r0, r0, #0x2;" \
+ "mcr 15, 0, r0, c1, c0, 1;" \
+ : \
+ : \
+ : "r0" \
+ ); \
+ CYG_MACRO_END
-#define HAL_DISABLE_L2() \
-{ \
- asm("mrc 15, 0, r0, c1, c0, 1"); \
- asm("bic r0, r0, #0x2"); \
- asm("mcr 15, 0, r0, c1, c0, 1"); \
-}
+#define HAL_DISABLE_L2() \
+ CYG_MACRO_START \
+ asm volatile( \
+ "mrc 15, 0, r0, c1, c0, 1;" \
+ "bic r0, r0, #0x2;" \
+ "mcr 15, 0, r0, c1, c0, 1;" \
+ : \
+ : \
+ : "r0" \
+ ); \
+ CYG_MACRO_END
#else //L2CC_ENABLED
-#define HAL_ENABLE_L2()
-#define HAL_DISABLE_L2()
+#define HAL_ENABLE_L2() CYG_EMPTY_STATEMENT
+#define HAL_DISABLE_L2() CYG_EMPTY_STATEMENT
#endif //L2CC_ENABLED
/*********************** Exported macros *******************/
-#define HAL_DCACHE_ENABLE() { \
- HAL_ENABLE_L2(); \
- HAL_DCACHE_ENABLE_L1(); \
+#define HAL_DCACHE_ENABLE() { \
+ HAL_ENABLE_L2(); \
+ HAL_DCACHE_ENABLE_L1(); \
}
-#define HAL_DCACHE_DISABLE() { \
- HAL_CACHE_FLUSH_ALL(); \
- HAL_DCACHE_DISABLE_C1(); \
+#define HAL_DCACHE_DISABLE() { \
+ HAL_CACHE_FLUSH_ALL(); \
+ HAL_DCACHE_DISABLE_L1(); \
}
-#define HAL_DCACHE_INVALIDATE_ALL() { \
- HAL_CACHE_FLUSH_ALL(); \
+#define HAL_DCACHE_INVALIDATE_ALL() { \
+ HAL_CACHE_FLUSH_ALL(); \
}
// not needed
-#define HAL_DCACHE_SYNC()
+#define HAL_DCACHE_SYNC() \
+ HAL_CACHE_FLUSH_ALL(); \
-#define HAL_ICACHE_INVALIDATE_ALL() { \
- HAL_CACHE_FLUSH_ALL(); \
+#define HAL_ICACHE_INVALIDATE_ALL() { \
+ HAL_CACHE_FLUSH_ALL(); \
}
-#define HAL_ICACHE_DISABLE() { \
- HAL_ICACHE_DISABLE_L1(); \
+#define HAL_ICACHE_DISABLE() { \
+ HAL_ICACHE_DISABLE_L1(); \
}
-#define HAL_ICACHE_ENABLE() { \
- HAL_ICACHE_ENABLE_L1(); \
+#define HAL_ICACHE_ENABLE() { \
+ HAL_ICACHE_ENABLE_L1(); \
}
-#define CYGARC_HAL_MMU_OFF(__paddr__) \
- "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
- "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
- "bic r0, r0, #0x1000;" /* disable ICache */ \
- "mcr p15, 0, r0, c1, c0, 0;" /* */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */ \
- "nop;" /* flush i+d-TLBs */
+#define CYGARC_HAL_MMU_OFF(__paddr__) \
+ "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
+ "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
+ "bic r0, r0, #0x1000;" /* disable ICache */ \
+ "mcr p15, 0, r0, c1, c0, 0;" /* */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */ \
+ "nop;" /* flush i+d-TLBs */
-#define HAL_MMU_OFF() \
-CYG_MACRO_START \
- asm volatile ( \
- CYGARC_HAL_MMU_OFF() \
- ); \
-CYG_MACRO_END
+#define HAL_MMU_OFF() \
+ CYG_MACRO_START \
+ asm volatile ( \
+ CYGARC_HAL_MMU_OFF() \
+ ); \
+ CYG_MACRO_END
+
+#if 1
+/* There is no direct access to the flash area, thus there is no need for these macros */
+#define HAL_FLASH_CACHES_OFF(d,i) \
+ CYG_MACRO_START \
+ /* prevent 'unused variable' warnings */ \
+ (void)d; \
+ (void)i; \
+ CYG_MACRO_END
+
+#define HAL_FLASH_CACHES_ON(d,i) CYG_EMPTY_STATEMENT
+#endif
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/*
* Translation Table Base Bit Masks
*/
-#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
+#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
/*
* Domain Access Control Bit Masks
*/
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num) (0x0 << ((domain_num) * 2))
+#define ARM_ACCESS_TYPE_CLIENT(domain_num) (0x1 << ((domain_num) * 2))
+#define ARM_ACCESS_TYPE_MANAGER(domain_num) (0x3 << ((domain_num) * 2))
struct ARM_MMU_FIRST_LEVEL_FAULT {
- unsigned int id : 2;
- unsigned int sbz : 30;
+ unsigned int id : 2;
+ unsigned int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
- unsigned int id : 2;
- unsigned int imp : 2;
- unsigned int domain : 4;
- unsigned int sbz : 1;
- unsigned int base_address : 23;
+ unsigned int id : 2;
+ unsigned int imp : 2;
+ unsigned int domain : 4;
+ unsigned int sbz : 1;
+ unsigned int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
struct ARM_MMU_FIRST_LEVEL_SECTION {
- unsigned int id : 2;
- unsigned int b : 1;
- unsigned int c : 1;
- unsigned int imp : 1;
- unsigned int domain : 4;
- unsigned int sbz0 : 1;
- unsigned int ap : 2;
- unsigned int sbz1 : 8;
- unsigned int base_address : 12;
+ unsigned int id : 2;
+ unsigned int b : 1;
+ unsigned int c : 1;
+ unsigned int imp : 1;
+ unsigned int domain : 4;
+ unsigned int sbz0 : 1;
+ unsigned int ap : 2;
+ unsigned int sbz1 : 8;
+ unsigned int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
struct ARM_MMU_FIRST_LEVEL_RESERVED {
- unsigned int id : 2;
- unsigned int sbz : 30;
+ unsigned int id : 2;
+ unsigned int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
-#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
- (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+ ((unsigned long *)(ttb_base) + (table_index))
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
- cacheable, bufferable, perm) \
- CYG_MACRO_START \
- register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
- \
- desc.word = 0; \
- desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
- desc.section.domain = 0; \
- desc.section.c = (cacheable); \
- desc.section.b = (bufferable); \
- desc.section.ap = (perm); \
- desc.section.base_address = (actual_base); \
- *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
- = desc.word; \
- CYG_MACRO_END
-
-#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
- { \
- int i; int j = abase; int k = vbase; \
- for (i = size; i > 0 ; i--,j++,k++) { \
- ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
- } \
- }
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
+ cacheable, bufferable, perm) \
+ CYG_MACRO_START \
+ register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
+ \
+ desc.word = 0; \
+ desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
+ desc.section.domain = 0; \
+ desc.section.c = cacheable; \
+ desc.section.b = bufferable; \
+ desc.section.ap = perm; \
+ desc.section.base_address = actual_base; \
+ *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, virtual_base) = desc.word; \
+ CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
+ CYG_MACRO_START \
+ int i; int j = abase; int k = vbase; \
+ for (i = size; i > 0 ; i--, j++, k++) { \
+ ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
+ } \
+ CYG_MACRO_END
union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
- unsigned long word;
- struct ARM_MMU_FIRST_LEVEL_FAULT fault;
- struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
- struct ARM_MMU_FIRST_LEVEL_SECTION section;
- struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+ unsigned long word;
+ struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+ struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+ struct ARM_MMU_FIRST_LEVEL_SECTION section;
+ struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};
-#define ARM_UNCACHEABLE 0
-#define ARM_CACHEABLE 1
-#define ARM_UNBUFFERABLE 0
-#define ARM_BUFFERABLE 1
+#define ARM_UNCACHEABLE 0
+#define ARM_CACHEABLE 1
+#define ARM_UNBUFFERABLE 0
+#define ARM_BUFFERABLE 1
-#define ARM_ACCESS_PERM_NONE_NONE 0
-#define ARM_ACCESS_PERM_RO_NONE 0
-#define ARM_ACCESS_PERM_RO_RO 0
-#define ARM_ACCESS_PERM_RW_NONE 1
-#define ARM_ACCESS_PERM_RW_RO 2
-#define ARM_ACCESS_PERM_RW_RW 3
+#define ARM_ACCESS_PERM_NONE_NONE 0
+#define ARM_ACCESS_PERM_RO_NONE 0
+#define ARM_ACCESS_PERM_RO_RO 0
+#define ARM_ACCESS_PERM_RW_NONE 1
+#define ARM_ACCESS_PERM_RW_RO 2
+#define ARM_ACCESS_PERM_RW_RW 3
/*
* Initialization for the Domain Access Control Register
*/
-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15) )
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
// End of hal_mm.h
-
-
-
-
-
#define __HAL_SOC_H__
#ifdef __ASSEMBLER__
+#define UL(a) (a)
+#define VA(a) (a)
+#define REG8_VAL(a) (a)
+#define REG16_VAL(a) (a)
+#define REG32_VAL(a) (a)
-#define REG8_VAL(a) (a)
-#define REG16_VAL(a) (a)
-#define REG32_VAL(a) (a)
-
-#define REG8_PTR(a) (a)
-#define REG16_PTR(a) (a)
-#define REG32_PTR(a) (a)
+#define REG8_PTR(a) (a)
+#define REG16_PTR(a) (a)
+#define REG32_PTR(a) (a)
#else /* __ASSEMBLER__ */
-
-extern char HAL_PLATFORM_EXTRA[];
-#define REG8_VAL(a) ((unsigned char)(a))
-#define REG16_VAL(a) ((unsigned short)(a))
-#define REG32_VAL(a) ((unsigned int)(a))
-
-#define REG8_PTR(a) ((volatile unsigned char *)(a))
-#define REG16_PTR(a) ((volatile unsigned short *)(a))
-#define REG32_PTR(a) ((volatile unsigned int *)(a))
-#define readb(a) (*(volatile unsigned char *)(a))
-#define readw(a) (*(volatile unsigned short *)(a))
-#define readl(a) (*(volatile unsigned int *)(a))
-#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
-#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
+#define UL(a) (a##UL)
+#define VA(a) ((void *)(a))
+
+extern char HAL_PLATFORM_EXTRA[40];
+externC void plf_hardware_init(void);
+
+#define REG8_VAL(a) ((unsigned char)(a))
+#define REG16_VAL(a) ((unsigned short)(a))
+#define REG32_VAL(a) ((unsigned int)(a))
+
+#define REG8_PTR(a) ((volatile unsigned char *)(a))
+#define REG16_PTR(a) ((volatile unsigned short *)(a))
+#define REG32_PTR(a) ((volatile unsigned int *)(a))
+#define readb(a) (*(volatile unsigned char *)(a))
+#define readw(a) (*(volatile unsigned short *)(a))
+#define readl(a) (*(volatile unsigned int *)(a))
+#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
#endif /* __ASSEMBLER__ */
* Default Memory Layout Definitions
*/
+#define MXC_NAND_BASE_DUMMY 0
+
/*
* UART Chip level Configuration that a user may not have to edit. These
* configuration vary depending on how the UART module is integrated with
* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
* Certain platforms need this bit to be set in order to receive Irda data.
*/
-#define MXC_UART_IR_RXDMUX 0x0004
+#define MXC_UART_IR_RXDMUX 0x0004
/*!
* This option is used to set or clear the RXDMUXSEL bit in control reg 3.
* Certain platforms need this bit to be set in order to receive UART data.
*/
-#define MXC_UART_RXDMUX 0x0004
+#define MXC_UART_RXDMUX 0x0004
/*
* IRAM
*/
-#define IRAM_BASE_ADDR 0x1FFE8000 /* 96K internal ram */
+#define IRAM_BASE_ADDR UL(0x1FFE2000) /* 96K internal ram */
/*
* ROM address
*/
-#define ROM_BASE_ADDRESS 0x0
-#define ROM_BASE_ADDRESS_VIRT 0x20000000
+#define ROM_BASE_ADDR UL(0x00000000)
+#define ROM_BASE_ADDR_VIRT VA(0x20000000)
-#define ROM_SI_REV_OFFSET 0x48
+#define ROM_SI_REV_OFFSET 0x48
/*
* NFC internal RAM
*/
-#define NFC_BASE_ADDR_AXI 0xCFFF0000
-#define NFC_BASE NFC_BASE_ADDR_AXI
+#define NFC_BASE_ADDR_AXI UL(0xCFFF0000)
+#define NFC_BASE NFC_BASE_ADDR_AXI
-#define PLATFORM_BASE_ADDR 0x83FA0000
-#define PLATFORM_ICGC 0x14
+#define PLATFORM_BASE_ADDR UL(0x83FA0000)
+#define PLATFORM_ICGC 0x14
/*
* Graphics Memory of GPU
*/
-#define GPU_BASE_ADDR 0x20000000
+#define GPU_BASE_ADDR UL(0x20000000)
-#define TZIC_BASE_ADDR 0x8FFFC000
+#define TZIC_BASE_ADDR UL(0x8FFFC000)
-#define DEBUG_BASE_ADDR 0x60000000
+#define DEBUG_BASE_ADDR UL(0x60000000)
#define DEBUG_ROM_ADDR (DEBUG_BASE_ADDR + 0x0)
-#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
-#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
-#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
-#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
-#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
-#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
-#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
-#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
/*
* SPBA global module enabled #0
*/
-#define SPBA0_BASE_ADDR 0x70000000
+#define SPBA0_BASE_ADDR UL(0x70000000)
-#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
-#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
-#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define ESDHC1_REG_BASE MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
//eCSPI1
-#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
-#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
-#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
-#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
-#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
-#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
#define SLIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
#define HSI2C_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
-#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
/*!
* defines for SPBA modules
*/
-#define SPBA_SDHC1 0x04
-#define SPBA_SDHC2 0x08
-#define SPBA_UART3 0x0C
-#define SPBA_CSPI1 0x10
+#define SPBA_SDHC1 0x04
+#define SPBA_SDHC2 0x08
+#define SPBA_UART3 0x0C
+#define SPBA_CSPI1 0x10
#define SPBA_SSI2 0x14
-#define SPBA_SDHC3 0x20
-#define SPBA_SDHC4 0x24
-#define SPBA_SPDIF 0x28
+#define SPBA_SDHC3 0x20
+#define SPBA_SDHC4 0x24
+#define SPBA_SPDIF 0x28
#define SPBA_ATA 0x30
#define SPBA_SLIM 0x34
-#define SPBA_HSI2C 0x38
+#define SPBA_HSI2C 0x38
#define SPBA_CTRL 0x3C
/*
* AIPS 1
*/
-#define AIPS1_BASE_ADDR 0x73F00000
-#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
-#define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
-#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
-#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
-#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
-#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
-#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
-#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
-#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
-#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
-#define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
-#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
-#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
-#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
-#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
-#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
-#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
-#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
-#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
-#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+#define AIPS1_BASE_ADDR UL(0x73F00000)
+#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
+#define USBOH3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG_BASE_ADDR WDOG1_BASE_ADDR
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
/*
* AIPS 2
*/
-#define AIPS2_BASE_ADDR 0x83F00000
-#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
-#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
-#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
-#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
-#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
-#define MAX_BASE_ADDR AHBMAX_BASE_ADDR
-#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
-#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
-#define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
-#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+#define AIPS2_BASE_ADDR UL(0x83F00000)
+#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define MAX_BASE_ADDR AHBMAX_BASE_ADDR
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_ELBOW_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
// eCSPI2
-#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
-#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
-#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
-#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
-#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
// actually cspi1
-#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
-#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
-#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
-#define I2C_BASE_ADDR I2C1_BASE_ADDR
-#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
-#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
-#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
-#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
-#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
-#define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
-#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define I2C_BASE_ADDR I2C1_BASE_ADDR
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_IP_BASE (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
-#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
-#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
-#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
-#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
-#define SOC_FEC_BASE FEC_BASE_ADDR
-#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
-#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
-#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define SOC_FEC_BASE FEC_BASE_ADDR
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
/*
* Memory regions and CS
*/
-#define GPU_CTRL_BASE_ADDR 0x30000000
-#define IPU_CTRL_BASE_ADDR 0x40000000
-#define CSD0_BASE_ADDR 0x90000000
-#define CSD1_BASE_ADDR 0xA0000000
-#define CS0_BASE_ADDR 0xB0000000
-#define CS1_BASE_ADDR 0xB8000000
-#define CS2_BASE_ADDR 0xC0000000
-#define CS3_BASE_ADDR 0xC8000000
-#define CS4_BASE_ADDR 0xCC000000
-#define CS5_BASE_ADDR 0xCE000000
+#define GPU_CTRL_BASE_ADDR UL(0x30000000)
+#define IPU_CTRL_BASE_ADDR UL(0x40000000)
+#define CSD0_BASE_ADDR UL(0x90000000)
+#define CSD1_BASE_ADDR UL(0xA0000000)
+#define CS0_BASE_ADDR UL(0xB0000000)
+#define CS1_BASE_ADDR UL(0xB8000000)
+#define CS2_BASE_ADDR UL(0xC0000000)
+#define CS3_BASE_ADDR UL(0xC8000000)
+#define CS4_BASE_ADDR UL(0xCC000000)
+#define CS5_BASE_ADDR UL(0xCE000000)
/*
* DMA request assignments
*/
#define DMA_REQ_SSI3_TX1 47
#define DMA_REQ_SSI3_RX1 46
-#define DMA_REQ_SPDIF 45
+#define DMA_REQ_SPDIF 45
#define DMA_REQ_UART3_TX 44
#define DMA_REQ_UART3_RX 43
#define DMA_REQ_SLIM_B_TX 42
-#define DMA_REQ_SDHC4 41
-#define DMA_REQ_SDHC3 40
+#define DMA_REQ_SDHC4 41
+#define DMA_REQ_SDHC3 40
#define DMA_REQ_CSPI_TX 39
#define DMA_REQ_CSPI_RX 38
#define DMA_REQ_SSI3_TX2 37
-#define DMA_REQ_IPU 36
+#define DMA_REQ_IPU 36
#define DMA_REQ_SSI3_RX2 35
-#define DMA_REQ_EPIT2 34
+#define DMA_REQ_EPIT2 34
#define DMA_REQ_CTI2_1 33
#define DMA_REQ_EMI_WR 32
#define DMA_REQ_CTI2_0 31
#define DMA_REQ_SSI2_RX1 24
#define DMA_REQ_SSI2_TX2 23
#define DMA_REQ_SSI2_RX2 22
-#define DMA_REQ_SDHC2_I2C2 21
-#define DMA_REQ_SDHC1_I2C1 20
+#define DMA_REQ_SDHC2_I2C2 21
+#define DMA_REQ_SDHC1_I2C1 20
#define DMA_REQ_UART1_TX 19
#define DMA_REQ_UART1_RX 18
#define DMA_REQ_UART2_TX 17
#define DMA_REQ_UART2_RX 16
-#define DMA_REQ_GPU_GPIO1_0 15
+#define DMA_REQ_GPU_GPIO1_0 15
#define DMA_REQ_GPIO1_1 14
#define DMA_REQ_FIRI_TX 13
#define DMA_REQ_FIRI_RX 12
#define DMA_REQ_CSPI1_TX 7
#define DMA_REQ_CSPI1_RX 6
#define DMA_REQ_SLIM_B 5
-#define DMA_REQ_ATA_TX_END 4
+#define DMA_REQ_ATA_TX_END 4
#define DMA_REQ_ATA_TX 3
#define DMA_REQ_ATA_RX 2
-#define DMA_REQ_GPC 1
-#define DMA_REQ_VPU 0
+#define DMA_REQ_GPC 1
+#define DMA_REQ_VPU 0
/*
* Interrupt numbers
*/
-#define MXC_INT_BASE 0
-#define MXC_INT_RESV0 0
+#define MXC_INT_BASE 0
+#define MXC_INT_RESV0 0
#define MXC_INT_MMC_SDHC1 1
#define MXC_INT_MMC_SDHC2 2
#define MXC_INT_MMC_SDHC3 3
#define MXC_INT_MMC_SDHC4 4
-#define MXC_INT_RESV5 5
-#define MXC_INT_SDMA 6
-#define MXC_INT_IOMUX 7
-#define MXC_INT_NFC 8
-#define MXC_INT_VPU 9
+#define MXC_INT_RESV5 5
+#define MXC_INT_SDMA 6
+#define MXC_INT_IOMUX 7
+#define MXC_INT_NFC 8
+#define MXC_INT_VPU 9
#define MXC_INT_IPU_ERR 10
#define MXC_INT_IPU_SYN 11
-#define MXC_INT_GPU 12
+#define MXC_INT_GPU 12
#define MXC_INT_RESV13 13
#define MXC_INT_USB_H1 14
-#define MXC_INT_EMI 15
+#define MXC_INT_EMI 15
#define MXC_INT_USB_H2 16
#define MXC_INT_USB_H3 17
#define MXC_INT_USB_OTG 18
#define MXC_INT_SCC_SCM 23
#define MXC_INT_SRTC_NTZ 24
#define MXC_INT_SRTC_TZ 25
-#define MXC_INT_RTIC 26
-#define MXC_INT_CSU 27
+#define MXC_INT_RTIC 26
+#define MXC_INT_CSU 27
#define MXC_INT_SLIM_B 28
-#define MXC_INT_SSI1 29
-#define MXC_INT_SSI2 30
-#define MXC_INT_UART1 31
-#define MXC_INT_UART2 32
-#define MXC_INT_UART3 33
+#define MXC_INT_SSI1 29
+#define MXC_INT_SSI2 30
+#define MXC_INT_UART1 31
+#define MXC_INT_UART2 32
+#define MXC_INT_UART3 33
#define MXC_INT_RESV34 34
#define MXC_INT_RESV35 35
-#define MXC_INT_CSPI1 36
-#define MXC_INT_CSPI2 37
-#define MXC_INT_CSPI 38
-#define MXC_INT_GPT 39
-#define MXC_INT_EPIT1 40
-#define MXC_INT_EPIT2 41
-#define MXC_INT_GPIO1_INT7 42
-#define MXC_INT_GPIO1_INT6 43
-#define MXC_INT_GPIO1_INT5 44
-#define MXC_INT_GPIO1_INT4 45
-#define MXC_INT_GPIO1_INT3 46
-#define MXC_INT_GPIO1_INT2 47
-#define MXC_INT_GPIO1_INT1 48
-#define MXC_INT_GPIO1_INT0 49
+#define MXC_INT_CSPI1 36
+#define MXC_INT_CSPI2 37
+#define MXC_INT_CSPI 38
+#define MXC_INT_GPT 39
+#define MXC_INT_EPIT1 40
+#define MXC_INT_EPIT2 41
+#define MXC_INT_GPIO1_INT7 42
+#define MXC_INT_GPIO1_INT6 43
+#define MXC_INT_GPIO1_INT5 44
+#define MXC_INT_GPIO1_INT4 45
+#define MXC_INT_GPIO1_INT3 46
+#define MXC_INT_GPIO1_INT2 47
+#define MXC_INT_GPIO1_INT1 48
+#define MXC_INT_GPIO1_INT0 49
#define MXC_INT_GPIO1_LOW 50
-#define MXC_INT_GPIO1_HIGH 51
+#define MXC_INT_GPIO1_HIGH 51
#define MXC_INT_GPIO2_LOW 52
-#define MXC_INT_GPIO2_HIGH 53
+#define MXC_INT_GPIO2_HIGH 53
#define MXC_INT_GPIO3_LOW 54
-#define MXC_INT_GPIO3_HIGH 55
+#define MXC_INT_GPIO3_HIGH 55
#define MXC_INT_GPIO4_LOW 56
-#define MXC_INT_GPIO4_HIGH 57
-#define MXC_INT_WDOG1 58
-#define MXC_INT_WDOG2 59
-#define MXC_INT_KPP 60
-#define MXC_INT_PWM1 61
-#define MXC_INT_I2C1 62
-#define MXC_INT_I2C2 63
+#define MXC_INT_GPIO4_HIGH 57
+#define MXC_INT_WDOG1 58
+#define MXC_INT_WDOG2 59
+#define MXC_INT_KPP 60
+#define MXC_INT_PWM1 61
+#define MXC_INT_I2C1 62
+#define MXC_INT_I2C2 63
#define MXC_INT_HS_I2C 64
#define MXC_INT_RESV65 65
#define MXC_INT_RESV66 66
#define MXC_INT_SIM_IPB 67
#define MXC_INT_SIM_DAT 68
-#define MXC_INT_IIM 69
-#define MXC_INT_ATA 70
-#define MXC_INT_CCM1 71
-#define MXC_INT_CCM2 72
-#define MXC_INT_GPC1 73
-#define MXC_INT_GPC2 74
-#define MXC_INT_SRC 75
-#define MXC_INT_NM 76
-#define MXC_INT_PMU 77
+#define MXC_INT_IIM 69
+#define MXC_INT_ATA 70
+#define MXC_INT_CCM1 71
+#define MXC_INT_CCM2 72
+#define MXC_INT_GPC1 73
+#define MXC_INT_GPC2 74
+#define MXC_INT_SRC 75
+#define MXC_INT_NM 76
+#define MXC_INT_PMU 77
#define MXC_INT_CTI_IRQ 78
#define MXC_INT_CTI1_TG0 79
#define MXC_INT_CTI1_TG1 80
#define MXC_INT_RESV84 84
#define MXC_INT_RESV85 85
#define MXC_INT_RESV86 86
-#define MXC_INT_FEC 87
-#define MXC_INT_OWIRE 88
+#define MXC_INT_FEC 87
+#define MXC_INT_OWIRE 88
#define MXC_INT_CTI1_TG2 89
-#define MXC_INT_SJC 90
-#define MXC_INT_SPDIF 91
-#define MXC_INT_TVE 92
-#define MXC_INT_FIFI 93
-#define MXC_INT_PWM2 94
+#define MXC_INT_SJC 90
+#define MXC_INT_SPDIF 91
+#define MXC_INT_TVE 92
+#define MXC_INT_FIFI 93
+#define MXC_INT_PWM2 94
#define MXC_INT_SLIM_EXP 95
-#define MXC_INT_SSI3 96
+#define MXC_INT_SSI3 96
#define MXC_INT_RESV97 97
#define MXC_INT_CTI1_TG3 98
#define MXC_INT_SMC_RX 99
/*!
* Number of GPIO port as defined in the IC Spec
*/
-#define GPIO_PORT_NUM 4
+#define GPIO_PORT_NUM 4
/*!
* Number of GPIO pins per port
*/
-#define GPIO_NUM_PIN 32
+#define GPIO_NUM_PIN 32
/* CCM */
-#define CLKCTL_CCR 0x00
-#define CLKCTL_CCDR 0x04
-#define CLKCTL_CSR 0x08
-#define CLKCTL_CCSR 0x0C
-#define CLKCTL_CACRR 0x10
-#define CLKCTL_CBCDR 0x14
-#define CLKCTL_CBCMR 0x18
-#define CLKCTL_CSCMR1 0x1C
-#define CLKCTL_CSCMR2 0x20
-#define CLKCTL_CSCDR1 0x24
-#define CLKCTL_CS1CDR 0x28
-#define CLKCTL_CS2CDR 0x2C
-#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCCDR 0x34
-#define CLKCTL_CSCDR2 0x38
-#define CLKCTL_CSCDR3 0x3C
-#define CLKCTL_CSCDR4 0x40
-#define CLKCTL_CWDR 0x44
-#define CLKCTL_CDHIPR 0x48
-#define CLKCTL_CDCR 0x4C
-#define CLKCTL_CTOR 0x50
-#define CLKCTL_CLPCR 0x54
-#define CLKCTL_CISR 0x58
-#define CLKCTL_CIMR 0x5C
-#define CLKCTL_CCOSR 0x60
-#define CLKCTL_CGPR 0x64
-#define CLKCTL_CCGR0 0x68
-#define CLKCTL_CCGR1 0x6C
-#define CLKCTL_CCGR2 0x70
-#define CLKCTL_CCGR3 0x74
-#define CLKCTL_CCGR4 0x78
-#define CLKCTL_CCGR5 0x7C
-#define CLKCTL_CMEOR 0x84
-
-#define FREQ_24MHZ 24000000
-#define FREQ_32768HZ (32768 * 1024)
-#define FREQ_38400HZ (38400 * 1024)
-#define FREQ_32000HZ (32000 * 1024)
-#define PLL_REF_CLK FREQ_24MHZ
-#define CKIH 22579200
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CMEOR 0x84
+
+#define FREQ_24MHZ 24000000
+#define FREQ_32768HZ (32768 * 1024)
+#define FREQ_38400HZ (38400 * 1024)
+#define FREQ_32000HZ (32000 * 1024)
+#define PLL_REF_CLK FREQ_24MHZ
+#define CKIH 22579200
//#define PLL_REF_CLK FREQ_32768HZ
//#define PLL_REF_CLK FREQ_32000HZ
/* WEIM registers */
-#define CSGCR1 0x00
-#define CSGCR2 0x04
-#define CSRCR1 0x08
-#define CSRCR2 0x0C
-#define CSWCR1 0x10
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
/* M4IF */
-#define M4IF_FBPM0 0x40
-#define M4IF_FIDBP 0x48
-#define M4IF_MIF4 0x48
+#define M4IF_FBPM0 0x40
+#define M4IF_FBPM1 0x44
+#define M4IF_FIDBP 0x48
+#define M4IF_MIF4 0x48
+#define M4IF_FPWC 0x9C
/* ESDCTL */
-#define ESDCTL_ESDCTL0 0x00
-#define ESDCTL_ESDCFG0 0x04
-#define ESDCTL_ESDCTL1 0x08
-#define ESDCTL_ESDCFG1 0x0C
-#define ESDCTL_ESDMISC 0x10
-#define ESDCTL_ESDSCR 0x14
-#define ESDCTL_ESDCDLY1 0x20
-#define ESDCTL_ESDCDLY2 0x24
-#define ESDCTL_ESDCDLY3 0x28
-#define ESDCTL_ESDCDLY4 0x2C
-#define ESDCTL_ESDCDLY5 0x30
-#define ESDCTL_ESDCDLYGD 0x34
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
/* DPLL */
-#define PLL_DP_CTL 0x00
-#define PLL_DP_CONFIG 0x04
-#define PLL_DP_OP 0x08
-#define PLL_DP_MFD 0x0C
-#define PLL_DP_MFN 0x10
-#define PLL_DP_MFNMINUS 0x14
-#define PLL_DP_MFNPLUS 0x18
-#define PLL_DP_HFS_OP 0x1C
-#define PLL_DP_HFS_MFD 0x20
-#define PLL_DP_HFS_MFN 0x24
-#define PLL_DP_TOGC 0x28
-#define PLL_DP_DESTAT 0x2C
-
-#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
-#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
-#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
-#define CHIP_LATEST CHIP_REV_1_1
-
-#define IIM_STAT_OFF 0x00
-#define IIM_STAT_BUSY (1 << 7)
-#define IIM_STAT_PRGD (1 << 1)
-#define IIM_STAT_SNSD (1 << 0)
-#define IIM_STATM_OFF 0x04
-#define IIM_ERR_OFF 0x08
-#define IIM_ERR_PRGE (1 << 7)
-#define IIM_ERR_WPE (1 << 6)
-#define IIM_ERR_OPE (1 << 5)
-#define IIM_ERR_RPE (1 << 4)
-#define IIM_ERR_WLRE (1 << 3)
-#define IIM_ERR_SNSE (1 << 2)
-#define IIM_ERR_PARITYE (1 << 1)
-#define IIM_EMASK_OFF 0x0C
-#define IIM_FCTL_OFF 0x10
-#define IIM_UA_OFF 0x14
-#define IIM_LA_OFF 0x18
-#define IIM_SDAT_OFF 0x1C
-#define IIM_PREV_OFF 0x20
-#define IIM_SREV_OFF 0x24
-#define IIM_PREG_P_OFF 0x28
-#define IIM_SCS0_OFF 0x2C
-#define IIM_SCS1_P_OFF 0x30
-#define IIM_SCS2_OFF 0x34
-#define IIM_SCS3_P_OFF 0x38
-
-#define IIM_PROD_REV_SH 3
-#define IIM_PROD_REV_LEN 5
-#define IIM_SREV_REV_SH 4
-#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX51 0x1
-
-#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
-#define EPITCR 0x00
-#define EPITSR 0x04
-#define EPITLR 0x08
-#define EPITCMPR 0x0C
-#define EPITCNR 0x10
-
-#define GPTCR 0x00
-#define GPTPR 0x04
-#define GPTSR 0x08
-#define GPTIR 0x0C
-#define GPTOCR1 0x10
-#define GPTOCR2 0x14
-#define GPTOCR3 0x18
-#define GPTICR1 0x1C
-#define GPTICR2 0x20
-#define GPTCNT 0x24
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+#define CHIP_REV_1_0 0x0 /* PASS 1.0 */
+#define CHIP_REV_1_1 0x1 /* PASS 1.1 */
+#define CHIP_REV_2_0 0x2 /* PASS 2.0 */
+#define CHIP_LATEST CHIP_REV_1_1
+
+#define IIM_STAT_OFF 0x00
+#define IIM_STAT_BUSY (1 << 7)
+#define IIM_STAT_PRGD (1 << 1)
+#define IIM_STAT_SNSD (1 << 0)
+#define IIM_STATM_OFF 0x04
+#define IIM_ERR_OFF 0x08
+#define IIM_ERR_PRGE (1 << 7)
+#define IIM_ERR_WPE (1 << 6)
+#define IIM_ERR_OPE (1 << 5)
+#define IIM_ERR_RPE (1 << 4)
+#define IIM_ERR_WLRE (1 << 3)
+#define IIM_ERR_SNSE (1 << 2)
+#define IIM_ERR_PARITYE (1 << 1)
+#define IIM_EMASK_OFF 0x0C
+#define IIM_FCTL_OFF 0x10
+#define IIM_UA_OFF 0x14
+#define IIM_LA_OFF 0x18
+#define IIM_SDAT_OFF 0x1C
+#define IIM_PREV_OFF 0x20
+#define IIM_SREV_OFF 0x24
+#define IIM_PREG_P_OFF 0x28
+#define IIM_SCS0_OFF 0x2C
+#define IIM_SCS1_P_OFF 0x30
+#define IIM_SCS2_OFF 0x34
+#define IIM_SCS3_P_OFF 0x38
+
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX51 0x1
+
+#define EPIT_BASE_ADDR EPIT1_BASE_ADDR
+#define EPITCR 0x00
+#define EPITSR 0x04
+#define EPITLR 0x08
+#define EPITCMPR 0x0C
+#define EPITCNR 0x10
+
+#define GPTCR 0x00
+#define GPTPR 0x04
+#define GPTSR 0x08
+#define GPTIR 0x0C
+#define GPTOCR1 0x10
+#define GPTOCR2 0x14
+#define GPTOCR3 0x18
+#define GPTICR1 0x1C
+#define GPTICR2 0x20
+#define GPTCNT 0x24
/* Assuming 24MHz input clock with doubler ON */
-/* MFI PDF */
-#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_850 (48 - 1)
-#define DP_MFN_850 41
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
-#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
-#define DP_MFD_800 (3 - 1)
-#define DP_MFN_800 1
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
-#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
-#define DP_MFD_700 (24 - 1)
-#define DP_MFN_700 7
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
-#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
-#define DP_MFD_400 (3 - 1)
-#define DP_MFN_400 1
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
-#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
-#define DP_MFD_532 (24 - 1)
-#define DP_MFN_532 13
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
-#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
-#define DP_MFD_665 (96 - 1)
-#define DP_MFN_665 89
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
-#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
-#define DP_MFD_216 (4 - 1)
-#define DP_MFN_216 3
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX51
-#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
-#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
-
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
-
-/* IOMUX defines */
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x108) // 0x108
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x10C) // 0x10c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x110) // 0x110
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x114) // 0x114
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x118) // 0x118
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x11C) // 0x11c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x120) // 0x120
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x124) // 0x124
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x128) // 0x128
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x12C) // 0x12c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x130) // 0x130
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x134) // 0x134
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x138) // 0x138
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x13C) // 0x13c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x140) // 0x140
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x144) // 0x144
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x148) // 0x148
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x14C) // 0x14c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x150) // 0x150
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x154) // 0x154
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x158) // 0x158
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x15C) // 0x15c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x160) // 0x160
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x164) // 0x164
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x168) // 0x168
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x16C) // 0x16c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x170) // 0x170
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x174) // 0x174
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x178) // 0x178
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x17C) // 0x17c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x180) // 0x180
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x184) // 0x184
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x188) // 0x188
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x18C) // 0x18c
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x190) // 0x190
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x194) // 0x194
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x198) // 0x198
-#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x19C) // 0x19c
-
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (IOMUXC_BASE_ADDR + 0x5B0) // 0x5b0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (IOMUXC_BASE_ADDR + 0x5B4) // 0x5b4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (IOMUXC_BASE_ADDR + 0x5B8) // 0x5b8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (IOMUXC_BASE_ADDR + 0x5BC) // 0x5bc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (IOMUXC_BASE_ADDR + 0x5C0) // 0x5c0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (IOMUXC_BASE_ADDR + 0x5C4) // 0x5c4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (IOMUXC_BASE_ADDR + 0x5C8) // 0x5c8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (IOMUXC_BASE_ADDR + 0x5CC) // 0x5cc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (IOMUXC_BASE_ADDR + 0x5D0) // 0x5d0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB4 (IOMUXC_BASE_ADDR + 0x5D4) // 0x5d4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5 (IOMUXC_BASE_ADDR + 0x5D8) // 0x5d8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB6 (IOMUXC_BASE_ADDR + 0x5DC) // 0x5dc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB7 (IOMUXC_BASE_ADDR + 0x5E0) // 0x5e0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (IOMUXC_BASE_ADDR + 0x5E4) // 0x5e4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (IOMUXC_BASE_ADDR + 0x5E8) // 0x5e8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (IOMUXC_BASE_ADDR + 0x5EC) // 0x5ec
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (IOMUXC_BASE_ADDR + 0x5F0) // 0x5f0
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (IOMUXC_BASE_ADDR + 0x5F4) // 0x5f4
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (IOMUXC_BASE_ADDR + 0x5F8) // 0x5f8
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (IOMUXC_BASE_ADDR + 0x5FC) // 0x5fc
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (IOMUXC_BASE_ADDR + 0x600) // 0x600
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (IOMUXC_BASE_ADDR + 0x604) // 0x604
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (IOMUXC_BASE_ADDR + 0x608) // 0x608
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (IOMUXC_BASE_ADDR + 0x60C) // 0x60c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (IOMUXC_BASE_ADDR + 0x610) // 0x610
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (IOMUXC_BASE_ADDR + 0x614) // 0x614
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (IOMUXC_BASE_ADDR + 0x618) // 0x618
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (IOMUXC_BASE_ADDR + 0x61C) // 0x61c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (IOMUXC_BASE_ADDR + 0x620) // 0x620
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (IOMUXC_BASE_ADDR + 0x624) // 0x624
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (IOMUXC_BASE_ADDR + 0x628) // 0x628
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (IOMUXC_BASE_ADDR + 0x62C) // 0x62c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (IOMUXC_BASE_ADDR + 0x630) // 0x630
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (IOMUXC_BASE_ADDR + 0x634) // 0x634
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (IOMUXC_BASE_ADDR + 0x638) // 0x638
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (IOMUXC_BASE_ADDR + 0x63C) // 0x63c
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (IOMUXC_BASE_ADDR + 0x640) // 0x640
-#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (IOMUXC_BASE_ADDR + 0x644) // 0x644
-
-
-//#define BARKER_CODE_SWAP_LOC 0x404
-#define BARKER_CODE_VAL 0xB1
-#define NFC_V3_0 0x30
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+
+#define PART_NUMBER_OFFSET 12
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
+
+//#define BARKER_CODE_SWAP_LOC 0x404
+#define BARKER_CODE_VAL 0xB1
+#define NFC_V3_0
+
// This defines the register base for the NAND AXI registers
-#define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
-
-#define NAND_CMD_REG (NAND_REG_BASE + 0x00)
-#define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
-#define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
-#define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
-#define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
-#define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
-#define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
-#define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
-#define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
-#define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
-#define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
-#define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
-#define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
-
-#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
-#define NAND_CONFIGURATION1_NFC_RST (1 << 2)
-#define NAND_CONFIGURATION1_NF_CE (1 << 1)
-#define NAND_CONFIGURATION1_SP_EN (1 << 0)
-
-#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
-
-#define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
-
-#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
-#define NAND_LAUNCH_FCMD (1 << 0)
-#define NAND_LAUNCH_FADD (1 << 1)
-#define NAND_LAUNCH_FDI (1 << 2)
-#define NAND_LAUNCH_AUTO_PROG (1 << 6)
-#define NAND_LAUNCH_AUTO_READ (1 << 7)
-#define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
-#define NAND_LAUNCH_AUTO_ERASE (1 << 9)
-#define NAND_LAUNCH_COPY_BACK0 (1 << 10)
-#define NAND_LAUNCH_COPY_BACK1 (1 << 11)
-#define NAND_LAUNCH_AUTO_STAT (1 << 12)
-
-#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
-#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
-#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
-#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
-#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
-#define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
-#define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
-#define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
-#define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
-
-#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
-#define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
-
-#define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
-
-#define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
-#define NFC_IPC_INT (1 << 31)
-#define NFC_IPC_AUTO_DONE (1 << 30)
-#define NFC_IPC_LPS (1 << 29)
-#define NFC_IPC_RB_B (1 << 28)
-#define NFC_IPC_CACK (1 << 1)
-#define NFC_IPC_CREQ (1 << 0)
-#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
-
-#define MXC_MMC_BASE_DUMMY 0x00000000
-
-#define NAND_FLASH_BOOT 0x10000000
-#define FROM_NAND_FLASH NAND_FLASH_BOOT
-
-#define SDRAM_NON_FLASH_BOOT 0x20000000
-
-#define MMC_FLASH_BOOT 0x40000000
-#define FROM_MMC_FLASH MMC_FLASH_BOOT
-
-#define SPI_NOR_FLASH_BOOT 0x80000000
-#define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
-
-#define IS_BOOTING_FROM_NAND() (0)
-#define IS_BOOTING_FROM_SPI_NOR() (0)
-#define IS_BOOTING_FROM_NOR() (0)
-#define IS_BOOTING_FROM_SDRAM() (0)
-#define IS_BOOTING_FROM_MMC() (0)
+#define NAND_REG_BASE (NFC_BASE_ADDR_AXI + 0x1E00)
+
+#define NAND_CMD_REG (NAND_REG_BASE + 0x00)
+#define NAND_ADD0_REG (NAND_REG_BASE + 0x04)
+#define NAND_ADD1_REG (NAND_REG_BASE + 0x08)
+#define NAND_ADD2_REG (NAND_REG_BASE + 0x0C)
+#define NAND_ADD3_REG (NAND_REG_BASE + 0x10)
+#define NAND_ADD4_REG (NAND_REG_BASE + 0x14)
+#define NAND_ADD5_REG (NAND_REG_BASE + 0x18)
+#define NAND_ADD6_REG (NAND_REG_BASE + 0x1C)
+#define NAND_ADD7_REG (NAND_REG_BASE + 0x20)
+#define NAND_ADD8_REG (NAND_REG_BASE + 0x24)
+#define NAND_ADD9_REG (NAND_REG_BASE + 0x28)
+#define NAND_ADD10_REG (NAND_REG_BASE + 0x2C)
+#define NAND_ADD11_REG (NAND_REG_BASE + 0x30)
+
+#define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x34)
+#define NAND_CONFIGURATION1_NFC_RST (1 << 2)
+#define NAND_CONFIGURATION1_NF_CE (1 << 1)
+#define NAND_CONFIGURATION1_SP_EN (1 << 0)
+
+#define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x38)
+
+#define NAND_STATUS_SUM_REG (NAND_REG_BASE + 0x3C)
+
+#define NAND_LAUNCH_REG (NAND_REG_BASE + 0x40)
+#define NAND_LAUNCH_FCMD (1 << 0)
+#define NAND_LAUNCH_FADD (1 << 1)
+#define NAND_LAUNCH_FDI (1 << 2)
+#define NAND_LAUNCH_AUTO_PROG (1 << 6)
+#define NAND_LAUNCH_AUTO_READ (1 << 7)
+#define NAND_LAUNCH_AUTO_READ_CONT (1 << 8)
+#define NAND_LAUNCH_AUTO_ERASE (1 << 9)
+#define NAND_LAUNCH_COPY_BACK0 (1 << 10)
+#define NAND_LAUNCH_COPY_BACK1 (1 << 11)
+#define NAND_LAUNCH_AUTO_STAT (1 << 12)
+
+#define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
+#define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
+#define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
+#define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
+#define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
+#define UNLOCK_BLK_ADD4_REG (NFC_IP_BASE + 0x14)
+#define UNLOCK_BLK_ADD5_REG (NFC_IP_BASE + 0x18)
+#define UNLOCK_BLK_ADD6_REG (NFC_IP_BASE + 0x1C)
+#define UNLOCK_BLK_ADD7_REG (NFC_IP_BASE + 0x20)
+
+#define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x24)
+#define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
+
+#define NFC_FLASH_CONFIG3_REG (NFC_IP_BASE + 0x28)
+
+#define NFC_IPC_REG (NFC_IP_BASE + 0x2C)
+#define NFC_IPC_INT (1 << 31)
+#define NFC_IPC_AUTO_DONE (1 << 30)
+#define NFC_IPC_LPS (1 << 29)
+#define NFC_IPC_RB_B (1 << 28)
+#define NFC_IPC_CACK (1 << 1)
+#define NFC_IPC_CREQ (1 << 0)
+#define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x30)
+
+#define MXC_MMC_BASE_DUMMY 0x00000000
+
+#define NAND_FLASH_BOOT 0x10000000
+#define FROM_NAND_FLASH NAND_FLASH_BOOT
+
+#define SDRAM_NON_FLASH_BOOT 0x20000000
+
+#define MMC_FLASH_BOOT 0x40000000
+#define FROM_MMC_FLASH MMC_FLASH_BOOT
+
+#define SPI_NOR_FLASH_BOOT 0x80000000
+#define FROM_SPI_NOR_FLASH SPI_NOR_FLASH_BOOT
+
+#define IS_BOOTING_FROM_NAND() 0
+#define IS_BOOTING_FROM_SPI_NOR() 0
+#define IS_BOOTING_FROM_NOR() 0
+#define IS_BOOTING_FROM_SDRAM() 0
+#define IS_BOOTING_FROM_MMC() 0
#ifndef MXCFLASH_SELECT_NAND
-#define IS_FIS_FROM_NAND() 0
+#define IS_FIS_FROM_NAND() 0
#else
-#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
+#define IS_FIS_FROM_NAND() (_mxc_fis == FROM_NAND_FLASH)
#endif
#ifndef MXCFLASH_SELECT_MMC
-#define IS_FIS_FROM_MMC() 0
+#define IS_FIS_FROM_MMC() 0
#else
-#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
+#define IS_FIS_FROM_MMC() (_mxc_fis == FROM_MMC_FLASH)
#endif
-#define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH)
+#define IS_FIS_FROM_SPI_NOR() (_mxc_fis == FROM_SPI_NOR_FLASH)
+
+#define IS_FIS_FROM_NOR() 0
-#define IS_FIS_FROM_NOR() 0
+#define SOC_MAC_ADDR_FUSE_BANK 1
+#define SOC_MAC_ADDR_FUSE 9
+#define SOC_MAC_ADDR_LOCK_FUSE 0
+#define SOC_MAC_ADDR_LOCK_BIT 4
/*
* This macro is used to get certain bit field from a number
*/
-#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
+#define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
/*
* This macro is used to set certain bit field inside a number
*/
-#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+#define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
#define L2CC_ENABLED
-#define UART_WIDTH_32 /* internal UART is 32bit access only */
+#define UART_WIDTH_32 /* internal UART is 32bit access only */
#if !defined(__ASSEMBLER__)
+extern int fuse_blow(int bank, int row, int bit);
+
void cyg_hal_plf_serial_init(void);
void cyg_hal_plf_serial_stop(void);
void hal_delay_us(unsigned int usecs);
-#define HAL_DELAY_US(n) hal_delay_us(n)
+#define HAL_DELAY_US(n) hal_delay_us(n)
extern int _mxc_fis;
extern unsigned int system_rev;
enum plls {
- PLL1,
- PLL2,
- PLL3,
+ PLL1,
+ PLL2,
+ PLL3,
};
enum main_clocks {
- CPU_CLK,
- AHB_CLK,
- IPG_CLK,
- IPG_PER_CLK,
- DDR_CLK,
- NFC_CLK,
- USB_CLK,
+ CPU_CLK,
+ AHB_CLK,
+ IPG_CLK,
+ IPG_PER_CLK,
+ DDR_CLK,
+ NFC_CLK,
+ USB_CLK,
};
enum peri_clocks {
- UART1_BAUD,
- UART2_BAUD,
- UART3_BAUD,
- SSI1_BAUD,
- SSI2_BAUD,
- CSI_BAUD,
- MSTICK1_CLK,
- MSTICK2_CLK,
- SPI1_CLK = CSPI1_BASE_ADDR,
- SPI2_CLK = CSPI2_BASE_ADDR,
+ UART1_BAUD,
+ UART2_BAUD,
+ UART3_BAUD,
+ SSI1_BAUD,
+ SSI2_BAUD,
+ CSI_BAUD,
+ MSTICK1_CLK,
+ MSTICK2_CLK,
+ SPI1_CLK = CSPI1_BASE_ADDR,
+ SPI2_CLK = CSPI2_BASE_ADDR,
};
-unsigned int pll_clock(enum plls pll);
+extern unsigned int pll_clock(enum plls pll);
-unsigned int get_main_clock(enum main_clocks clk);
+extern unsigned int get_main_clock(enum main_clocks clk);
-unsigned int get_peri_clock(enum peri_clocks clk);
+extern unsigned int get_peri_clock(enum peri_clocks clk);
typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+extern void increase_core_voltage(bool);
+
#endif //#if !defined(__ASSEMBLER__)
#endif /* __HAL_SOC_H__ */
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
-#include <cyg/hal/hal_soc.h> // registers
+#include <cyg/hal/hal_soc.h> // registers
-#define CYGNUM_HAL_INTERRUPT_GPIO0 0
-#define CYGNUM_HAL_INTERRUPT_GPIO1 1
-#define CYGNUM_HAL_INTERRUPT_GPIO2 2
-#define CYGNUM_HAL_INTERRUPT_GPIO3 3
-#define CYGNUM_HAL_INTERRUPT_GPIO4 4
-#define CYGNUM_HAL_INTERRUPT_GPIO5 5
-#define CYGNUM_HAL_INTERRUPT_GPIO6 6
-#define CYGNUM_HAL_INTERRUPT_GPIO7 7
-#define CYGNUM_HAL_INTERRUPT_GPIO8 8
-#define CYGNUM_HAL_INTERRUPT_GPIO9 9
-#define CYGNUM_HAL_INTERRUPT_GPIO10 10
-#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
-#define CYGNUM_HAL_INTERRUPT_LCD 12
-#define CYGNUM_HAL_INTERRUPT_UDC 13
-#define CYGNUM_HAL_INTERRUPT_UART1 15
-#define CYGNUM_HAL_INTERRUPT_UART2 16
-#define CYGNUM_HAL_INTERRUPT_UART3 17
-#define CYGNUM_HAL_INTERRUPT_UART4 17
-#define CYGNUM_HAL_INTERRUPT_MCP 18
-#define CYGNUM_HAL_INTERRUPT_SSP 19
-#define CYGNUM_HAL_INTERRUPT_TIMER0 26
-#define CYGNUM_HAL_INTERRUPT_TIMER1 27
-#define CYGNUM_HAL_INTERRUPT_TIMER2 28
-#define CYGNUM_HAL_INTERRUPT_TIMER3 29
-#define CYGNUM_HAL_INTERRUPT_HZ 30
-#define CYGNUM_HAL_INTERRUPT_ALARM 31
+#define CYGNUM_HAL_INTERRUPT_GPIO0 0
+#define CYGNUM_HAL_INTERRUPT_GPIO1 1
+#define CYGNUM_HAL_INTERRUPT_GPIO2 2
+#define CYGNUM_HAL_INTERRUPT_GPIO3 3
+#define CYGNUM_HAL_INTERRUPT_GPIO4 4
+#define CYGNUM_HAL_INTERRUPT_GPIO5 5
+#define CYGNUM_HAL_INTERRUPT_GPIO6 6
+#define CYGNUM_HAL_INTERRUPT_GPIO7 7
+#define CYGNUM_HAL_INTERRUPT_GPIO8 8
+#define CYGNUM_HAL_INTERRUPT_GPIO9 9
+#define CYGNUM_HAL_INTERRUPT_GPIO10 10
+#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD 12
+#define CYGNUM_HAL_INTERRUPT_UDC 13
+#define CYGNUM_HAL_INTERRUPT_UART1 15
+#define CYGNUM_HAL_INTERRUPT_UART2 16
+#define CYGNUM_HAL_INTERRUPT_UART3 17
+#define CYGNUM_HAL_INTERRUPT_UART4 17
+#define CYGNUM_HAL_INTERRUPT_MCP 18
+#define CYGNUM_HAL_INTERRUPT_SSP 19
+#define CYGNUM_HAL_INTERRUPT_TIMER0 26
+#define CYGNUM_HAL_INTERRUPT_TIMER1 27
+#define CYGNUM_HAL_INTERRUPT_TIMER2 28
+#define CYGNUM_HAL_INTERRUPT_TIMER3 29
+#define CYGNUM_HAL_INTERRUPT_HZ 30
+#define CYGNUM_HAL_INTERRUPT_ALARM 31
// GPIO bits 31..11 can generate interrupts as well, but they all
// end up clumped into interrupt signal #11. Using the symbols
// below allow for detection of these separately.
-#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
-#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
-#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
-#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
-#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
-#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
-#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
-#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
-#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
-#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
-#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
-#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
-#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
-#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
-#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
-#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
-#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
+#define CYGNUM_HAL_INTERRUPT_GPIO11 (32 + 11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12 (32 + 12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13 (32 + 13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14 (32 + 14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15 (32 + 15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16 (32 + 16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17 (32 + 17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18 (32 + 18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19 (32 + 19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20 (32 + 20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21 (32 + 21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22 (32 + 22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23 (32 + 23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24 (32 + 24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25 (32 + 25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26 (32 + 26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27 (32 + 27)
-#define CYGNUM_HAL_INTERRUPT_NONE -1
+#define CYGNUM_HAL_INTERRUPT_NONE -1
-#define CYGNUM_HAL_ISR_MIN 0
-#define CYGNUM_HAL_ISR_MAX (27+32)
+#define CYGNUM_HAL_ISR_MIN 0
+#define CYGNUM_HAL_ISR_MAX (27 + 32)
-#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
+#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
// The vector used by the Real time clock
-#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
+#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
// The vector used by the Ethernet
-#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
+#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0
// method for reading clock interrupt latency
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
externC void hal_clock_latency(cyg_uint32 *);
-# define HAL_CLOCK_LATENCY( _pvalue_ ) \
- hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+# define HAL_CLOCK_LATENCY(_pvalue_) \
+ hal_clock_latency((cyg_uint32 *)(_pvalue_))
#endif
//----------------------------------------------------------------------------
// Reset.
-#define HAL_PLATFORM_RESET() \
- CYG_MACRO_START \
- writel(readl(NFC_FLASH_CONFIG3_REG) & ~0x73, NFC_FLASH_CONFIG3_REG); \
- *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4; \
- /* hang here forever if reset fails */ \
- while (1){} \
- CYG_MACRO_END
+#define HAL_PLATFORM_RESET() \
+ CYG_MACRO_START \
+ writel(readl(NFC_FLASH_CONFIG3_REG) & ~0x73, NFC_FLASH_CONFIG3_REG); \
+ *(volatile unsigned short *)WDOG_BASE_ADDR &= ~(1 << 4); \
+ /* hang here forever if reset fails */ \
+ while (1){} \
+ CYG_MACRO_END
// Fallback (never really used)
#define HAL_PLATFORM_RESET_ENTRY 0x00000000
--- /dev/null
+/***************************************************************************
+*
+* MX51_IOMUX.H
+*
+* Macros definations for MX51 IPUv3e IOMUX.
+*
+***************************************************************************
+*
+* Author(s) : Ray Sun-B17777 <Yanfei.Sun@freescale.com>
+* Create Date: 2008-11-10
+* Description : i.MX51 IOMUX defines
+*
+***************************************************************************/
+
+#ifndef _MX51_IOMUX_H_
+#define _MX51_IOMUX_H_
+
+#include <cyg/hal/hal_soc.h>
+
+#define GPR_BASE_ADDR (IOMUXC_BASE_ADDR + 0x0) // 0x0
+#define OBSRV_BASE_ADDR (GPR_BASE_ADDR + 0x8) // 0x8
+#define SW_MUX_BASE_ADDR (OBSRV_BASE_ADDR + 0x14) // 0x1c
+#define SW_PAD_BASE_ADDR (SW_MUX_BASE_ADDR + 0x3d4) // 0x3f0
+#define SW_GRP_BASE_ADDR (SW_PAD_BASE_ADDR + 0x42c) // 0x81c
+#define SW_INPUT_PORT_BASE_ADDR (SW_GRP_BASE_ADDR + 0xa8) // 0x8c4
+#define SELECT_INPUT_BASE_ADDR (SW_INPUT_PORT_BASE_ADDR + 0x0) // 0x8c4
+
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 (SW_MUX_BASE_ADDR + 0x0) // 0x1c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 (SW_MUX_BASE_ADDR + 0x4) // 0x20
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 (SW_MUX_BASE_ADDR + 0x8) // 0x24
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 (SW_MUX_BASE_ADDR + 0xc) // 0x28
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 (SW_MUX_BASE_ADDR + 0x10) // 0x2c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 (SW_MUX_BASE_ADDR + 0x14) // 0x30
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 (SW_MUX_BASE_ADDR + 0x18) // 0x34
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 (SW_MUX_BASE_ADDR + 0x1c) // 0x38
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 (SW_MUX_BASE_ADDR + 0x20) // 0x3c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 (SW_MUX_BASE_ADDR + 0x24) // 0x40
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 (SW_MUX_BASE_ADDR + 0x28) // 0x44
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 (SW_MUX_BASE_ADDR + 0x2c) // 0x48
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 (SW_MUX_BASE_ADDR + 0x30) // 0x4c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 (SW_MUX_BASE_ADDR + 0x34) // 0x50
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 (SW_MUX_BASE_ADDR + 0x38) // 0x54
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 (SW_MUX_BASE_ADDR + 0x3c) // 0x58
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 (SW_MUX_BASE_ADDR + 0x40) // 0x5c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 (SW_MUX_BASE_ADDR + 0x44) // 0x60
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 (SW_MUX_BASE_ADDR + 0x48) // 0x64
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 (SW_MUX_BASE_ADDR + 0x4c) // 0x68
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 (SW_MUX_BASE_ADDR + 0x50) // 0x6c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 (SW_MUX_BASE_ADDR + 0x54) // 0x70
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 (SW_MUX_BASE_ADDR + 0x58) // 0x74
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 (SW_MUX_BASE_ADDR + 0x5c) // 0x78
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 (SW_MUX_BASE_ADDR + 0x60) // 0x7c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 (SW_MUX_BASE_ADDR + 0x64) // 0x80
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 (SW_MUX_BASE_ADDR + 0x68) // 0x84
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 (SW_MUX_BASE_ADDR + 0x6c) // 0x88
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 (SW_MUX_BASE_ADDR + 0x70) // 0x8c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 (SW_MUX_BASE_ADDR + 0x74) // 0x90
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 (SW_MUX_BASE_ADDR + 0x78) // 0x94
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 (SW_MUX_BASE_ADDR + 0x7c) // 0x98
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 (SW_MUX_BASE_ADDR + 0x80) // 0x9c
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 (SW_MUX_BASE_ADDR + 0x84) // 0xa0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 (SW_MUX_BASE_ADDR + 0x88) // 0xa4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 (SW_MUX_BASE_ADDR + 0x8c) // 0xa8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 (SW_MUX_BASE_ADDR + 0x90) // 0xac
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 (SW_MUX_BASE_ADDR + 0x94) // 0xb0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 (SW_MUX_BASE_ADDR + 0x98) // 0xb4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 (SW_MUX_BASE_ADDR + 0x9c) // 0xb8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 (SW_MUX_BASE_ADDR + 0xa0) // 0xbc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 (SW_MUX_BASE_ADDR + 0xa4) // 0xc0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 (SW_MUX_BASE_ADDR + 0xa8) // 0xc4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 (SW_MUX_BASE_ADDR + 0xac) // 0xc8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 (SW_MUX_BASE_ADDR + 0xb0) // 0xcc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 (SW_MUX_BASE_ADDR + 0xb4) // 0xd0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 (SW_MUX_BASE_ADDR + 0xb8) // 0xd4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 (SW_MUX_BASE_ADDR + 0xbc) // 0xd8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_OE (SW_MUX_BASE_ADDR + 0xc0) // 0xdc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 (SW_MUX_BASE_ADDR + 0xc4) // 0xe0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 (SW_MUX_BASE_ADDR + 0xc8) // 0xe4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 (SW_MUX_BASE_ADDR + 0xcc) // 0xe8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 (SW_MUX_BASE_ADDR + 0xd0) // 0xec
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 (SW_MUX_BASE_ADDR + 0xd4) // 0xf0
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 (SW_MUX_BASE_ADDR + 0xd8) // 0xf4
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK (SW_MUX_BASE_ADDR + 0xdc) // 0xf8
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA (SW_MUX_BASE_ADDR + 0xe0) // 0xfc
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE (SW_MUX_BASE_ADDR + 0xe4) // 0x100
+#define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 (SW_MUX_BASE_ADDR + 0xe8) // 0x104
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B (SW_MUX_BASE_ADDR + 0xec) // 0x108
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B (SW_MUX_BASE_ADDR + 0xf0) // 0x10c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE (SW_MUX_BASE_ADDR + 0xf4) // 0x110
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE (SW_MUX_BASE_ADDR + 0xf8) // 0x114
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B (SW_MUX_BASE_ADDR + 0xfc) // 0x118
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 (SW_MUX_BASE_ADDR + 0x100) // 0x11c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 (SW_MUX_BASE_ADDR + 0x104) // 0x120
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 (SW_MUX_BASE_ADDR + 0x108) // 0x124
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 (SW_MUX_BASE_ADDR + 0x10c) // 0x128
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND (SW_MUX_BASE_ADDR + 0x110) // 0x12c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 (SW_MUX_BASE_ADDR + 0x114) // 0x130
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 (SW_MUX_BASE_ADDR + 0x118) // 0x134
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 (SW_MUX_BASE_ADDR + 0x11c) // 0x138
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 (SW_MUX_BASE_ADDR + 0x120) // 0x13c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 (SW_MUX_BASE_ADDR + 0x124) // 0x140
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 (SW_MUX_BASE_ADDR + 0x128) // 0x144
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 (SW_MUX_BASE_ADDR + 0x12c) // 0x148
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 (SW_MUX_BASE_ADDR + 0x130) // 0x14c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT (SW_MUX_BASE_ADDR + 0x134) // 0x150
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 (SW_MUX_BASE_ADDR + 0x138) // 0x154
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 (SW_MUX_BASE_ADDR + 0x13c) // 0x158
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 (SW_MUX_BASE_ADDR + 0x140) // 0x15c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 (SW_MUX_BASE_ADDR + 0x144) // 0x160
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 (SW_MUX_BASE_ADDR + 0x148) // 0x164
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 (SW_MUX_BASE_ADDR + 0x14c) // 0x168
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 (SW_MUX_BASE_ADDR + 0x150) // 0x16c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 (SW_MUX_BASE_ADDR + 0x154) // 0x170
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 (SW_MUX_BASE_ADDR + 0x158) // 0x174
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 (SW_MUX_BASE_ADDR + 0x15c) // 0x178
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 (SW_MUX_BASE_ADDR + 0x160) // 0x17c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 (SW_MUX_BASE_ADDR + 0x164) // 0x180
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 (SW_MUX_BASE_ADDR + 0x168) // 0x184
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 (SW_MUX_BASE_ADDR + 0x16c) // 0x188
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 (SW_MUX_BASE_ADDR + 0x170) // 0x18c
+#define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 (SW_MUX_BASE_ADDR + 0x174) // 0x190
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 (SW_MUX_BASE_ADDR + 0x178) // 0x194
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 (SW_MUX_BASE_ADDR + 0x17c) // 0x198
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 (SW_MUX_BASE_ADDR + 0x180) // 0x19c
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 (SW_MUX_BASE_ADDR + 0x184) // 0x1a0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 (SW_MUX_BASE_ADDR + 0x188) // 0x1a4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 (SW_MUX_BASE_ADDR + 0x18c) // 0x1a8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 (SW_MUX_BASE_ADDR + 0x190) // 0x1ac
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 (SW_MUX_BASE_ADDR + 0x194) // 0x1b0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 (SW_MUX_BASE_ADDR + 0x198) // 0x1b4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 (SW_MUX_BASE_ADDR + 0x19c) // 0x1b8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 (SW_MUX_BASE_ADDR + 0x1a0) // 0x1bc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 (SW_MUX_BASE_ADDR + 0x1a4) // 0x1c0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC (SW_MUX_BASE_ADDR + 0x1a8) // 0x1c4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC (SW_MUX_BASE_ADDR + 0x1ac) // 0x1c8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 (SW_MUX_BASE_ADDR + 0x1b0) // 0x1cc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 (SW_MUX_BASE_ADDR + 0x1b4) // 0x1d0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 (SW_MUX_BASE_ADDR + 0x1b8) // 0x1d4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 (SW_MUX_BASE_ADDR + 0x1bc) // 0x1d8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 (SW_MUX_BASE_ADDR + 0x1c0) // 0x1dc
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 (SW_MUX_BASE_ADDR + 0x1c4) // 0x1e0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 (SW_MUX_BASE_ADDR + 0x1c8) // 0x1e4
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 (SW_MUX_BASE_ADDR + 0x1cc) // 0x1e8
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC (SW_MUX_BASE_ADDR + 0x1d0) // 0x1ec
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC (SW_MUX_BASE_ADDR + 0x1d4) // 0x1f0
+#define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK (SW_MUX_BASE_ADDR + 0x1d8) // 0x1f4
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK (SW_MUX_BASE_ADDR + 0x1dc) // 0x1f8
+#define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT (SW_MUX_BASE_ADDR + 0x1e0) // 0x1fc
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD (SW_MUX_BASE_ADDR + 0x1e4) // 0x200
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD (SW_MUX_BASE_ADDR + 0x1e8) // 0x204
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK (SW_MUX_BASE_ADDR + 0x1ec) // 0x208
+#define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS (SW_MUX_BASE_ADDR + 0x1f0) // 0x20c
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI (SW_MUX_BASE_ADDR + 0x1f4) // 0x210
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO (SW_MUX_BASE_ADDR + 0x1f8) // 0x214
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 (SW_MUX_BASE_ADDR + 0x1fc) // 0x218
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 (SW_MUX_BASE_ADDR + 0x200) // 0x21c
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY (SW_MUX_BASE_ADDR + 0x204) // 0x220
+#define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK (SW_MUX_BASE_ADDR + 0x208) // 0x224
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD (SW_MUX_BASE_ADDR + 0x20c) // 0x228
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD (SW_MUX_BASE_ADDR + 0x210) // 0x22c
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS (SW_MUX_BASE_ADDR + 0x214) // 0x230
+#define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS (SW_MUX_BASE_ADDR + 0x218) // 0x234
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD (SW_MUX_BASE_ADDR + 0x21c) // 0x238
+#define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD (SW_MUX_BASE_ADDR + 0x220) // 0x23c
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD (SW_MUX_BASE_ADDR + 0x224) // 0x240
+#define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD (SW_MUX_BASE_ADDR + 0x228) // 0x244
+#define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE (SW_MUX_BASE_ADDR + 0x22c) // 0x248
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 (SW_MUX_BASE_ADDR + 0x230) // 0x24c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 (SW_MUX_BASE_ADDR + 0x234) // 0x250
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 (SW_MUX_BASE_ADDR + 0x238) // 0x254
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 (SW_MUX_BASE_ADDR + 0x23c) // 0x258
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 (SW_MUX_BASE_ADDR + 0x240) // 0x25c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 (SW_MUX_BASE_ADDR + 0x244) // 0x260
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 (SW_MUX_BASE_ADDR + 0x248) // 0x264
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 (SW_MUX_BASE_ADDR + 0x24c) // 0x268
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 (SW_MUX_BASE_ADDR + 0x250) // 0x26c
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 (SW_MUX_BASE_ADDR + 0x254) // 0x270
+#define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B (SW_MUX_BASE_ADDR + 0x258) // 0x274
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK (SW_MUX_BASE_ADDR + 0x25c) // 0x278
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR (SW_MUX_BASE_ADDR + 0x260) // 0x27c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP (SW_MUX_BASE_ADDR + 0x264) // 0x280
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT (SW_MUX_BASE_ADDR + 0x268) // 0x284
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 (SW_MUX_BASE_ADDR + 0x26c) // 0x288
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 (SW_MUX_BASE_ADDR + 0x270) // 0x28c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 (SW_MUX_BASE_ADDR + 0x274) // 0x290
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 (SW_MUX_BASE_ADDR + 0x278) // 0x294
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 (SW_MUX_BASE_ADDR + 0x27c) // 0x298
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 (SW_MUX_BASE_ADDR + 0x280) // 0x29c
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 (SW_MUX_BASE_ADDR + 0x284) // 0x2a0
+#define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 (SW_MUX_BASE_ADDR + 0x288) // 0x2a4
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 (SW_MUX_BASE_ADDR + 0x28c) // 0x2a8
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 (SW_MUX_BASE_ADDR + 0x290) // 0x2ac
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 (SW_MUX_BASE_ADDR + 0x294) // 0x2b0
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS (SW_MUX_BASE_ADDR + 0x298) // 0x2b4
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS (SW_MUX_BASE_ADDR + 0x29c) // 0x2b8
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN (SW_MUX_BASE_ADDR + 0x2a0) // 0x2bc
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO (SW_MUX_BASE_ADDR + 0x2a4) // 0x2c0
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK (SW_MUX_BASE_ADDR + 0x2a8) // 0x2c4
+#define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS (SW_MUX_BASE_ADDR + 0x2ac) // 0x2c8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 (SW_MUX_BASE_ADDR + 0x2b0) // 0x2cc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 (SW_MUX_BASE_ADDR + 0x2b4) // 0x2d0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 (SW_MUX_BASE_ADDR + 0x2b8) // 0x2d4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 (SW_MUX_BASE_ADDR + 0x2bc) // 0x2d8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 (SW_MUX_BASE_ADDR + 0x2c0) // 0x2dc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 (SW_MUX_BASE_ADDR + 0x2c4) // 0x2e0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 (SW_MUX_BASE_ADDR + 0x2c8) // 0x2e4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 (SW_MUX_BASE_ADDR + 0x2cc) // 0x2e8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 (SW_MUX_BASE_ADDR + 0x2d0) // 0x2ec
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 (SW_MUX_BASE_ADDR + 0x2d4) // 0x2f0
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 (SW_MUX_BASE_ADDR + 0x2d8) // 0x2f4
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 (SW_MUX_BASE_ADDR + 0x2dc) // 0x2f8
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 (SW_MUX_BASE_ADDR + 0x2e0) // 0x2fc
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 (SW_MUX_BASE_ADDR + 0x2e4) // 0x300
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 (SW_MUX_BASE_ADDR + 0x2e8) // 0x304
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 (SW_MUX_BASE_ADDR + 0x2ec) // 0x308
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 (SW_MUX_BASE_ADDR + 0x2f0) // 0x30c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 (SW_MUX_BASE_ADDR + 0x2f4) // 0x310
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 (SW_MUX_BASE_ADDR + 0x2f8) // 0x314
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 (SW_MUX_BASE_ADDR + 0x2fc) // 0x318
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 (SW_MUX_BASE_ADDR + 0x300) // 0x31c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 (SW_MUX_BASE_ADDR + 0x304) // 0x320
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 (SW_MUX_BASE_ADDR + 0x308) // 0x324
+#define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 (SW_MUX_BASE_ADDR + 0x30c) // 0x328
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 (SW_MUX_BASE_ADDR + 0x310) // 0x32c
+#define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 (SW_MUX_BASE_ADDR + 0x314) // 0x330
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 (SW_MUX_BASE_ADDR + 0x318) // 0x334
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 (SW_MUX_BASE_ADDR + 0x31c) // 0x338
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 (SW_MUX_BASE_ADDR + 0x320) // 0x33c
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 (SW_MUX_BASE_ADDR + 0x324) // 0x340
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 (SW_MUX_BASE_ADDR + 0x328) // 0x344
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 (SW_MUX_BASE_ADDR + 0x32c) // 0x348
+#define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK (SW_MUX_BASE_ADDR + 0x330) // 0x34c
+#define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 (SW_MUX_BASE_ADDR + 0x334) // 0x350
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 (SW_MUX_BASE_ADDR + 0x338) // 0x354
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 (SW_MUX_BASE_ADDR + 0x33c) // 0x358
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 (SW_MUX_BASE_ADDR + 0x340) // 0x35c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 (SW_MUX_BASE_ADDR + 0x344) // 0x360
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 (SW_MUX_BASE_ADDR + 0x348) // 0x364
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 (SW_MUX_BASE_ADDR + 0x34c) // 0x368
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 (SW_MUX_BASE_ADDR + 0x350) // 0x36c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 (SW_MUX_BASE_ADDR + 0x354) // 0x370
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 (SW_MUX_BASE_ADDR + 0x358) // 0x374
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 (SW_MUX_BASE_ADDR + 0x35c) // 0x378
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 (SW_MUX_BASE_ADDR + 0x360) // 0x37c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 (SW_MUX_BASE_ADDR + 0x364) // 0x380
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 (SW_MUX_BASE_ADDR + 0x368) // 0x384
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 (SW_MUX_BASE_ADDR + 0x36c) // 0x388
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 (SW_MUX_BASE_ADDR + 0x370) // 0x38c
+#define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 (SW_MUX_BASE_ADDR + 0x374) // 0x390
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD (SW_MUX_BASE_ADDR + 0x378) // 0x394
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK (SW_MUX_BASE_ADDR + 0x37c) // 0x398
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 (SW_MUX_BASE_ADDR + 0x380) // 0x39c
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 (SW_MUX_BASE_ADDR + 0x384) // 0x3a0
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 (SW_MUX_BASE_ADDR + 0x388) // 0x3a4
+#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 (SW_MUX_BASE_ADDR + 0x38c) // 0x3a8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 (SW_MUX_BASE_ADDR + 0x390) // 0x3ac
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 (SW_MUX_BASE_ADDR + 0x394) // 0x3b0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD (SW_MUX_BASE_ADDR + 0x398) // 0x3b4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK (SW_MUX_BASE_ADDR + 0x39c) // 0x3b8
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 (SW_MUX_BASE_ADDR + 0x3a0) // 0x3bc
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 (SW_MUX_BASE_ADDR + 0x3a4) // 0x3c0
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 (SW_MUX_BASE_ADDR + 0x3a8) // 0x3c4
+#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 (SW_MUX_BASE_ADDR + 0x3ac) // 0x3c8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 (SW_MUX_BASE_ADDR + 0x3b0) // 0x3cc
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 (SW_MUX_BASE_ADDR + 0x3b4) // 0x3d0
+#define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ (SW_MUX_BASE_ADDR + 0x3b8) // 0x3d4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 (SW_MUX_BASE_ADDR + 0x3bc) // 0x3d8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 (SW_MUX_BASE_ADDR + 0x3c0) // 0x3dc
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 (SW_MUX_BASE_ADDR + 0x3c4) // 0x3e0
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 (SW_MUX_BASE_ADDR + 0x3c8) // 0x3e4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 (SW_MUX_BASE_ADDR + 0x3cc) // 0x3e8
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 (SW_MUX_BASE_ADDR + 0x3d0) // 0x3ec
+
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 (SW_PAD_BASE_ADDR + 0x0) // 0x3f0
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 (SW_PAD_BASE_ADDR + 0x4) // 0x3f4
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 (SW_PAD_BASE_ADDR + 0x8) // 0x3f8
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 (SW_PAD_BASE_ADDR + 0xc) // 0x3fc
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 (SW_PAD_BASE_ADDR + 0x10) // 0x400
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 (SW_PAD_BASE_ADDR + 0x14) // 0x404
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 (SW_PAD_BASE_ADDR + 0x18) // 0x408
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 (SW_PAD_BASE_ADDR + 0x1c) // 0x40c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 (SW_PAD_BASE_ADDR + 0x20) // 0x410
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 (SW_PAD_BASE_ADDR + 0x24) // 0x414
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 (SW_PAD_BASE_ADDR + 0x28) // 0x418
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 (SW_PAD_BASE_ADDR + 0x2c) // 0x41c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 (SW_PAD_BASE_ADDR + 0x30) // 0x420
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 (SW_PAD_BASE_ADDR + 0x34) // 0x424
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 (SW_PAD_BASE_ADDR + 0x38) // 0x428
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 (SW_PAD_BASE_ADDR + 0x3c) // 0x42c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 (SW_PAD_BASE_ADDR + 0x40) // 0x430
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 (SW_PAD_BASE_ADDR + 0x44) // 0x434
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 (SW_PAD_BASE_ADDR + 0x48) // 0x438
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 (SW_PAD_BASE_ADDR + 0x4c) // 0x43c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 (SW_PAD_BASE_ADDR + 0x50) // 0x440
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 (SW_PAD_BASE_ADDR + 0x54) // 0x444
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 (SW_PAD_BASE_ADDR + 0x58) // 0x448
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 (SW_PAD_BASE_ADDR + 0x5c) // 0x44c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 (SW_PAD_BASE_ADDR + 0x60) // 0x450
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 (SW_PAD_BASE_ADDR + 0x64) // 0x454
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 (SW_PAD_BASE_ADDR + 0x68) // 0x458
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 (SW_PAD_BASE_ADDR + 0x6c) // 0x45c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 (SW_PAD_BASE_ADDR + 0x70) // 0x460
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 (SW_PAD_BASE_ADDR + 0x74) // 0x464
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 (SW_PAD_BASE_ADDR + 0x78) // 0x468
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 (SW_PAD_BASE_ADDR + 0x7c) // 0x46c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_OE (SW_PAD_BASE_ADDR + 0x80) // 0x470
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 (SW_PAD_BASE_ADDR + 0x84) // 0x474
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 (SW_PAD_BASE_ADDR + 0x88) // 0x478
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 (SW_PAD_BASE_ADDR + 0x8c) // 0x47c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 (SW_PAD_BASE_ADDR + 0x90) // 0x480
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 (SW_PAD_BASE_ADDR + 0x94) // 0x484
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 (SW_PAD_BASE_ADDR + 0x98) // 0x488
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK (SW_PAD_BASE_ADDR + 0x9c) // 0x48c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT (SW_PAD_BASE_ADDR + 0xa0) // 0x490
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA (SW_PAD_BASE_ADDR + 0xa4) // 0x494
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK (SW_PAD_BASE_ADDR + 0xa8) // 0x498
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_RW (SW_PAD_BASE_ADDR + 0xac) // 0x49c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE (SW_PAD_BASE_ADDR + 0xb0) // 0x4a0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS (SW_PAD_BASE_ADDR + 0xb4) // 0x4a4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS (SW_PAD_BASE_ADDR + 0xb8) // 0x4a8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE (SW_PAD_BASE_ADDR + 0xbc) // 0x4ac
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 (SW_PAD_BASE_ADDR + 0xc0) // 0x4b0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 (SW_PAD_BASE_ADDR + 0xc4) // 0x4b4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK (SW_PAD_BASE_ADDR + 0xc8) // 0x4b8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 (SW_PAD_BASE_ADDR + 0xcc) // 0x4bc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 (SW_PAD_BASE_ADDR + 0xd0) // 0x4c0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 (SW_PAD_BASE_ADDR + 0xd4) // 0x4c4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 (SW_PAD_BASE_ADDR + 0xd8) // 0x4c8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 (SW_PAD_BASE_ADDR + 0xdc) // 0x4cc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 (SW_PAD_BASE_ADDR + 0xe0) // 0x4d0
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 (SW_PAD_BASE_ADDR + 0xe4) // 0x4d4
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 (SW_PAD_BASE_ADDR + 0xe8) // 0x4d8
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 (SW_PAD_BASE_ADDR + 0xec) // 0x4dc
+#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 (SW_PAD_BASE_ADDR + 0xf0) // 0x4e0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B (SW_PAD_BASE_ADDR + 0xf4) // 0x4e4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B (SW_PAD_BASE_ADDR + 0xf8) // 0x4e8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE (SW_PAD_BASE_ADDR + 0xfc) // 0x4ec
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE (SW_PAD_BASE_ADDR + 0x100) // 0x4f0
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B (SW_PAD_BASE_ADDR + 0x104) // 0x4f4
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 (SW_PAD_BASE_ADDR + 0x108) // 0x4f8
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 (SW_PAD_BASE_ADDR + 0x10c) // 0x4fc
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 (SW_PAD_BASE_ADDR + 0x110) // 0x500
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 (SW_PAD_BASE_ADDR + 0x114) // 0x504
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 (SW_PAD_BASE_ADDR + 0x118) // 0x508
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 (SW_PAD_BASE_ADDR + 0x11c) // 0x50c
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 (SW_PAD_BASE_ADDR + 0x120) // 0x510
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND (SW_PAD_BASE_ADDR + 0x124) // 0x514
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 (SW_PAD_BASE_ADDR + 0x128) // 0x518
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 (SW_PAD_BASE_ADDR + 0x12c) // 0x51c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 (SW_PAD_BASE_ADDR + 0x130) // 0x520
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 (SW_PAD_BASE_ADDR + 0x134) // 0x524
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 (SW_PAD_BASE_ADDR + 0x138) // 0x528
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 (SW_PAD_BASE_ADDR + 0x13c) // 0x52c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 (SW_PAD_BASE_ADDR + 0x140) // 0x530
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 (SW_PAD_BASE_ADDR + 0x144) // 0x534
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT (SW_PAD_BASE_ADDR + 0x148) // 0x538
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 (SW_PAD_BASE_ADDR + 0x14c) // 0x53c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 (SW_PAD_BASE_ADDR + 0x150) // 0x540
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 (SW_PAD_BASE_ADDR + 0x154) // 0x544
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 (SW_PAD_BASE_ADDR + 0x158) // 0x548
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 (SW_PAD_BASE_ADDR + 0x15c) // 0x54c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 (SW_PAD_BASE_ADDR + 0x160) // 0x550
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 (SW_PAD_BASE_ADDR + 0x164) // 0x554
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 (SW_PAD_BASE_ADDR + 0x168) // 0x558
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 (SW_PAD_BASE_ADDR + 0x16c) // 0x55c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 (SW_PAD_BASE_ADDR + 0x170) // 0x560
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 (SW_PAD_BASE_ADDR + 0x174) // 0x564
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 (SW_PAD_BASE_ADDR + 0x178) // 0x568
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 (SW_PAD_BASE_ADDR + 0x17c) // 0x56c
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 (SW_PAD_BASE_ADDR + 0x180) // 0x570
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 (SW_PAD_BASE_ADDR + 0x184) // 0x574
+#define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 (SW_PAD_BASE_ADDR + 0x188) // 0x578
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 (SW_PAD_BASE_ADDR + 0x18c) // 0x57c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 (SW_PAD_BASE_ADDR + 0x190) // 0x580
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 (SW_PAD_BASE_ADDR + 0x194) // 0x584
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 (SW_PAD_BASE_ADDR + 0x198) // 0x588
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 (SW_PAD_BASE_ADDR + 0x19c) // 0x58c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 (SW_PAD_BASE_ADDR + 0x1a0) // 0x590
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 (SW_PAD_BASE_ADDR + 0x1a4) // 0x594
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 (SW_PAD_BASE_ADDR + 0x1a8) // 0x598
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 (SW_PAD_BASE_ADDR + 0x1ac) // 0x59c
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 (SW_PAD_BASE_ADDR + 0x1b0) // 0x5a0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 (SW_PAD_BASE_ADDR + 0x1b4) // 0x5a4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 (SW_PAD_BASE_ADDR + 0x1b8) // 0x5a8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC (SW_PAD_BASE_ADDR + 0x1bc) // 0x5ac
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC (SW_PAD_BASE_ADDR + 0x1c0) // 0x5b0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK (SW_PAD_BASE_ADDR + 0x1c4) // 0x5b4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK (SW_PAD_BASE_ADDR + 0x1c8) // 0x5b8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 (SW_PAD_BASE_ADDR + 0x1cc) // 0x5bc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 (SW_PAD_BASE_ADDR + 0x1d0) // 0x5c0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 (SW_PAD_BASE_ADDR + 0x1d4) // 0x5c4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 (SW_PAD_BASE_ADDR + 0x1d8) // 0x5c8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 (SW_PAD_BASE_ADDR + 0x1dc) // 0x5cc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 (SW_PAD_BASE_ADDR + 0x1e0) // 0x5d0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 (SW_PAD_BASE_ADDR + 0x1e4) // 0x5d4
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 (SW_PAD_BASE_ADDR + 0x1e8) // 0x5d8
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC (SW_PAD_BASE_ADDR + 0x1ec) // 0x5dc
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC (SW_PAD_BASE_ADDR + 0x1f0) // 0x5e0
+#define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK (SW_PAD_BASE_ADDR + 0x1f4) // 0x5e4
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK (SW_PAD_BASE_ADDR + 0x1f8) // 0x5e8
+#define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT (SW_PAD_BASE_ADDR + 0x1fc) // 0x5ec
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD (SW_PAD_BASE_ADDR + 0x200) // 0x5f0
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD (SW_PAD_BASE_ADDR + 0x204) // 0x5f4
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK (SW_PAD_BASE_ADDR + 0x208) // 0x5f8
+#define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS (SW_PAD_BASE_ADDR + 0x20c) // 0x5fc
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI (SW_PAD_BASE_ADDR + 0x210) // 0x600
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO (SW_PAD_BASE_ADDR + 0x214) // 0x604
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 (SW_PAD_BASE_ADDR + 0x218) // 0x608
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 (SW_PAD_BASE_ADDR + 0x21c) // 0x60c
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY (SW_PAD_BASE_ADDR + 0x220) // 0x610
+#define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK (SW_PAD_BASE_ADDR + 0x224) // 0x614
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD (SW_PAD_BASE_ADDR + 0x228) // 0x618
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD (SW_PAD_BASE_ADDR + 0x22c) // 0x61c
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS (SW_PAD_BASE_ADDR + 0x230) // 0x620
+#define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS (SW_PAD_BASE_ADDR + 0x234) // 0x624
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD (SW_PAD_BASE_ADDR + 0x238) // 0x628
+#define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD (SW_PAD_BASE_ADDR + 0x23c) // 0x62c
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD (SW_PAD_BASE_ADDR + 0x240) // 0x630
+#define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD (SW_PAD_BASE_ADDR + 0x244) // 0x634
+#define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE (SW_PAD_BASE_ADDR + 0x248) // 0x638
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 (SW_PAD_BASE_ADDR + 0x24c) // 0x63c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 (SW_PAD_BASE_ADDR + 0x250) // 0x640
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 (SW_PAD_BASE_ADDR + 0x254) // 0x644
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 (SW_PAD_BASE_ADDR + 0x258) // 0x648
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 (SW_PAD_BASE_ADDR + 0x25c) // 0x64c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 (SW_PAD_BASE_ADDR + 0x260) // 0x650
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 (SW_PAD_BASE_ADDR + 0x264) // 0x654
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 (SW_PAD_BASE_ADDR + 0x268) // 0x658
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 (SW_PAD_BASE_ADDR + 0x26c) // 0x65c
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 (SW_PAD_BASE_ADDR + 0x270) // 0x660
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK (SW_PAD_BASE_ADDR + 0x274) // 0x664
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS (SW_PAD_BASE_ADDR + 0x278) // 0x668
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI (SW_PAD_BASE_ADDR + 0x27c) // 0x66c
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB (SW_PAD_BASE_ADDR + 0x280) // 0x670
+#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD (SW_PAD_BASE_ADDR + 0x284) // 0x674
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK (SW_PAD_BASE_ADDR + 0x288) // 0x678
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR (SW_PAD_BASE_ADDR + 0x28c) // 0x67c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP (SW_PAD_BASE_ADDR + 0x290) // 0x680
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT (SW_PAD_BASE_ADDR + 0x294) // 0x684
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 (SW_PAD_BASE_ADDR + 0x298) // 0x688
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 (SW_PAD_BASE_ADDR + 0x29c) // 0x68c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 (SW_PAD_BASE_ADDR + 0x2a0) // 0x690
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 (SW_PAD_BASE_ADDR + 0x2a4) // 0x694
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 (SW_PAD_BASE_ADDR + 0x2a8) // 0x698
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 (SW_PAD_BASE_ADDR + 0x2ac) // 0x69c
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 (SW_PAD_BASE_ADDR + 0x2b0) // 0x6a0
+#define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 (SW_PAD_BASE_ADDR + 0x2b4) // 0x6a4
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 (SW_PAD_BASE_ADDR + 0x2b8) // 0x6a8
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 (SW_PAD_BASE_ADDR + 0x2bc) // 0x6ac
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 (SW_PAD_BASE_ADDR + 0x2c0) // 0x6b0
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS (SW_PAD_BASE_ADDR + 0x2c4) // 0x6b4
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS (SW_PAD_BASE_ADDR + 0x2c8) // 0x6b8
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN (SW_PAD_BASE_ADDR + 0x2cc) // 0x6bc
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO (SW_PAD_BASE_ADDR + 0x2d0) // 0x6c0
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK (SW_PAD_BASE_ADDR + 0x2d4) // 0x6c4
+#define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS (SW_PAD_BASE_ADDR + 0x2d8) // 0x6c8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 (SW_PAD_BASE_ADDR + 0x2dc) // 0x6cc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 (SW_PAD_BASE_ADDR + 0x2e0) // 0x6d0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 (SW_PAD_BASE_ADDR + 0x2e4) // 0x6d4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 (SW_PAD_BASE_ADDR + 0x2e8) // 0x6d8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 (SW_PAD_BASE_ADDR + 0x2ec) // 0x6dc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 (SW_PAD_BASE_ADDR + 0x2f0) // 0x6e0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 (SW_PAD_BASE_ADDR + 0x2f4) // 0x6e4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 (SW_PAD_BASE_ADDR + 0x2f8) // 0x6e8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 (SW_PAD_BASE_ADDR + 0x2fc) // 0x6ec
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 (SW_PAD_BASE_ADDR + 0x300) // 0x6f0
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 (SW_PAD_BASE_ADDR + 0x304) // 0x6f4
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 (SW_PAD_BASE_ADDR + 0x308) // 0x6f8
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 (SW_PAD_BASE_ADDR + 0x30c) // 0x6fc
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 (SW_PAD_BASE_ADDR + 0x310) // 0x700
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 (SW_PAD_BASE_ADDR + 0x314) // 0x704
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 (SW_PAD_BASE_ADDR + 0x318) // 0x708
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 (SW_PAD_BASE_ADDR + 0x31c) // 0x70c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 (SW_PAD_BASE_ADDR + 0x320) // 0x710
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 (SW_PAD_BASE_ADDR + 0x324) // 0x714
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 (SW_PAD_BASE_ADDR + 0x328) // 0x718
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 (SW_PAD_BASE_ADDR + 0x32c) // 0x71c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 (SW_PAD_BASE_ADDR + 0x330) // 0x720
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 (SW_PAD_BASE_ADDR + 0x334) // 0x724
+#define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 (SW_PAD_BASE_ADDR + 0x338) // 0x728
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 (SW_PAD_BASE_ADDR + 0x33c) // 0x72c
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK (SW_PAD_BASE_ADDR + 0x340) // 0x730
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 (SW_PAD_BASE_ADDR + 0x344) // 0x734
+#define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 (SW_PAD_BASE_ADDR + 0x348) // 0x738
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 (SW_PAD_BASE_ADDR + 0x34c) // 0x73c
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 (SW_PAD_BASE_ADDR + 0x350) // 0x740
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 (SW_PAD_BASE_ADDR + 0x354) // 0x744
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 (SW_PAD_BASE_ADDR + 0x358) // 0x748
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 (SW_PAD_BASE_ADDR + 0x35c) // 0x74c
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 (SW_PAD_BASE_ADDR + 0x360) // 0x750
+#define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK (SW_PAD_BASE_ADDR + 0x364) // 0x754
+#define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 (SW_PAD_BASE_ADDR + 0x368) // 0x758
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 (SW_PAD_BASE_ADDR + 0x36c) // 0x75c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 (SW_PAD_BASE_ADDR + 0x370) // 0x760
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 (SW_PAD_BASE_ADDR + 0x374) // 0x764
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 (SW_PAD_BASE_ADDR + 0x378) // 0x768
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 (SW_PAD_BASE_ADDR + 0x37c) // 0x76c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 (SW_PAD_BASE_ADDR + 0x380) // 0x770
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 (SW_PAD_BASE_ADDR + 0x384) // 0x774
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 (SW_PAD_BASE_ADDR + 0x388) // 0x778
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 (SW_PAD_BASE_ADDR + 0x38c) // 0x77c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 (SW_PAD_BASE_ADDR + 0x390) // 0x780
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 (SW_PAD_BASE_ADDR + 0x394) // 0x784
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 (SW_PAD_BASE_ADDR + 0x398) // 0x788
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 (SW_PAD_BASE_ADDR + 0x39c) // 0x78c
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 (SW_PAD_BASE_ADDR + 0x3a0) // 0x790
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 (SW_PAD_BASE_ADDR + 0x3a4) // 0x794
+#define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 (SW_PAD_BASE_ADDR + 0x3a8) // 0x798
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD (SW_PAD_BASE_ADDR + 0x3ac) // 0x79c
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK (SW_PAD_BASE_ADDR + 0x3b0) // 0x7a0
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 (SW_PAD_BASE_ADDR + 0x3b4) // 0x7a4
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 (SW_PAD_BASE_ADDR + 0x3b8) // 0x7a8
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 (SW_PAD_BASE_ADDR + 0x3bc) // 0x7ac
+#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 (SW_PAD_BASE_ADDR + 0x3c0) // 0x7b0
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 (SW_PAD_BASE_ADDR + 0x3c4) // 0x7b4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 (SW_PAD_BASE_ADDR + 0x3c8) // 0x7b8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD (SW_PAD_BASE_ADDR + 0x3cc) // 0x7bc
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK (SW_PAD_BASE_ADDR + 0x3d0) // 0x7c0
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 (SW_PAD_BASE_ADDR + 0x3d4) // 0x7c4
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 (SW_PAD_BASE_ADDR + 0x3d8) // 0x7c8
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 (SW_PAD_BASE_ADDR + 0x3dc) // 0x7cc
+#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 (SW_PAD_BASE_ADDR + 0x3e0) // 0x7d0
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 (SW_PAD_BASE_ADDR + 0x3e4) // 0x7d4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 (SW_PAD_BASE_ADDR + 0x3e8) // 0x7d8
+#define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B (SW_PAD_BASE_ADDR + 0x3ec) // 0x7dc
+#define IOMUXC_SW_PAD_CTL_PAD_POR_B (SW_PAD_BASE_ADDR + 0x3f0) // 0x7e0
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 (SW_PAD_BASE_ADDR + 0x3f4) // 0x7e4
+#define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 (SW_PAD_BASE_ADDR + 0x3f8) // 0x7e8
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY (SW_PAD_BASE_ADDR + 0x3fc) // 0x7ec
+#define IOMUXC_SW_PAD_CTL_PAD_CKIL (SW_PAD_BASE_ADDR + 0x400) // 0x7f0
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ (SW_PAD_BASE_ADDR + 0x404) // 0x7f4
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ (SW_PAD_BASE_ADDR + 0x408) // 0x7f8
+#define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ (SW_PAD_BASE_ADDR + 0x40c) // 0x7fc
+#define IOMUXC_SW_PAD_CTL_PAD_CLK_SS (SW_PAD_BASE_ADDR + 0x410) // 0x800
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 (SW_PAD_BASE_ADDR + 0x414) // 0x804
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 (SW_PAD_BASE_ADDR + 0x418) // 0x808
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 (SW_PAD_BASE_ADDR + 0x41c) // 0x80c
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 (SW_PAD_BASE_ADDR + 0x420) // 0x810
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 (SW_PAD_BASE_ADDR + 0x424) // 0x814
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 (SW_PAD_BASE_ADDR + 0x428) // 0x818
+
+#define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 (SW_GRP_BASE_ADDR + 0x0) // 0x81c
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS (SW_GRP_BASE_ADDR + 0x4) // 0x820
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 (SW_GRP_BASE_ADDR + 0x8) // 0x824
+#define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 (SW_GRP_BASE_ADDR + 0xc) // 0x828
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 (SW_GRP_BASE_ADDR + 0x10) // 0x82c
+#define IOMUXC_SW_PAD_CTL_GRP_INDDR (SW_GRP_BASE_ADDR + 0x14) // 0x830
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 (SW_GRP_BASE_ADDR + 0x18) // 0x834
+#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR (SW_GRP_BASE_ADDR + 0x1c) // 0x838
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 (SW_GRP_BASE_ADDR + 0x20) // 0x83c
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 (SW_GRP_BASE_ADDR + 0x24) // 0x840
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 (SW_GRP_BASE_ADDR + 0x28) // 0x844
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 (SW_GRP_BASE_ADDR + 0x2c) // 0x848
+#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS (SW_GRP_BASE_ADDR + 0x30) // 0x84c
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 (SW_GRP_BASE_ADDR + 0x34) // 0x850
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 (SW_GRP_BASE_ADDR + 0x38) // 0x854
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 (SW_GRP_BASE_ADDR + 0x3c) // 0x858
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 (SW_GRP_BASE_ADDR + 0x40) // 0x85c
+#define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 (SW_GRP_BASE_ADDR + 0x44) // 0x860
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 (SW_GRP_BASE_ADDR + 0x48) // 0x864
+#define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 (SW_GRP_BASE_ADDR + 0x4c) // 0x868
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 (SW_GRP_BASE_ADDR + 0x50) // 0x86c
+#define IOMUXC_SW_PAD_CTL_GRP_HVDDR (SW_GRP_BASE_ADDR + 0x54) // 0x870
+#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 (SW_GRP_BASE_ADDR + 0x58) // 0x874
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 (SW_GRP_BASE_ADDR + 0x5c) // 0x878
+#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS (SW_GRP_BASE_ADDR + 0x60) // 0x87c
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 (SW_GRP_BASE_ADDR + 0x64) // 0x880
+#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS (SW_GRP_BASE_ADDR + 0x68) // 0x884
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 (SW_GRP_BASE_ADDR + 0x6c) // 0x888
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 (SW_GRP_BASE_ADDR + 0x70) // 0x88c
+#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR (SW_GRP_BASE_ADDR + 0x74) // 0x890
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 (SW_GRP_BASE_ADDR + 0x78) // 0x894
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 (SW_GRP_BASE_ADDR + 0x7c) // 0x898
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 (SW_GRP_BASE_ADDR + 0x80) // 0x89c
+#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 (SW_GRP_BASE_ADDR + 0x84) // 0x8a0
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 (SW_GRP_BASE_ADDR + 0x88) // 0x8a4
+#define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 (SW_GRP_BASE_ADDR + 0x8c) // 0x8a8
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 (SW_GRP_BASE_ADDR + 0x90) // 0x8ac
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 (SW_GRP_BASE_ADDR + 0x94) // 0x8b0
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 (SW_GRP_BASE_ADDR + 0x98) // 0x8b4
+#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 (SW_GRP_BASE_ADDR + 0x9c) // 0x8b8
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 (SW_GRP_BASE_ADDR + 0xa0) // 0x8bc
+#define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 (SW_GRP_BASE_ADDR + 0xa4) // 0x8c0
+
+#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x0) // 0x8c4
+#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4) // 0x8c8
+#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8) // 0x8cc
+#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc) // 0x8d0
+#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10) // 0x8d4
+#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14) // 0x8d8
+#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x18) // 0x8dc
+#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x1c) // 0x8e0
+#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x20) // 0x8e4
+#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x24) // 0x8e8
+#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x28) // 0x8ec
+#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x2c) // 0x8f0
+#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x30) // 0x8f4
+#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x34) // 0x8f8
+#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x38) // 0x8fc
+#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x3c) // 0x900
+#define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x40) // 0x904
+#define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x44) // 0x908
+#define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x48) // 0x90c
+#define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x4c) // 0x910
+#define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x50) // 0x914
+#define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x54) // 0x918
+#define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x58) // 0x91c
+#define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x5c) // 0x920
+#define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x60) // 0x924
+#define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x64) // 0x928
+#define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x68) // 0x92c
+#define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x6c) // 0x930
+#define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x70) // 0x934
+#define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x74) // 0x938
+#define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x78) // 0x93c
+#define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x7c) // 0x940
+#define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x80) // 0x944
+#define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x84) // 0x948
+#define IOMUXC_FEC_FEC_COL_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x88) // 0x94c
+#define IOMUXC_FEC_FEC_CRS_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x8c) // 0x950
+#define IOMUXC_FEC_FEC_MDI_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x90) // 0x954
+#define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x94) // 0x958
+#define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x98) // 0x95c
+#define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x9c) // 0x960
+#define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa0) // 0x964
+#define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa4) // 0x968
+#define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xa8) // 0x96c
+#define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xac) // 0x970
+#define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb0) // 0x974
+#define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb4) // 0x978
+#define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xb8) // 0x97c
+#define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xbc) // 0x980
+#define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc0) // 0x984
+#define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc4) // 0x988
+#define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xc8) // 0x98c
+#define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xcc) // 0x990
+#define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd0) // 0x994
+#define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd4) // 0x998
+#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xd8) // 0x99c
+#define IOMUXC_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xdc) // 0x9a0
+#define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe0) // 0x9a4
+#define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe4) // 0x9a8
+#define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xe8) // 0x9ac
+#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xec) // 0x9b0
+#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf0) // 0x9b4
+#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf4) // 0x9b8
+#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xf8) // 0x9bc
+#define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0xfc) // 0x9c0
+#define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x100) // 0x9c4
+#define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x104) // 0x9c8
+#define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x108) // 0x9cc
+#define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x10c) // 0x9d0
+#define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x110) // 0x9d4
+#define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x114) // 0x9d8
+#define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x118) // 0x9dc
+#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x11c) // 0x9e0
+#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x120) // 0x9e4
+#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x124) // 0x9e8
+#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x128) // 0x9ec
+#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x12c) // 0x9f0
+#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x130) // 0x9f4
+#define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x134) // 0x9f8
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x138) // 0x9fc
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x13c) // 0xa00
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x140) // 0xa04
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x144) // 0xa08
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x148) // 0xa0c
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x14c) // 0xa10
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x150) // 0xa14
+#define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x154) // 0xa18
+#define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x158) // 0xa1c
+#define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x15c) // 0xa20
+#define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT (SELECT_INPUT_BASE_ADDR + 0x160) // 0xa24
+
+#define IOMUX_SW_MUX_CTL_SION 0x4
+
+#define IOMUX_PAD_SRC_LSH 0
+#define IOMUX_PAD_DSE_LSH 1
+#define IOMUX_PAD_PUE_LSH 6
+#define IOMUX_PAD_HYS_LSH 8
+
+// IOMUXC_SW_PAD_CTL, value of each field
+#define IOMUX_SW_PAD_CTL_SRE_SLOW 0 // Slow slew rate
+#define IOMUX_SW_PAD_CTL_SRE_FAST 1 // Fast slew rate
+
+#define IOMUX_SW_PAD_CTL_DSE_NORMAL 0 // Normal drive strength
+#define IOMUX_SW_PAD_CTL_DSE_MEDIUM 1 // Medium drive strength
+#define IOMUX_SW_PAD_CTL_DSE_HIGH 2 // High drive strength
+#define IOMUX_SW_PAD_CTL_DSE_MAX 3 // Maximum drive strength
+
+#define IOMUX_SW_PAD_CTL_ODE_DISABLE 0 // Disable open drain
+#define IOMUX_SW_PAD_CTL_ODE_ENABLE 1 // Enable open drain
+
+#define IOMUX_SW_PAD_CTL_PUS_100K_DOWN 0 // 100K Ohm pull down
+#define IOMUX_SW_PAD_CTL_PUS_47K_UP 1 // 47K Ohm pull up
+#define IOMUX_SW_PAD_CTL_PUS_100K_UP 2 // 100K Ohm pull up
+#define IOMUX_SW_PAD_CTL_PUS_22K_UP 3 // 22K Ohm pull up
+
+#define IOMUX_SW_PAD_CTL_PUE_KEEPER 0 // Keeper enable
+#define IOMUX_SW_PAD_CTL_PUE_PULL 1 // Pull up/down enable
+
+#define IOMUX_SW_PAD_CTL_PKE_DISABLE 0 // Pull up/down/keeper disabled
+#define IOMUX_SW_PAD_CTL_PKE_ENABLE 1 // Pull up/down/keeper enabled
+
+#define IOMUX_SW_PAD_CTL_HYS_DISABLE 0 // Disable hysteresis
+#define IOMUX_SW_PAD_CTL_HYS_ENABLE 1 // Enable hysteresis
+
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS 0 // CMOS input
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_DDR 1 // DDR input
+
+#define IOMUX_SW_PAD_CTL_HVE_LOW 0 // Low output voltage
+#define IOMUX_SW_PAD_CTL_HVE_HIGH 1 // High output voltage
+// offset
+#define IOMUX_SW_PAD_CTL_SRE_LSH 0
+#define IOMUX_SW_PAD_CTL_DSE_LSH 1
+#define IOMUX_SW_PAD_CTL_ODE_LSH 3
+#define IOMUX_SW_PAD_CTL_PUS_LSH 4
+#define IOMUX_SW_PAD_CTL_PUE_LSH 6
+#define IOMUX_SW_PAD_CTL_PKE_LSH 7
+#define IOMUX_SW_PAD_CTL_HYS_LSH 8
+#define IOMUX_SW_PAD_CTL_DDR_INPUT_LSH 9
+#define IOMUX_SW_PAD_CTL_HVE_LSH 13
+// end of pad control configuration
+
+// Mode define
+typedef enum
+{
+ IOMUX_SW_MUX_CTL_ALT0 = 0,
+ IOMUX_SW_MUX_CTL_ALT1 = 1,
+ IOMUX_SW_MUX_CTL_ALT2 = 2,
+ IOMUX_SW_MUX_CTL_ALT3 = 3,
+ IOMUX_SW_MUX_CTL_ALT4 = 4,
+ IOMUX_SW_MUX_CTL_ALT5 = 5,
+ IOMUX_SW_MUX_CTL_ALT6 = 6,
+ IOMUX_SW_MUX_CTL_ALT7 = 7
+} IOMUX_PIN_MODE;
+
+typedef enum
+{
+ IOMUX_PIN_SION_REGULAR = (0 << IOMUX_SW_MUX_CTL_SION),
+ IOMUX_PIN_SION_FORCE = (1 << IOMUX_SW_MUX_CTL_SION)
+} IOMUX_PIN_SION;
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_SLEW
+//
+// Specifies the slew rate for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_SLEW_SLOW = (IOMUX_SW_PAD_CTL_SRE_SLOW << IOMUX_SW_PAD_CTL_SRE_LSH),
+ IOMUX_PAD_SLEW_FAST = (IOMUX_SW_PAD_CTL_SRE_FAST << IOMUX_SW_PAD_CTL_SRE_LSH),
+} IOMUX_PAD_SLEW;
+
+#define IOMUX_PAD_SLEW_NULL ((IOMUX_PAD_SLEW)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_DRIVE
+//
+// Specifies the drive strength for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_DRIVE_NORMAL = (IOMUX_SW_PAD_CTL_DSE_NORMAL << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_MEDIUM = (IOMUX_SW_PAD_CTL_DSE_MEDIUM << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_HIGH = (IOMUX_SW_PAD_CTL_DSE_HIGH << IOMUX_SW_PAD_CTL_DSE_LSH),
+ IOMUX_PAD_DRIVE_MAX = (IOMUX_SW_PAD_CTL_DSE_MAX << IOMUX_SW_PAD_CTL_DSE_LSH)
+} IOMUX_PAD_DRIVE;
+
+#define IOMUX_PAD_DRIVE_NULL ((IOMUX_PAD_DRIVE)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_OPENDRAIN
+//
+// Specifies the open drain for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_OPENDRAIN_DISABLE = (IOMUX_SW_PAD_CTL_ODE_DISABLE << IOMUX_SW_PAD_CTL_ODE_LSH),
+ IOMUX_PAD_OPENDRAIN_ENABLE = (IOMUX_SW_PAD_CTL_ODE_ENABLE << IOMUX_SW_PAD_CTL_ODE_LSH)
+} IOMUX_PAD_OPENDRAIN;
+
+#define IOMUX_PAD_OPENDRAIN_NULL ((IOMUX_PAD_OPENDRAIN)0)
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_PULL
+//
+// Specifies the pull-up/pull-down/keeper configuration for a pad.
+//
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_PULL_NONE = (IOMUX_SW_PAD_CTL_PKE_DISABLE << IOMUX_SW_PAD_CTL_PKE_LSH),
+
+ IOMUX_PAD_PULL_KEEPER = (IOMUX_SW_PAD_CTL_PUE_KEEPER << IOMUX_SW_PAD_CTL_PUE_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH),
+
+ IOMUX_PAD_PULL_DOWN_100K = (IOMUX_SW_PAD_CTL_PUS_100K_DOWN << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_100K = (IOMUX_SW_PAD_CTL_PUS_100K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_47K = (IOMUX_SW_PAD_CTL_PUS_47K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH),
+
+ IOMUX_PAD_PULL_UP_22K = (IOMUX_SW_PAD_CTL_PUS_22K_UP << IOMUX_SW_PAD_CTL_PUS_LSH) |
+ (IOMUX_SW_PAD_CTL_PKE_ENABLE << IOMUX_SW_PAD_CTL_PKE_LSH) |
+ (IOMUX_SW_PAD_CTL_PUE_PULL << IOMUX_SW_PAD_CTL_PUE_LSH)
+
+} IOMUX_PAD_PULL;
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_HYSTERESIS
+//
+// Specifies the hysteresis for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_HYSTERESIS_DISABLE = (IOMUX_SW_PAD_CTL_HYS_DISABLE << IOMUX_SW_PAD_CTL_HYS_LSH),
+ IOMUX_PAD_HYSTERESIS_ENABLE = (IOMUX_SW_PAD_CTL_HYS_ENABLE << IOMUX_SW_PAD_CTL_HYS_LSH)
+} IOMUX_PAD_HYSTERESIS;
+
+#define IOMUX_PAD_HYSTERESIS_NULL ((IOMUX_PAD_HYSTERESIS)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_INMODE
+//
+// Specifies the input mode (DDR/CMOS) for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_INMODE_CMOS = (IOMUX_SW_PAD_CTL_DDR_INPUT_CMOS << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH),
+ IOMUX_PAD_INMODE_DDR = (IOMUX_SW_PAD_CTL_DDR_INPUT_DDR << IOMUX_SW_PAD_CTL_DDR_INPUT_LSH)
+} IOMUX_PAD_INMODE;
+
+#define IOMUX_PAD_INMODE_NULL ((IOMUX_PAD_INMODE)0)
+
+//-----------------------------------------------------------------------------
+//
+// Type: IOMUX_PAD_OUTVOLT
+//
+// Specifies the output voltage for a pad.
+//
+//-----------------------------------------------------------------------------
+typedef enum
+{
+ IOMUX_PAD_OUTVOLT_LOW = (IOMUX_SW_PAD_CTL_HVE_LOW << IOMUX_SW_PAD_CTL_HVE_LSH),
+ IOMUX_PAD_OUTVOLT_HIGH = (IOMUX_SW_PAD_CTL_HVE_HIGH << IOMUX_SW_PAD_CTL_HVE_LSH)
+} IOMUX_PAD_OUTVOLT;
+
+#define IOMUX_PAD_OUTVOLT_NULL ((IOMUX_PAD_OUTVOLT)0)
+
+#define CONFIG_PIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val
+#define CONFIG_DAISY_CHAIN(Reg_Addr, Val) *(volatile unsigned int *)Reg_Addr=Val
+#define CONFIG_PAD(Reg_Addr,Val) *(volatile unsigned int *)Reg_Addr=Val
+
+#endif
#include <redboot.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/plf_mmap.h>
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
#include <cyg/hal/hal_cache.h>
-int gcd(int m, int n);
+#include "hab_super_root.h"
+
+//#define CMD_CLOCK_DEBUG
+#ifdef CMD_CLOCK_DEBUG
+#define dbg(fmt...) \
+ CYG_MACRO_START \
+ diag_printf(fmt); \
+ CYG_MACRO_END
+#else
+#define dbg(fmt...) CYG_EMPTY_STATEMENT
+#endif
-typedef unsigned long long u64;
-typedef unsigned int u32;
-typedef unsigned short u16;
-typedef unsigned char u8;
-
-#define SZ_DEC_1M 1000000
-#define PLL_PD_MAX 16 //actual pd+1
-#define PLL_MFI_MAX 15
-#define PLL_MFI_MIN 5
-#define ARM_DIV_MAX 8
-#define IPG_DIV_MAX 4
-#define AHB_DIV_MAX 8
-#define EMI_DIV_MAX 8
-#define NFC_DIV_MAX 8
-
-#define REF_IN_CLK_NUM 4
+int gcd(int m, int n);
+extern void increase_core_voltage(bool i);
+
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+#define SZ_DEC_1M 1000000
+#define PLL_PD_MAX 16 //actual pd+1
+#define PLL_MFI_MAX 15
+#define PLL_MFI_MIN 5
+#define ARM_DIV_MAX 8
+#define IPG_DIV_MAX 4
+#define AHB_DIV_MAX 8
+#define EMI_DIV_MAX 8
+#define NFC_DIV_MAX 8
+
+#define REF_IN_CLK_NUM 4
struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
+ u32 ref_clk_hz;
+ u32 mfd;
};
+
const struct fixed_pll_mfd fixed_mfd[REF_IN_CLK_NUM] = {
- {0, 0}, // reserved
- {0, 0}, // reserved
- {FREQ_24MHZ, 24 * 16}, // 384
- {0, 0}, // reserved
+ { 0, 0, }, // reserved
+ { 0, 0, }, // reserved
+ { FREQ_24MHZ, 24 * 16, }, // internal osc
+ { FREQ_32768HZ, 1024, }, // FPM
};
struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
+ u32 pd;
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
};
-#define PLL_FREQ_MAX(_ref_clk_) (4 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
-#define MAX_DDR_CLK 200000000
-#define AHB_CLK_MAX 133333333
-#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX 25000000
+#define PLL_FREQ_MAX(_ref_clk_) (4 * _ref_clk_ * PLL_MFI_MAX)
+#define PLL_FREQ_MIN(_ref_clk_) ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define MAX_DDR_CLK 220000000
+#define AHB_CLK_MAX 133333333
+#define IPG_CLK_MAX (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX 25000000
// IPU-HSP clock is independent of the HCLK and can go up to 177MHz but requires
// higher voltage support. For simplicity, limit it to 133MHz
-#define HSP_CLK_MAX 133333333
+#define HSP_CLK_MAX 133333333
-#define ERR_WRONG_CLK -1
-#define ERR_NO_MFI -2
-#define ERR_NO_MFN -3
-#define ERR_NO_PD -4
-#define ERR_NO_PRESC -5
-#define ERR_NO_AHB_DIV -6
+#define ERR_WRONG_CLK (-1)
+#define ERR_NO_MFI (-2)
+#define ERR_NO_MFN (-3)
+#define ERR_NO_PD (-4)
+#define ERR_NO_PRESC (-5)
+#define ERR_NO_AHB_DIV (-6)
u32 pll_clock(enum plls pll);
u32 get_main_clock(enum main_clocks clk);
static volatile u32 *pll_base[] =
{
- REG32_PTR(PLL1_BASE_ADDR),
- REG32_PTR(PLL2_BASE_ADDR),
- REG32_PTR(PLL3_BASE_ADDR),
+ REG32_PTR(PLL1_BASE_ADDR),
+ REG32_PTR(PLL2_BASE_ADDR),
+ REG32_PTR(PLL3_BASE_ADDR),
};
#define NOT_ON_VAL 0xDEADBEEF
static void clock_setup(int argc, char *argv[]);
RedBoot_cmd("clock",
- "Setup/Display clock\nSyntax:",
- "[<core clock in MHz> :<DDR clock in MHz>] \n\n\
- Examples:\n\
- [clock] -> Show various clocks\n\
- [clock 665] -> Core=665 \n\
- [clock 800:133] -> Core=800 DDR=133 \n\
- [clock :166] -> Core=no change DDR=166 \n",
- clock_setup
- );
+ "Setup/Display clock\nSyntax:",
+ "[<core clock in MHz> :<DDR clock in MHz>]\n\n"
+ " Examples:\n"
+ " [clock] -> Show various clocks\n"
+ " [clock 665] -> Core=665\n"
+ " [clock 800:133] -> Core=800 DDR=133\n"
+ " [clock :166] -> Core=no change DDR=166\n",
+ clock_setup
+ );
/*!
* This is to calculate various parameters based on reference clock and
*/
int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
{
- u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
-
- // make sure targeted freq is in the valid range. Otherwise the
- // following calculation might be wrong!!!
- if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
- return ERR_WRONG_CLK;
- for (i = 0; ; i++) {
- if (i == REF_IN_CLK_NUM)
- return ERR_WRONG_CLK;
- if (fixed_mfd[i].ref_clk_hz == ref) {
- mfd = fixed_mfd[i].mfd;
- break;
- }
- }
-
- // Use n_target and n_ref to avoid overflow
- for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- mfi = (n_target * pd) / (4 * n_ref);
- if (mfi > PLL_MFI_MAX) {
- return ERR_NO_MFI;
- } else if (mfi < 5) {
- continue;
- }
- break;
- }
- // Now got pd and mfi already
- mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
-#ifdef CMD_CLOCK_DEBUG
- diag_printf("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
-#endif
- i = 1;
- if (mfn != 0)
- i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- pll->mfn = (u32)(mfn / i);
- pll->mfd = (u32)(mfd / i);
- return 0;
+ u64 pd, mfi = 1, mfn, mfd, n_target = target, n_ref = ref, i;
+
+ // make sure targeted freq is in the valid range. Otherwise the
+ // following calculation might be wrong!!!
+ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref))
+ return ERR_WRONG_CLK;
+ for (i = 0; ; i++) {
+ if (i == REF_IN_CLK_NUM)
+ return ERR_WRONG_CLK;
+ if (fixed_mfd[i].ref_clk_hz == ref) {
+ mfd = fixed_mfd[i].mfd;
+ break;
+ }
+ }
+
+ // Use n_target and n_ref to avoid overflow
+ for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+ mfi = (n_target * pd) / (4 * n_ref);
+ if (mfi > PLL_MFI_MAX) {
+ return ERR_NO_MFI;
+ } else if (mfi < 5) {
+ continue;
+ }
+ break;
+ }
+ // Now got pd and mfi already
+ mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+
+ dbg("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+ __LINE__, ref, (u32)n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
+
+ i = 1;
+ if (mfn != 0)
+ i = gcd(mfd, mfn);
+ pll->pd = (u32)pd;
+ pll->mfi = (u32)mfi;
+ pll->mfn = (u32)(mfn / i);
+ pll->mfd = (u32)(mfd / i);
+ return 0;
}
/*!
*/
u32 get_lp_apm(void)
{
- u32 ret_val = 0;
- u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
-
- if (((ccsr >> 9) & 1) == 0) {
- ret_val = FREQ_24MHZ;
- } else {
- ret_val = FREQ_32768HZ;
- }
- return ret_val;
+ u32 ret_val;
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0) {
+ ret_val = FREQ_24MHZ;
+ } else {
+ ret_val = FREQ_32768HZ;
+ }
+ dbg("%s: CCSR[%08lx]=%08x freq=%u.%03uMHz\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CCSR, ccsr, ret_val / 1000000, ret_val / 1000 % 1000);
+ return ret_val;
}
/*!
*/
u32 get_periph_clk(void)
{
- u32 ret_val = 0, clk_sel;
-
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
-
- if (((cbcdr >> 25) & 1) == 0) {
- ret_val = pll_clock(PLL2);
- } else {
- clk_sel = (cbcmr >> 12) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1);
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL3);
- } else if (clk_sel == 2) {
- ret_val = get_lp_apm();
- }
- }
- return ret_val;
+ u32 ret_val, clk_sel;
+
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+
+ if (!(cbcdr & (1 << 25))) {
+ ret_val = pll_clock(PLL2);
+ dbg("%s: CBCDR[%08lx]=%08x CBCMR[%08lx]=%08x freq=%u.%03uMHz\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CBCDR, cbcdr,
+ CCM_BASE_ADDR + CLKCTL_CBCMR, cbcmr,
+ ret_val / 1000000, ret_val / 1000 % 1000);
+ } else {
+ clk_sel = (cbcmr >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL3);
+ } else if (clk_sel == 2) {
+ ret_val = get_lp_apm();
+ } else {
+ diag_printf("Invalid CBCMR[CLK_SEL]: %d\n", clk_sel);
+ return ERR_WRONG_CLK;
+ }
+ dbg("%s: CBCDR[%08lx]=%08x CBCMR[%08lx]=%08x clk_sel=%d freq=%u.%03uMHz\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CBCDR, cbcdr,
+ CCM_BASE_ADDR + CLKCTL_CBCMR, cbcmr,
+ clk_sel, ret_val / 1000000, ret_val / 1000 % 1000);
+ }
+ return ret_val;
}
/*!
*/
int configure_clock(u32 ref, u32 core_clk, u32 emi_clk)
{
-
- u32 pll, clk_src;
- struct pll_param pll_param;
- int ret, clk_sel, div = 1, div_core = 1, div_per = 1, shift = 0;
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
- u32 icgc = readl(PLATFORM_BASE_ADDR + PLATFORM_ICGC);
-
- if (core_clk != 0) {
- // assume pll default to core clock first
- pll = core_clk;
- if ((ret = calc_pll_params(ref, pll, &pll_param)) != 0) {
- diag_printf("can't find pll parameters: %d\n", ret);
- return ret;
- }
-#ifdef CMD_CLOCK_DEBUG
- diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
- ref, pll, pll_param.pd, pll_param.mfi, pll_param.mfn, pll_param.mfd);
-#endif
-
- /* Applies for TO 2 only */
- if (((cbcdr >> 30) & 0x1) == 0x1) {
- /* Disable IPU and HSC dividers */
- writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
- /* Switch DDR to different source */
- writel(cbcdr & ~0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
- }
-
- /* Switch ARM to PLL2 clock */
- writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
-
- if ((core_clk > 665000000) && (core_clk <= 800000000)) {
- div_per = 5;
- } else if (core_clk > 800000000) {
- div_per = 6;
- } else {
- div_per = 4;
- }
-
- if (core_clk > 800000000) {
- div_core = 3;
- increase_core_voltage(true);
- } else {
- div_core = 2;
- increase_core_voltage(false);
- }
-
- // adjust pll settings
- writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
- PLL1_BASE_ADDR + PLL_DP_OP);
- writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_MFN);
- writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_MFD);
- writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
- PLL1_BASE_ADDR + PLL_DP_HFS_OP);
- writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_HFS_MFN);
- writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_HFS_MFD);
-
- icgc &= ~(0x77);
- icgc |= (div_core << 4);
- icgc |= div_per;
- /* Set the platform clock dividers */
- writel(icgc, PLATFORM_BASE_ADDR + PLATFORM_ICGC);
- /* Switch ARM back to PLL1 */
- writel((ccsr & ~0x4), CCM_BASE_ADDR + CLKCTL_CCSR);
- /* Applies for TO 2 only */
- if (((cbcdr >> 30) & 0x1) == 0x1) {
- /* Disable IPU and HSC dividers */
- writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
- /* Switch DDR back to PLL1 */
- writel(cbcdr | 0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
- if (emi_clk == 0) {
- /* Keep EMI clock to the max if not specified */
- emi_clk = 200000000;
- }
- }
- }
-
- if (emi_clk != 0) {
- /* Applies for TO 2 only */
- if (((cbcdr >> 30) & 0x1) == 0x1) {
- clk_src = pll_clock(PLL1);
- shift = 27;
- } else {
- clk_src = get_periph_clk();
- /* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
- if (clk_sel == 0) {
- shift = 16;
- } else if (clk_sel == 1) {
- shift = 19;
- } else if (clk_sel == 2) {
- shift = 22;
- } else if (clk_sel == 3) {
- shift = 10;
- }
- }
- if ((clk_src % emi_clk) == 0)
- div = clk_src / emi_clk;
- else
- div = (clk_src / emi_clk) + 1;
- if (div > 8)
- div = 8;
-
- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- /* Disable IPU and HSC dividers */
- writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
- writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
- while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
- writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
- }
- return 0;
+ u32 pll, clk_src;
+ struct pll_param pll_param;
+ int ret, clk_sel, div = 1, div_core = 1, div_per = 1, shift = 0;
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+ u32 ccsr = readl(CCM_BASE_ADDR + CLKCTL_CCSR);
+ u32 icgc = readl(PLATFORM_BASE_ADDR + PLATFORM_ICGC);
+
+ dbg("%s: cbcdr[%08lx]=%08x\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CBCDR, cbcdr);
+ dbg("%s: cbcmr[%08lx]=%08x\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CBCMR, cbcdr);
+ dbg("%s: ccsr[%08lx]=%08x\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CCSR, cbcdr);
+ dbg("%s: icgc[%08lx]=%08x\n", __FUNCTION__,
+ PLATFORM_BASE_ADDR + PLATFORM_ICGC, icgc);
+
+ if (core_clk != 0) {
+ // assume pll default to core clock first
+ pll = core_clk;
+ if ((ret = calc_pll_params(ref, pll, &pll_param)) != 0) {
+ diag_printf("can't find pll parameters: %d\n", ret);
+ return ret;
+ }
+
+ dbg("%s: ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n", __FUNCTION__,
+ ref, pll, pll_param.pd, pll_param.mfi, pll_param.mfn, pll_param.mfd);
+
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Switch DDR to different source */
+ writel(cbcdr & ~0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+
+ /* Switch ARM to PLL2 clock */
+ writel(ccsr | 0x4, CCM_BASE_ADDR + CLKCTL_CCSR);
+
+ if ((core_clk > 665000000) && (core_clk <= 800000000)) {
+ div_per = 5;
+ } else if (core_clk > 800000000) {
+ div_per = 6;
+ } else {
+ div_per = 4;
+ }
+
+ if (core_clk > 800000000) {
+ div_core = 3;
+ increase_core_voltage(true);
+ } else {
+ div_core = 2;
+ increase_core_voltage(false);
+ }
+
+ // adjust pll settings
+ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
+ PLL1_BASE_ADDR + PLL_DP_OP);
+ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_MFN);
+ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_MFD);
+ writel(((pll_param.pd - 1) << 0) | (pll_param.mfi << 4),
+ PLL1_BASE_ADDR + PLL_DP_HFS_OP);
+ writel(pll_param.mfn, PLL1_BASE_ADDR + PLL_DP_HFS_MFN);
+ writel(pll_param.mfd - 1, PLL1_BASE_ADDR + PLL_DP_HFS_MFD);
+
+ icgc &= ~0x77;
+ icgc |= div_core << 4;
+ icgc |= div_per;
+ /* Set the platform clock dividers */
+ writel(icgc, PLATFORM_BASE_ADDR + PLATFORM_ICGC);
+ /* Switch ARM back to PLL1 */
+ writel((ccsr & ~0x4), CCM_BASE_ADDR + CLKCTL_CCSR);
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ /* Switch DDR back to PLL1 */
+ writel(cbcdr | 0x40000000, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ if (emi_clk == 0) {
+ /* Keep EMI clock to the max if not specified */
+ emi_clk = 200000000;
+ }
+ }
+ }
+
+ if (emi_clk != 0) {
+ /* Applies for TO 2 only */
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ clk_src = pll_clock(PLL1);
+ shift = 27;
+ } else {
+ clk_src = get_periph_clk();
+ /* Find DDR clock input */
+ clk_sel = (cbcmr >> 10) & 0x3;
+ if (clk_sel == 0) {
+ shift = 16;
+ } else if (clk_sel == 1) {
+ shift = 19;
+ } else if (clk_sel == 2) {
+ shift = 22;
+ } else if (clk_sel == 3) {
+ shift = 10;
+ }
+ }
+ if ((clk_src % emi_clk) == 0)
+ div = clk_src / emi_clk;
+ else
+ div = (clk_src / emi_clk) + 1;
+ if (div > 8)
+ div = 8;
+
+ cbcdr &= ~(0x7 << shift);
+ cbcdr |= (div - 1) << shift;
+ dbg("%s@%d: \n", __FUNCTION__, __LINE__);
+
+ /* Disable IPU and HSC dividers */
+ writel(0x60000, CCM_BASE_ADDR + CLKCTL_CCDR);
+ writel(cbcdr, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0);
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+ return 0;
}
static void clock_setup(int argc,char *argv[])
{
-
- u32 i, core_clk, ddr_clk, data[3];
- unsigned long temp;
- int ret;
-
- if (argc == 1)
- goto print_clock;
-
- for (i = 0; i < 2; i++) {
- if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- data[i] = temp;
- }
-
- core_clk = data[0] * SZ_DEC_1M;
- ddr_clk = data[1] * SZ_DEC_1M;
-
- if (core_clk != 0) {
- if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) {
- diag_printf("Targeted core clock should be within [%d - %d]\n",
- PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK));
- return;
- }
- }
-
- if (ddr_clk != 0) {
- if (ddr_clk > MAX_DDR_CLK) {
- diag_printf("DDR clock should be less than %d MHz, assuming max value \n", (MAX_DDR_CLK / SZ_DEC_1M));
- ddr_clk = MAX_DDR_CLK;
- }
- }
-
- // stop the serial to be ready to adjust the clock
- hal_delay_us(100000);
- cyg_hal_plf_serial_stop();
- // adjust the clock
- ret = configure_clock(PLL_REF_CLK, core_clk, ddr_clk);
- // restart the serial driver
- cyg_hal_plf_serial_init();
- hal_delay_us(100000);
-
- if (ret != 0) {
- diag_printf("Failed to setup clock: %d\n", ret);
- return;
- }
- diag_printf("\n<<<New clock setting>>>\n");
-
- // Now printing clocks
+ u32 i, core_clk, ddr_clk, data[3];
+ unsigned long temp;
+ int ret;
+
+ if (argc == 1)
+ goto print_clock;
+
+ for (i = 0; i < 2; i++) {
+ if (!parse_num(*(&argv[1]), &temp, &argv[1], ":")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ data[i] = temp;
+ }
+
+ core_clk = data[0] * SZ_DEC_1M;
+ ddr_clk = data[1] * SZ_DEC_1M;
+
+ if (core_clk != 0) {
+ if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) {
+ diag_printf("Targeted core clock should be within [%d - %d]\n",
+ PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK));
+ return;
+ }
+ }
+
+ if (ddr_clk != 0) {
+ if (ddr_clk > MAX_DDR_CLK) {
+ diag_printf("DDR clock should be less than %d MHz, assuming max value\n", (MAX_DDR_CLK / SZ_DEC_1M));
+ ddr_clk = MAX_DDR_CLK;
+ }
+ }
+
+#if 1
+ // stop the serial to be ready to adjust the clock
+ hal_delay_us(100000);
+ cyg_hal_plf_serial_stop();
+ // adjust the clock
+#endif
+ ret = configure_clock(PLL_REF_CLK, core_clk, ddr_clk);
+ // restart the serial driver
+ cyg_hal_plf_serial_init();
+ hal_delay_us(100000);
+
+ if (ret != 0) {
+ diag_printf("Failed to setup clock: %d\n", ret);
+ return;
+ }
+ diag_printf("\n<<<New clock setting>>>\n");
+
+ // Now printing clocks
print_clock:
- diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
- diag_printf("========================================\n");
- diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
- pll_clock(PLL3));
- diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
- diag_printf("========================================================\n");
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_main_clock(CPU_CLK),
- get_main_clock(AHB_CLK),
- get_main_clock(IPG_CLK),
- get_main_clock(DDR_CLK));
-
- diag_printf("NFC\t\tUSB\t\tIPG_PER_CLK\n");
- diag_printf("========================================\n");
- diag_printf("%-16d%-16d%-16d\n\n",
- get_main_clock(NFC_CLK),
- get_main_clock(USB_CLK),
- get_main_clock(IPG_PER_CLK));
-
- diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tSPI\n");
- diag_printf("===========================================");
- diag_printf("=============\n");
-
- diag_printf("%-16d%-16d%-16d%-16d\n\n",
- get_peri_clock(UART1_BAUD),
- get_peri_clock(SSI1_BAUD),
- get_peri_clock(SSI2_BAUD),
- get_peri_clock(SPI1_CLK));
+ diag_printf("\nPLL1\t\tPLL2\t\tPLL3\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n", pll_clock(PLL1), pll_clock(PLL2),
+ pll_clock(PLL3));
+ diag_printf("CPU\t\tAHB\t\tIPG\t\tEMI_CLK\n");
+ diag_printf("========================================================\n");
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_main_clock(CPU_CLK),
+ get_main_clock(AHB_CLK),
+ get_main_clock(IPG_CLK),
+ get_main_clock(DDR_CLK));
+
+ diag_printf("NFC\t\tUSB\t\tIPG_PER_CLK\n");
+ diag_printf("========================================\n");
+ diag_printf("%-16d%-16d%-16d\n\n",
+ get_main_clock(NFC_CLK),
+ get_main_clock(USB_CLK),
+ get_main_clock(IPG_PER_CLK));
+
+ diag_printf("UART1-3\t\tSSI1\t\tSSI2\t\tSPI\n");
+ diag_printf("===========================================");
+ diag_printf("=============\n");
+
+ diag_printf("%-16d%-16d%-16d%-16d\n\n",
+ get_peri_clock(UART1_BAUD),
+ get_peri_clock(SSI1_BAUD),
+ get_peri_clock(SSI2_BAUD),
+ get_peri_clock(SPI1_CLK));
#if 0
- diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
- if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
- diag_printf(", EPIT");
- }
- if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
- diag_printf("GPT,");
- }
+ diag_printf("IPG_PERCLK as baud clock for: UART1-5, I2C, OWIRE, SDHC");
+ if (((readl(EPIT1_BASE_ADDR) >> 24) & 0x3) == 0x2) {
+ diag_printf(", EPIT");
+ }
+ if (((readl(GPT1_BASE_ADDR) >> 6) & 0x7) == 0x2) {
+ diag_printf("GPT,");
+ }
#endif
- diag_printf("\n");
+ diag_printf("\n");
}
*/
u32 pll_clock(enum plls pll)
{
- u64 mfi, mfn, mfd, pdf, ref_clk, pll_out, sign;
- u64 dp_ctrl, dp_op, dp_mfd, dp_mfn, clk_sel;
- u8 dbl = 0;
-
- dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
- clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
- ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
-
- if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
- dp_op = pll_base[pll][PLL_DP_OP >> 2];
- dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
- dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
- } else {
- dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
- dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
- dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
- }
- pdf = dp_op & 0xF;
- mfi = (dp_op >> 4) & 0xF;
- mfi = (mfi <= 5) ? 5: mfi;
- mfd = dp_mfd & 0x07FFFFFF;
- mfn = dp_mfn & 0x07FFFFFF;
-
- sign = (mfn < 0x4000000) ? 0: 1;
- mfn = (mfn <= 0x4000000) ? mfn: (0x8000000 - mfn);
-
- dbl = ((dp_ctrl >> 12) & 0x1) + 1;
-
- dbl = dbl * 2;
- if (sign == 0) {
- pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
- } else {
- pll_out = (dbl * ref_clk * mfi - ((dbl * ref_clk * mfn) / (mfd + 1))) /
- (pdf + 1);
- }
-
- return (u32)pll_out;
+ u64 ref_clk;
+ u32 mfi, mfn, mfd, pdf, pll_out, sign;
+ u32 dp_ctrl, dp_op, dp_mfd, dp_mfn;
+ int clk_sel;
+ int dbl;
+
+ dp_ctrl = pll_base[pll][PLL_DP_CTL >> 2];
+ clk_sel = MXC_GET_FIELD(dp_ctrl, 2, 8);
+ ref_clk = fixed_mfd[clk_sel].ref_clk_hz;
+
+ dbg("clk_sel=%d\n", clk_sel);
+
+ if ((pll_base[pll][PLL_DP_CTL >> 2] & 0x80) == 0) {
+ dp_op = pll_base[pll][PLL_DP_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_MFN >> 2];
+ } else {
+ dp_op = pll_base[pll][PLL_DP_HFS_OP >> 2];
+ dp_mfd = pll_base[pll][PLL_DP_HFS_MFD >> 2];
+ dp_mfn = pll_base[pll][PLL_DP_HFS_MFN >> 2];
+ }
+ pdf = dp_op & 0xF;
+ mfi = (dp_op >> 4) & 0xF;
+ mfi = (mfi <= 5) ? 5: mfi;
+ mfd = dp_mfd & 0x07FFFFFF;
+ mfn = dp_mfn & 0x07FFFFFF;
+
+ sign = (mfn < 0x4000000) ? 1 : -1;
+ mfn = (mfn < 0x4000000) ? mfn : (0x8000000 - mfn);
+
+ dbl = 2 * (((dp_ctrl >> 12) & 0x1) + 1);
+
+ dbg("%s: ref=%llu.%03lluMHz, dbl=%d, pd=%d, mfi=%d, mfn=%s%d, mfd=%d\n",
+ __FUNCTION__, ref_clk / 1000000, ref_clk / 1000 % 1000,
+ dbl, pdf, mfi, sign ? "-" : "", mfn, mfd);
+
+ pll_out = (dbl * ref_clk * mfi + ((dbl * ref_clk * sign * mfn) / (mfd + 1))) /
+ (pdf + 1);
+
+ return pll_out;
}
/*!
*/
u32 get_emi_core_clk(void)
{
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- u32 clk_sel = 0, max_pdf = 0, peri_clk = 0, ahb_clk = 0;
- u32 ret_val = 0;
-
- max_pdf = (cbcdr >> 10) & 0x7;
- peri_clk = get_periph_clk();
- ahb_clk = peri_clk / (max_pdf + 1);
-
- clk_sel = (cbcdr >> 26) & 1;
- if (clk_sel == 0) {
- ret_val = peri_clk;
- } else {
- ret_val = ahb_clk ;
- }
- return ret_val;
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 clk_sel, max_pdf, peri_clk, ahb_clk;
+ u32 ret_val;
+
+ max_pdf = (cbcdr >> 10) & 0x7;
+ peri_clk = get_periph_clk();
+ ahb_clk = peri_clk / (max_pdf + 1);
+
+ clk_sel = (cbcdr >> 26) & 1;
+ if (clk_sel == 0) {
+ ret_val = peri_clk;
+ } else {
+ ret_val = ahb_clk ;
+ }
+ dbg("%s: CBCDR[%08lx]=%08x freq=%u.%03uMHz\n", __FUNCTION__,
+ CCM_BASE_ADDR + CLKCTL_CBCDR, cbcdr, ret_val / 1000000, ret_val / 1000 % 1000);
+ return ret_val;
}
/*!
*/
u32 get_main_clock(enum main_clocks clk)
{
- u32 pdf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
- u32 pll, ret_val = 0;
- u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
- u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
- u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
- u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
- u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
-
- switch (clk) {
- case CPU_CLK:
- pdf = cacrr & 0x7;
- pll = pll_clock(PLL1);
- ret_val = pll / (pdf + 1);
- break;
- case AHB_CLK:
- max_pdf = (cbcdr >> 10) & 0x7;
- pll = get_periph_clk();
- ret_val = pll / (max_pdf + 1);
- break;
- case IPG_CLK:
- max_pdf = (cbcdr >> 10) & 0x7;
- ipg_pdf = (cbcdr >> 8) & 0x3;
- pll = get_periph_clk();
- ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
- break;
- case IPG_PER_CLK:
- clk_sel = cbcmr & 1;
- if (clk_sel == 0) {
- clk_sel = (cbcmr >> 1) & 1;
- pdf = (((cbcdr >> 6) & 3) + 1) * (((cbcdr >> 3) & 7) + 1) * ((cbcdr & 7) + 1);
- if (clk_sel == 0) {
- ret_val = get_periph_clk() / pdf;
- } else {
- ret_val = get_lp_apm();
- }
- } else {
- /* Same as IPG_CLK */
- max_pdf = (cbcdr >> 10) & 0x7;
- ipg_pdf = (cbcdr >> 8) & 0x3;
- pll = get_periph_clk();
- ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
- }
- break;
- case DDR_CLK:
- if (((cbcdr >> 30) & 0x1) == 0x1) {
- pll = pll_clock(PLL1);
- pdf = (cbcdr >> 27) & 0x7;
- } else {
- clk_sel = (cbcmr >> 10) & 3;
- pll = get_periph_clk();
- if (clk_sel == 0) {
- /* AXI A */
- pdf = (cbcdr >> 16) & 0x7;
- } else if (clk_sel == 1) {
- /* AXI B */
- pdf = (cbcdr >> 19) & 0x7;
- } else if (clk_sel == 2) {
- /* EMI SLOW CLOCK ROOT */
- pll = get_emi_core_clk();
- pdf = (cbcdr >> 22) & 0x7;
- } else if (clk_sel == 3) {
- /* AHB CLOCK */
- pdf = (cbcdr >> 10) & 0x7;
- }
- }
-
- ret_val = pll / (pdf + 1);
- break;
- case NFC_CLK:
- pdf = (cbcdr >> 22) & 0x7;
- nfc_pdf = (cbcdr >> 13) & 0x7;
- pll = get_emi_core_clk();
- ret_val = pll / ((pdf + 1) * (nfc_pdf + 1));
- break;
- case USB_CLK:
- clk_sel = (cscmr1 >> 22) & 3;
- if (clk_sel == 0) {
- pll = pll_clock(PLL1);
- } else if (clk_sel == 1) {
- pll = pll_clock(PLL2);
- } else if (clk_sel == 2) {
- pll = pll_clock(PLL3);
- } else if (clk_sel == 3) {
- pll = get_lp_apm();
- }
- pdf = (cscdr1 >> 8) & 0x7;
- max_pdf = (cscdr1 >> 6) & 0x3;
- ret_val = pll / ((pdf + 1) * (max_pdf + 1));
- break;
- default:
- diag_printf("Unknown clock: %d\n", clk);
- break;
- }
-
- return ret_val;
+ u32 pdf, max_pdf, ipg_pdf, nfc_pdf, clk_sel;
+ u32 pll, ret_val;
+ u32 cacrr = readl(CCM_BASE_ADDR + CLKCTL_CACRR);
+ u32 cbcdr = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ u32 cbcmr = readl(CCM_BASE_ADDR + CLKCTL_CBCMR);
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+
+ dbg("%s: \n", __FUNCTION__);
+ switch (clk) {
+ case CPU_CLK:
+ pdf = cacrr & 0x7;
+ pll = pll_clock(PLL1);
+ ret_val = pll / (pdf + 1);
+ break;
+ case AHB_CLK:
+ max_pdf = (cbcdr >> 10) & 0x7;
+ pll = get_periph_clk();
+ ret_val = pll / (max_pdf + 1);
+ break;
+ case IPG_CLK:
+ max_pdf = (cbcdr >> 10) & 0x7;
+ ipg_pdf = (cbcdr >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ break;
+ case IPG_PER_CLK:
+ clk_sel = cbcmr & 1;
+ if (clk_sel == 0) {
+ clk_sel = (cbcmr >> 1) & 1;
+ pdf = (((cbcdr >> 6) & 3) + 1) * (((cbcdr >> 3) & 7) + 1) * ((cbcdr & 7) + 1);
+ if (clk_sel == 0) {
+ ret_val = get_periph_clk() / pdf;
+ } else {
+ ret_val = get_lp_apm();
+ }
+ } else {
+ /* Same as IPG_CLK */
+ max_pdf = (cbcdr >> 10) & 0x7;
+ ipg_pdf = (cbcdr >> 8) & 0x3;
+ pll = get_periph_clk();
+ ret_val = pll / ((max_pdf + 1) * (ipg_pdf + 1));
+ }
+ break;
+ case DDR_CLK:
+ if (((cbcdr >> 30) & 0x1) == 0x1) {
+ pll = pll_clock(PLL1);
+ pdf = (cbcdr >> 27) & 0x7;
+ } else {
+ clk_sel = (cbcmr >> 10) & 3;
+ pll = get_periph_clk();
+ if (clk_sel == 0) {
+ /* AXI A */
+ pdf = (cbcdr >> 16) & 0x7;
+ } else if (clk_sel == 1) {
+ /* AXI B */
+ pdf = (cbcdr >> 19) & 0x7;
+ } else if (clk_sel == 2) {
+ /* EMI SLOW CLOCK ROOT */
+ pll = get_emi_core_clk();
+ pdf = (cbcdr >> 22) & 0x7;
+ } else if (clk_sel == 3) {
+ /* AHB CLOCK */
+ pdf = (cbcdr >> 10) & 0x7;
+ }
+ }
+
+ ret_val = pll / (pdf + 1);
+ break;
+ case NFC_CLK:
+ pdf = (cbcdr >> 22) & 0x7;
+ nfc_pdf = (cbcdr >> 13) & 0x7;
+ pll = get_emi_core_clk();
+ ret_val = pll / ((pdf + 1) * (nfc_pdf + 1));
+ break;
+ case USB_CLK:
+ clk_sel = (cscmr1 >> 22) & 3;
+ if (clk_sel == 0) {
+ pll = pll_clock(PLL1);
+ } else if (clk_sel == 1) {
+ pll = pll_clock(PLL2);
+ } else if (clk_sel == 2) {
+ pll = pll_clock(PLL3);
+ } else if (clk_sel == 3) {
+ pll = get_lp_apm();
+ }
+ pdf = (cscdr1 >> 8) & 0x7;
+ max_pdf = (cscdr1 >> 6) & 0x3;
+ ret_val = pll / ((pdf + 1) * (max_pdf + 1));
+ break;
+ default:
+ diag_printf("Unknown clock: %d\n", clk);
+ return ERR_WRONG_CLK;
+ }
+
+ return ret_val;
}
/*!
*/
u32 get_peri_clock(enum peri_clocks clk)
{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
- u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
- u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
- u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
- u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
-
- switch (clk) {
- case UART1_BAUD:
- case UART2_BAUD:
- case UART3_BAUD:
- pre_pdf = (cscdr1 >> 3) & 0x7;
- pdf = cscdr1 & 0x7;
- clk_sel = (cscmr1 >> 24) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
- }
- break;
- case SSI1_BAUD:
- pre_pdf = (cs1cdr >> 6) & 0x7;
- pdf = cs1cdr & 0x3F;
- clk_sel = (cscmr1 >> 14) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
- }
- break;
- case SSI2_BAUD:
- pre_pdf = (cs2cdr >> 6) & 0x7;
- pdf = cs2cdr & 0x3F;
- clk_sel = (cscmr1 >> 12) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 0x2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
- }
- break;
- case SPI1_CLK:
- case SPI2_CLK:
- pre_pdf = (cscdr2 >> 25) & 0x7;
- pdf = (cscdr2 >> 19) & 0x3F;
- clk_sel = (cscmr1 >> 4) & 3;
- if (clk_sel == 0) {
- ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 1) {
- ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
- } else if (clk_sel == 2) {
- ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
- } else {
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
- }
- break;
- default:
- diag_printf("%s(): This clock: %d not supported yet \n",
- __FUNCTION__, clk);
- break;
- }
-
- return ret_val;
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCMR1);
+ u32 cscdr1 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR1);
+ u32 cscdr2 = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2);
+ u32 cs1cdr = readl(CCM_BASE_ADDR + CLKCTL_CS1CDR);
+ u32 cs2cdr = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
+
+ dbg("%s: \n", __FUNCTION__);
+ switch (clk) {
+ case UART1_BAUD:
+ case UART2_BAUD:
+ case UART3_BAUD:
+ pre_pdf = (cscdr1 >> 3) & 0x7;
+ pdf = cscdr1 & 0x7;
+ clk_sel = (cscmr1 >> 24) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI1_BAUD:
+ pre_pdf = (cs1cdr >> 6) & 0x7;
+ pdf = cs1cdr & 0x3F;
+ clk_sel = (cscmr1 >> 14) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SSI2_BAUD:
+ pre_pdf = (cs2cdr >> 6) & 0x7;
+ pdf = cs2cdr & 0x3F;
+ clk_sel = (cscmr1 >> 12) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 0x2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = CKIH /((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ case SPI1_CLK:
+ case SPI2_CLK:
+ pre_pdf = (cscdr2 >> 25) & 0x7;
+ pdf = (cscdr2 >> 19) & 0x3F;
+ clk_sel = (cscmr1 >> 4) & 3;
+ if (clk_sel == 0) {
+ ret_val = pll_clock(PLL1) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 1) {
+ ret_val = pll_clock(PLL2) / ((pre_pdf + 1) * (pdf + 1));
+ } else if (clk_sel == 2) {
+ ret_val = pll_clock(PLL3) / ((pre_pdf + 1) * (pdf + 1));
+ } else {
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ }
+ break;
+ default:
+ diag_printf("%s(): This clock: %d not supported yet\n",
+ __FUNCTION__, clk);
+ }
+
+ return ret_val;
}
#ifdef L2CC_ENABLED
* by using this command.
*/
RedBoot_cmd("L2",
- "L2 cache",
- "[ON | OFF]",
- do_L2_caches
- );
+ "L2 cache",
+ "[ON | OFF]",
+ do_L2_caches
+ );
void do_L2_caches(int argc, char *argv[])
{
- u32 oldints;
- int L2cache_on=0;
-
- if (argc == 2) {
- if (strcasecmp(argv[1], "on") == 0) {
- HAL_DISABLE_INTERRUPTS(oldints);
- HAL_ENABLE_L2();
- HAL_RESTORE_INTERRUPTS(oldints);
- } else if (strcasecmp(argv[1], "off") == 0) {
- HAL_DISABLE_INTERRUPTS(oldints);
- HAL_DCACHE_DISABLE_C1();
- HAL_CACHE_FLUSH_ALL();
- HAL_DISABLE_L2();
- HAL_DCACHE_ENABLE_L1();
- HAL_RESTORE_INTERRUPTS(oldints);
- } else {
- diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
- }
- } else {
- HAL_L2CACHE_IS_ENABLED(L2cache_on);
- diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
- }
+ u32 oldints;
+ int L2cache_on=0;
+
+ if (argc == 2) {
+ if (strcasecmp(argv[1], "on") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_ENABLE_L2();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else if (strcasecmp(argv[1], "off") == 0) {
+ HAL_DISABLE_INTERRUPTS(oldints);
+ HAL_DCACHE_DISABLE_L1();
+ HAL_CACHE_FLUSH_ALL();
+ HAL_DISABLE_L2();
+ HAL_DCACHE_ENABLE_L1();
+ HAL_RESTORE_INTERRUPTS(oldints);
+ } else {
+ diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
+ }
+ } else {
+ HAL_L2CACHE_IS_ENABLED(L2cache_on);
+ diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ }
}
#endif //L2CC_ENABLED
-#define IIM_ERR_SHIFT 8
-#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
-#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+#define IIM_ERR_SHIFT 8
+#define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
static void fuse_op_start(void)
{
- /* Do not generate interrupt */
- writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
- // clear the status bits and error bits
- writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
- writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+ /* Do not generate interrupt */
+ writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+ // clear the status bits and error bits
+ writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+ writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
}
/*
*/
static int poll_fuse_op_done(int action)
{
-
- u32 status, error;
-
- if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
- diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
- return -1;
- }
-
- /* Poll busy bit till it is NOT set */
- while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
- }
-
- /* Test for successful write */
- status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
- error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
-
- if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
- if (error) {
- diag_printf("Even though the operation seems successful...\n");
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- }
- return 0;
- }
- diag_printf("%s(%d) failed\n", __FUNCTION__, action);
- diag_printf("status address=0x%x, value=0x%x\n",
- (IIM_BASE_ADDR + IIM_STAT_OFF), status);
- diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
- (IIM_BASE_ADDR + IIM_ERR_OFF), error);
- return -1;
+ u32 status, error;
+
+ if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+ diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+ return -1;
+ }
+
+ /* Poll busy bit till it is NOT set */
+ while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+ }
+
+ /* Test for successful write */
+ status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+ error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+ if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+ if (error) {
+ diag_printf("Even though the operation seems successful...\n");
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ }
+ return 0;
+ }
+ diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+ diag_printf("status address=0x%08lx, value=0x%08x\n",
+ (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+ diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+ (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+ return -1;
}
-static void sense_fuse(int bank, int row, int bit)
+static unsigned int sense_fuse(int bank, int row, int bit)
{
- int addr, addr_l, addr_h, reg_addr;
+ int addr, addr_l, addr_h, reg_addr;
- fuse_op_start();
+ fuse_op_start();
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
- __FUNCTION__, addr_h, addr_l);
+ diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ __FUNCTION__, addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start sensing */
- writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
- diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
- __FUNCTION__, bank, row, bit);
- }
- reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
- diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start sensing */
+ writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+ diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+ __FUNCTION__, bank, row, bit);
+ }
+ reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+ diag_printf("fuses at (bank:%d, row:%d) = 0x%08x\n", bank, row, readl(reg_addr));
+ return readl(reg_addr);
}
void do_fuse_read(int argc, char *argv[])
{
- unsigned long bank, row;
-
- if (argc == 1) {
- diag_printf("Useage: fuse_read <bank> <row>\n");
- return;
- } else if (argc == 3) {
- if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
- sense_fuse(bank, row, 0);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: fuse_read <bank> <row>\n");
- }
+ unsigned long bank, row;
+ unsigned long fuse_val;
+
+ if (argc == 1) {
+ diag_printf("Usage: fuse_read <bank> <row>\n");
+ return;
+ } else if (argc == 3) {
+ if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+ fuse_val = sense_fuse(bank, row, 0);
+ diag_printf("fuses at (bank:%ld, row:%ld) = 0x%lx\n", bank, row, fuse_val);
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Usage: fuse_read <bank> <row>\n");
+ }
}
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
-static int fuse_blow(int bank,int row,int bit)
+int fuse_blow(int bank,int row,int bit)
{
- int addr, addr_l, addr_h, ret = -1;
+ int addr, addr_l, addr_h, ret = -1;
- fuse_op_start();
+ fuse_op_start();
- /* Disable IIM Program Protect */
- writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ /* Disable IIM Program Protect */
+ writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- addr = ((bank << 11) | (row << 3) | (bit & 0x7));
- /* Set IIM Program Upper Address */
- addr_h = (addr >> 8) & 0x000000FF;
- /* Set IIM Program Lower Address */
- addr_l = (addr & 0x000000FF);
+ addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+ /* Set IIM Program Upper Address */
+ addr_h = (addr >> 8) & 0x000000FF;
+ /* Set IIM Program Lower Address */
+ addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+ diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
#endif
- writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
- writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
- /* Start Programming */
- writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
- if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
- ret = 0;
- }
-
- /* Enable IIM Program Protect */
- writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
- return ret;
+ writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+ writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+ /* Start Programming */
+ writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+ ret = 0;
+ }
+
+ /* Enable IIM Program Protect */
+ writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+ return ret;
}
/*
* This command is added for burning IIM fuses
*/
RedBoot_cmd("fuse_read",
- "read some fuses",
- "<bank> <row>",
- do_fuse_read
- );
+ "read some fuses",
+ "<bank> <row>",
+ do_fuse_read
+ );
RedBoot_cmd("fuse_blow",
- "blow some fuses",
- "<bank> <row> <value>",
- do_fuse_blow
- );
-
-#define INIT_STRING "12345678"
+ "blow some fuses",
+ "<bank> <row> <value>",
+ do_fuse_blow
+ );
void quick_itoa(u32 num, char *a)
{
- int i, j, k;
- for (i = 0; i <= 7; i++) {
- j = (num >> (4 * i)) & 0xF;
- k = (j < 10) ? '0' : ('a' - 0xa);
- a[i] = j + k;
- }
+ int i, j, k;
+ for (i = 0; i <= 7; i++) {
+ j = (num >> (4 * i)) & 0xF;
+ k = (j < 10) ? '0' : ('a' - 0xa);
+ a[i] = j + k;
+ }
+}
+
+// slen - streng length, e.g.: 23 -> slen=2; abcd -> slen=4
+// only convert hex value as string input. so "12" is 0x12.
+u32 quick_atoi(char *a, u32 slen)
+{
+ u32 i, num = 0, digit;
+
+ for (i = 0; i < slen; i++) {
+ if (a[i] >= '0' && a[i] <= '9') {
+ digit = a[i] - '0';
+ } else if (a[i] >= 'a' && a[i] <= 'f') {
+ digit = a[i] - 'a' + 10;
+ } else if (a[i] >= 'A' && a[i] <= 'F') {
+ digit = a[i] - 'A' + 10;
+ } else {
+ diag_printf("ERROR: %c\n", a[i]);
+ return -1;
+ }
+ num = (num * 16) + digit;
+ }
+ return num;
+}
+
+static void fuse_blow_row(int bank, int row, int value)
+{
+ unsigned int reg, i;
+
+ // enable fuse blown
+ reg = readl(CCM_BASE_ADDR + 0x64);
+ reg |= 0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
+
+ for (i = 0; i < 8; i++) {
+ if (((value >> i) & 0x1) == 0) {
+ continue;
+ }
+ if (fuse_blow(bank, row, i) != 0) {
+ diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
+ bank, row, i);
+ }
+ }
+ reg &= ~0x10;
+ writel(reg, CCM_BASE_ADDR + 0x64);
}
void do_fuse_blow(int argc, char *argv[])
{
- unsigned long bank, row, value;
- unsigned int reg, i;
-
- if (argc != 4) {
- diag_printf("It is too dangeous for you to use this command.\n");
- return;
- }
- if (!parse_num(*(&argv[1]), &bank, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- if (!parse_num(*(&argv[3]), &value, &argv[3], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
-
- reg = readl(CCM_BASE_ADDR + 0x64);
- reg |= 0x10;
- writel(reg, CCM_BASE_ADDR + 0x64);
-
- diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
- bank, row, value);
- for (i = 0; i < 8; i++) {
- if (((value >> i) & 0x1) == 0) {
- continue;
- }
- if (fuse_blow(bank, row, i) != 0) {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
- bank, row, i);
- } else {
- diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
- bank, row, i);
- }
- }
- sense_fuse(bank, row, 0);
- reg &= ~0x10;
- writel(reg, CCM_BASE_ADDR + 0x64);
+ unsigned long bank, row, value, i;
+ unsigned int fuse_val;
+ char *s;
+ char val[3];
+
+ if (argc == 1) {
+ diag_printf("It is too dangeous for you to use this command.\n");
+ return;
+ }
+
+ if (argc == 3) {
+ if (strcasecmp(argv[1], "scc") == 0) {
+ // fuse_blow scc C3D153EDFD2EA9982226EF5047D3B9A0B9C7138EA87C028401D28C2C2C0B9AA2
+ diag_printf("Ready to burn SCC fuses\n");
+ s=argv[2];
+ for (i = 0; ;i++) {
+ memcpy(val, s, 2);
+ val[2]='\0';
+ value = quick_atoi(val, 2);
+ // diag_printf("fuse_blow_row(2, %d, value=0x%x)\n", i, value);
+ fuse_blow_row(2, i, value);
+
+ if ((++s)[0] == '\0') {
+ diag_printf("ERROR: Odd string input\n");
+ break;
+ }
+ if ((++s)[0] == '\0') {
+ diag_printf("Successful\n");
+ break;
+ }
+ }
+ } else if (strcasecmp(argv[1], "srk") == 0) {
+ // fuse_blow srk 418bccd09b53bee1ab59e2662b3c7877bc0094caee201052add49be8780dff95
+ diag_printf("Ready to burn SRK key fuses\n");
+ s=argv[2];
+ for (i = 0; ;i++) {
+ memcpy(val, s, 2);
+ val[2]='\0';
+ value = quick_atoi(val, 2);
+ if (i == 0) {
+ fuse_blow_row(1, 1, value); // 0x41 goes to SRK_HASH[255:248], bank 1, row 1
+ } else
+ fuse_blow_row(3, i, value); // 0x8b in SRK_HASH[247:240] bank 3, row 1
+ // 0xcc in SRK_HASH[239:232] bank 3, row 2
+ // ...
+ if ((++s)[0] == '\0') {
+ diag_printf("ERROR: Odd string input\n");
+ break;
+ }
+ if ((++s)[0] == '\0') {
+ diag_printf("Successful\n");
+ break;
+ }
+ }
+ } else
+ diag_printf("This command is not supported\n");
+
+ return;
+ } else if (argc == 4) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ if (!parse_num(*(&argv[3]), &value, &argv[3], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+
+ diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
+ bank, row, value);
+ fuse_blow_row(bank, row, value);
+ fuse_val = sense_fuse(bank, row, 0);
+ diag_printf("fuses at (bank:%ld, row:%ld) = 0x%x\n", bank, row, fuse_val);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ }
}
/* precondition: m>0 and n>0. Let g=gcd(m,n). */
int gcd(int m, int n)
{
- int t;
- while(m > 0) {
- if(n > m) {t = m; m = n; n = t;} /* swap */
- m -= n;
- }
- return n;
+ int t;
+ while(m > 0) {
+ if(n > m) {t = m; m = n; n = t;} /* swap */
+ m -= n;
+ }
+ return n;
}
-#define CLOCK_SRC_DETECT_MS 100
-#define CLOCK_IPG_DEFAULT 66500000
-#define CLOCK_SRC_DETECT_MARGIN 500000
-void mxc_show_clk_input(void)
+int read_mac_addr_from_fuse(unsigned char* data)
{
-// u32 c1, c2, diff, ipg_real, num = 0;
-
- return; // FIXME
-#if 0
- switch (prcs) {
- case 0x01:
- diag_printf("FPM enabled --> 32KHz input source\n");
- return;
- case 0x02:
- break;
- default:
- diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
- return;
- }
-
- // enable GPT with IPG clock input
- writel(0x241, GPT_BASE_ADDR + GPTCR);
- // prescaler = 1
- writel(0, GPT_BASE_ADDR + GPTPR);
-
- c1 = readl(GPT_BASE_ADDR + GPTCNT);
- // use 32KHz input clock to get the delay
- hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
- c2 = readl(GPT_BASE_ADDR + GPTCNT);
- diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
-
- ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
-
- if (num != 0) {
- diag_printf("Error: Actural clock input is %d MHz\n", num);
- diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- hal_delay_us(2000000);
- } else {
- diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
- ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
- }
-#endif
+ data[0] = sense_fuse(1, 9, 0) ;
+ data[1] = sense_fuse(1, 10, 0) ;
+ data[2] = sense_fuse(1, 11, 0) ;
+ data[3] = sense_fuse(1, 12, 0) ;
+ data[4] = sense_fuse(1, 13, 0) ;
+ data[5] = sense_fuse(1, 14, 0) ;
+
+ if ((data[0] == 0) && (data[1] == 0) && (data[2] == 0) &&
+ (data[3] == 0) && (data[4] == 0) && (data[5] == 0)) {
+ return 0;
+ }
+
+ return 1;
}
-RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
#if 0
void imx_power_mode(int mode)
{
- volatile unsigned int val;
- switch (mode) {
- case 2:
- writel(0x0000030f, GPC_PGR);
- writel(0x1, SRPGCR_EMI);
- writel(0x1, SRPGCR_ARM);
- writel(0x1, PGC_PGCR_VPU);
- writel(0x1, PGC_PGCR_IPU);
-
-
- case 1:
- // stop mode - from validation code
- // Set DSM_INT_HOLDOFF bit in TZIC
- // If the TZIC didn't write the bit then there was interrupt pending
- // It will be serviced while we're in the loop
- // So we write to this bit again
- while (readl(INTC_BASE_ADDR + 0x14) == 0) {
- writel(1, INTC_BASE_ADDR + 0x14);
- // Wait few cycles
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- __asm("nop");
- }
- diag_printf("Entering stop mode\n");
- val = readl(CCM_BASE_ADDR + 0x74);
- val = (val & 0xfffffffc) | 0x2; // set STOP mode
- writel(val, CCM_BASE_ADDR + 0x74);
- val = readl(PLATFORM_LPC_REG);
- writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
- writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
- break;
- default:
- break;
- }
-
- hal_delay_us(50);
-
- asm("mov r1, #0");
- asm("mcr p15, 0, r1, c7, c0, 4");
+ volatile unsigned int val;
+ switch (mode) {
+ case 2:
+ writel(0x0000030f, GPC_PGR);
+ writel(0x1, SRPGCR_EMI);
+ writel(0x1, SRPGCR_ARM);
+ writel(0x1, PGC_PGCR_VPU);
+ writel(0x1, PGC_PGCR_IPU);
+
+
+ case 1:
+ // stop mode - from validation code
+ // Set DSM_INT_HOLDOFF bit in TZIC
+ // If the TZIC didn't write the bit then there was interrupt pending
+ // It will be serviced while we're in the loop
+ // So we write to this bit again
+ while (readl(INTC_BASE_ADDR + 0x14) == 0) {
+ writel(1, INTC_BASE_ADDR + 0x14);
+ // Wait few cycles
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ __asm("nop");
+ }
+ diag_printf("Entering stop mode\n");
+ val = readl(CCM_BASE_ADDR + 0x74);
+ val = (val & 0xfffffffc) | 0x2; // set STOP mode
+ writel(val, CCM_BASE_ADDR + 0x74);
+ val = readl(PLATFORM_LPC_REG);
+ writel(val | (1 << 16), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ writel(val | (1 << 17), PLATFORM_LPC_REG);// ENABLE DSM in ELBOW submodule of ARM platform
+ break;
+ }
+
+ hal_delay_us(50);
+
+ asm("mov r1, #0");
+ asm("mcr p15, 0, r1, c7, c0, 4");
}
void do_power_mode(int argc, char *argv[])
{
- int mode;
-
- if (argc == 1) {
- diag_printf("Useage: power_mode <mode>\n");
- return;
- } else if (argc == 2) {
- if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) {
- diag_printf("Error: Invalid parameter\n");
- return;
- }
- diag_printf("Entering power mode: %d\n", mode);
- imx_power_mode(mode);
-
- } else {
- diag_printf("Passing in wrong arguments: %d\n", argc);
- diag_printf("Useage: power_mode <mode>\n");
- }
+ int mode;
+
+ if (argc == 1) {
+ diag_printf("Usage: power_mode <mode>\n");
+ return;
+ } else if (argc == 2) {
+ if (!parse_num(*(&argv[1]), (unsigned long *)&mode, &argv[1], " ")) {
+ diag_printf("Error: Invalid parameter\n");
+ return;
+ }
+ diag_printf("Entering power mode: %d\n", mode);
+ imx_power_mode(mode);
+
+ } else {
+ diag_printf("Passing in wrong arguments: %d\n", argc);
+ diag_printf("Usage: power_mode <mode>\n");
+ }
}
/*
* This command is added for burning IIM fuses
*/
RedBoot_cmd("power_mode",
- "Enter various power modes:",
- "\n\
- <0> - WAIT\n\
- <1> - SRPG\n\
- <2> - STOP\n\
- <3> - STOP with Power-Gating\n\
- -- need reset after issuing the command",
- do_power_mode
- );
+ "Enter various power modes:",
+ "\n"
+ " <0> - WAIT\n"
+ " <1> - SRPG\n"
+ " <2> - STOP\n"
+ " <3> - STOP with Power-Gating\n"
+ " -- need reset after issuing the command",
+ do_power_mode
+ );
#endif
+
+/* Super Root key moduli */
+static const UINT8 hab_super_root_moduli[] = {
+ /* modulus data */
+ 0xb9, 0x84, 0xc8, 0x8a, 0xd3, 0x7e, 0xcc, 0xc0, 0xe7, 0x3e, 0x11, 0x53,
+ 0x6b, 0x5e, 0xea, 0xf4, 0xd9, 0xac, 0x5a, 0x63, 0x8a, 0x79, 0x96, 0x83,
+ 0xb1, 0x39, 0xb2, 0x6f, 0x9c, 0x54, 0x87, 0xf4, 0x3b, 0x9e, 0xd8, 0x0f,
+ 0x89, 0xf5, 0x01, 0x53, 0xb8, 0xe2, 0xcc, 0x75, 0x0d, 0xe1, 0x13, 0xfa,
+ 0xa7, 0xb9, 0x1e, 0xff, 0x6a, 0x05, 0xdb, 0x58, 0x10, 0xbf, 0x2b, 0xf4,
+ 0xe7, 0x0a, 0x63, 0x82, 0x2c, 0xa3, 0xb5, 0x0a, 0x72, 0x1c, 0xdc, 0x29,
+ 0xc1, 0x81, 0xb5, 0x9a, 0xf0, 0x25, 0x7d, 0xd6, 0xee, 0x01, 0x64, 0xc7,
+ 0x07, 0x2d, 0xcb, 0x31, 0x4c, 0x8d, 0x82, 0xf6, 0x44, 0x95, 0x4a, 0xbc,
+ 0xae, 0xe8, 0x2a, 0x89, 0xd4, 0xf2, 0x66, 0x72, 0x2b, 0x09, 0x4e, 0x56,
+ 0xe9, 0xbf, 0x5e, 0x38, 0x5c, 0xd5, 0x7e, 0x15, 0x55, 0x86, 0x0f, 0x19,
+ 0xf6, 0x00, 0xee, 0xa1, 0x92, 0x78, 0xef, 0x93, 0xcb, 0xfa, 0xb4, 0x98,
+ 0x19, 0xef, 0x10, 0x70, 0xde, 0x36, 0x1c, 0x12, 0x2e, 0xd2, 0x09, 0xc7,
+ 0x7b, 0xd1, 0xaa, 0xd3, 0x46, 0x65, 0xa1, 0x5b, 0xee, 0xa5, 0x96, 0x97,
+ 0x98, 0x3e, 0xfc, 0xf8, 0x74, 0x22, 0x51, 0xe7, 0xf1, 0x2f, 0x30, 0x79,
+ 0x13, 0xe5, 0x42, 0xc6, 0x7c, 0x18, 0x76, 0xd3, 0x7f, 0x5a, 0x13, 0xde,
+ 0x2f, 0x51, 0x07, 0xfa, 0x93, 0xfe, 0x10, 0x8a, 0x0c, 0x18, 0x60, 0x3c,
+ 0xff, 0x6a, 0x9b, 0xe7, 0x10, 0x2d, 0x71, 0xd2, 0x34, 0xc0, 0xdf, 0xbe,
+ 0x17, 0x4e, 0x75, 0x40, 0x83, 0xaa, 0x90, 0xd1, 0xed, 0xbd, 0xbf, 0xac,
+ 0x9a, 0x30, 0xbd, 0x69, 0x4d, 0xd8, 0x00, 0x63, 0x92, 0x69, 0x98, 0xf8,
+ 0x89, 0xdc, 0x7b, 0xe3, 0x66, 0x7e, 0xdd, 0xfa, 0x8c, 0x74, 0xe2, 0xb1,
+ 0xeb, 0x94, 0xf7, 0xab, 0x0e, 0x92, 0x06, 0xab, 0x60, 0xe5, 0x00, 0x43,
+ 0xb2, 0x5e, 0x6e, 0xeb
+};
+
+/* Super Root key */
+const hab_rsa_public_key hab_super_root_key[] = {
+ {
+ {
+ /* RSA public exponent, right-padded */
+ 0x01, 0x00, 0x01, 0x00,
+ },
+ /* pointer to modulus data */
+ hab_super_root_moduli,
+ /* Exponent size in bytes */
+ 0x03,
+ /* Modulus size in bytes */
+ 0x100,
+ /* Key data valid */
+ TRUE
+ }
+};
--- /dev/null
+//==========================================================================
+//
+// hab_super_root.h
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#ifndef HAB_SUPER_ROOT_H
+#define HAB_SUPER_ROOT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==================================================================================================
+
+ Header Name: hab_super_root.h
+
+ General Description: This module contains the HAB Super Root public keys.
+
+====================================================================================================*/
+
+/* Generic type definitions */
+typedef signed char INT8;
+typedef unsigned char UINT8;
+typedef short int INT16;
+typedef unsigned short int UINT16;
+typedef int INT32;
+typedef unsigned int UINT32;
+typedef unsigned char BOOLEAN;
+
+
+/* HAB specific type definitions */
+typedef UINT8 *hab_bytestring;
+typedef UINT16 hab_algorithm;
+typedef UINT8 hab_index;
+typedef UINT32 hab_address;
+typedef UINT8 hab_certificate;
+typedef UINT32 hab_data_length;
+typedef UINT16 hab_int_length;
+typedef UINT8 hab_error;
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* HAB specific definitions */
+#define HAB_MAX_EXP_SIZE ((hab_int_length)4) /* Maximum size of RSA
+ * public key exponent
+ * - in bytes
+ */
+
+/*==================================================================================================
+ MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+ ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+ STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/* RSA public key structure */
+typedef struct
+{
+ UINT8 rsa_exponent[HAB_MAX_EXP_SIZE]; /* RSA public exponent */
+ const UINT8 *rsa_modulus; /* RSA modulus pointer */
+ hab_int_length exponent_size; /* Exponent size in bytes */
+ hab_int_length modulus_size; /* Modulus size in bytes */
+ BOOLEAN init_flag; /* Indicates if key initialised */
+} hab_rsa_public_key;
+
+/*==================================================================================================
+ GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+/* Super Root keys */
+extern const hab_rsa_public_key hab_super_root_key[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAB_SUPER_ROOT_H */
/*=============================================================================
//
-// hal_diag.c
+// hal_diag.c
//
-// HAL diagnostic output code
+// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
-#include <cyg/infra/cyg_type.h> // base types
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_arch.h> // basic machine info
-#include <cyg/hal/hal_intr.h> // interrupt macros
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_if.h> // Calling interface definitions
+#include <cyg/hal/hal_arch.h> // basic machine info
+#include <cyg/hal/hal_intr.h> // interrupt macros
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_if.h> // Calling interface definitions
#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
-#include <cyg/hal/hal_misc.h> // Helper functions
-#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/drv_api.h> // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h> // Helper functions
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <redboot.h>
/*
* UART Control Register 0 Bit Fields.
*/
-#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
-#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
-#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
-#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
-#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
-#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
-#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
-#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
-#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
-#define EUartUCR1_SNDBRK (1 << 4) // Send break
-#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
-#define EUartUCR1_DOZE (1 << 1) // Doze
-#define EUartUCR1_UARTEN (1 << 0) // UART enabled
-#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
-#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
-#define EUartUCR2_CTSC (1 << 13) // CTS pin control
-#define EUartUCR2_CTS (1 << 12) // Clear to send
-#define EUartUCR2_ESCEN (1 << 11) // Escape enable
-#define EUartUCR2_PREN (1 << 8) // Parity enable
-#define EUartUCR2_PROE (1 << 7) // Parity odd/even
-#define EUartUCR2_STPB (1 << 6) // Stop
-#define EUartUCR2_WS (1 << 5) // Word size
-#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
-#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
-#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
-#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
-#define EUartUCR2_SRST_ (1 << 0) // SW reset
-#define EUartUCR3_PARERREN (1 << 12) // Parity enable
-#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
-#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
-#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
-#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
-#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
-#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
-#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
-#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
-#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
-#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
-#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
-#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
-#define EUartUCR4_IRSC (1 << 5) // IR special case
-#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
-#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
-#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
-#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
-#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
-#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
-#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
-#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
-#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
-#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
-#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
-#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
-#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
-#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
-#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
-#define EUartUSR1_RTSS (1 << 14) // RTS pin status
-#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
-#define EUartUSR1_RTSD (1 << 12) // RTS delta
-#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
-#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
-#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
-#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
-#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
-#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
-#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
-#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
-#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
-#define EUartUSR2_IDLE (1 << 12) // Idle condition
-#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
-#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
-#define EUartUSR2_WAKE (1 << 7) // Wake
-#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
-#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
-#define EUartUSR2_BRCD (1 << 2) // Break condition
-#define EUartUSR2_ORE (1 << 1) // Overrun error
-#define EUartUSR2_RDR (1 << 0) // Recv data ready
-#define EUartUTS_FRCPERR (1 << 13) // Force parity error
-#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
-#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
-#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
-#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
-#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
-#define EUartUTS_SOFTRST (1 << 0) // Software reset
-
-#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2
-//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4
-//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_7
+#define EUartUCR1_ADEN (1 << 15) // Auto dectect interrupt
+#define EUartUCR1_ADBR (1 << 14) // Auto detect baud rate
+#define EUartUCR1_TRDYEN (1 << 13) // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN (1 << 12) // Idle condition interrupt
+#define EUartUCR1_RRDYEN (1 << 9) // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN (1 << 8) // Recv ready DMA enable
+#define EUartUCR1_IREN (1 << 7) // Infrared interface enable
+#define EUartUCR1_TXMPTYEN (1 << 6) // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN (1 << 5) // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK (1 << 4) // Send break
+#define EUartUCR1_TDMAEN (1 << 3) // Transmitter ready DMA enable
+#define EUartUCR1_DOZE (1 << 1) // Doze
+#define EUartUCR1_UARTEN (1 << 0) // UART enabled
+#define EUartUCR2_ESCI (1 << 15) // Escape seq interrupt enable
+#define EUartUCR2_IRTS (1 << 14) // Ignore RTS pin
+#define EUartUCR2_CTSC (1 << 13) // CTS pin control
+#define EUartUCR2_CTS (1 << 12) // Clear to send
+#define EUartUCR2_ESCEN (1 << 11) // Escape enable
+#define EUartUCR2_PREN (1 << 8) // Parity enable
+#define EUartUCR2_PROE (1 << 7) // Parity odd/even
+#define EUartUCR2_STPB (1 << 6) // Stop
+#define EUartUCR2_WS (1 << 5) // Word size
+#define EUartUCR2_RTSEN (1 << 4) // Request to send interrupt enable
+#define EUartUCR2_ATEN (1 << 3) // Aging timer enable
+#define EUartUCR2_TXEN (1 << 2) // Transmitter enabled
+#define EUartUCR2_RXEN (1 << 1) // Receiver enabled
+#define EUartUCR2_SRST_ (1 << 0) // SW reset
+#define EUartUCR3_PARERREN (1 << 12) // Parity enable
+#define EUartUCR3_FRAERREN (1 << 11) // Frame error interrupt enable
+#define EUartUCR3_ADNIMP (1 << 7) // Autobaud detection not improved
+#define EUartUCR3_RXDSEN (1 << 6) // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN (1 << 5) // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN (1 << 4) // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2) // RXD muxed input selected
+#define EUartUCR3_INVT (1 << 1) // Inverted Infrared transmission
+#define EUartUCR3_ACIEN (1 << 0) // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32 (32 << 10) // CTS trigger level (32 chars)
+#define EUartUCR4_INVR (1 << 9) // Inverted infrared reception
+#define EUartUCR4_ENIRI (1 << 8) // Serial infrared interrupt enable
+#define EUartUCR4_WKEN (1 << 7) // Wake interrupt enable
+#define EUartUCR4_IRSC (1 << 5) // IR special case
+#define EUartUCR4_LPBYP (1 << 4) // Low power bypass
+#define EUartUCR4_TCEN (1 << 3) // Transmit complete interrupt enable
+#define EUartUCR4_BKEN (1 << 2) // Break condition interrupt enable
+#define EUartUCR4_OREN (1 << 1) // Receiver overrun interrupt enable
+#define EUartUCR4_DREN (1 << 0) // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF 0 // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1 (5 << 7) // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2 (4 << 7) // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3 (3 << 7) // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4 (2 << 7) // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5 (1 << 7) // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6 (0 << 7) // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7 (6 << 7) // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF 10 // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15) // Parity error interrupt flag
+#define EUartUSR1_RTSS (1 << 14) // RTS pin status
+#define EUartUSR1_TRDY (1 << 13) // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD (1 << 12) // RTS delta
+#define EUartUSR1_ESCF (1 << 11) // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR (1 << 10) // Frame error interrupt flag
+#define EUartUSR1_RRDY (1 << 9) // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM (1 << 8) // Aging timeout interrupt status
+#define EUartUSR1_RXDS (1 << 6) // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT (1 << 5) // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE (1 << 4) // Aysnc wake interrupt flag
+#define EUartUSR2_ADET (1 << 15) // Auto baud rate detect complete
+#define EUartUSR2_TXFE (1 << 14) // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE (1 << 12) // Idle condition
+#define EUartUSR2_ACST (1 << 11) // Autobaud counter stopped
+#define EUartUSR2_IRINT (1 << 8) // Serial infrared interrupt flag
+#define EUartUSR2_WAKE (1 << 7) // Wake
+#define EUartUSR2_RTSF (1 << 4) // RTS edge interrupt flag
+#define EUartUSR2_TXDC (1 << 3) // Transmitter complete
+#define EUartUSR2_BRCD (1 << 2) // Break condition
+#define EUartUSR2_ORE (1 << 1) // Overrun error
+#define EUartUSR2_RDR (1 << 0) // Recv data ready
+#define EUartUTS_FRCPERR (1 << 13) // Force parity error
+#define EUartUTS_LOOP (1 << 12) // Loop tx and rx
+#define EUartUTS_TXEMPTY (1 << 6) // TxFIFO empty
+#define EUartUTS_RXEMPTY (1 << 5) // RxFIFO empty
+#define EUartUTS_TXFULL (1 << 4) // TxFIFO full
+#define EUartUTS_RXFULL (1 << 3) // RxFIFO full
+#define EUartUTS_SOFTRST (1 << 0) // Software reset
+
+#define EUartUFCR_RFDIV EUartUFCR_RFDIV_2
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_4
+//#define EUartUFCR_RFDIV EUartUFCR_RFDIV_7
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
-#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 2)
#endif
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
-#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 4)
#endif
#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_7)
-#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 7)
+#define MXC_UART_REFFREQ (get_peri_clock(UART1_BAUD) / 7)
#endif
-#if 0
+/* The Freescale boards have two external UART ports which are mapped first
+ * for whatever strange reason.
+ * Other manufacturers may not have these UARTS on their boards but would
+ * as well like to have their serial ports start at '0'!
+ */
+#ifdef CYGPKG_HAL_ARM_TX51KARO
+#define MXC_UART_CHAN_OFFSET 0
+#else
+#define MXC_UART_CHAN_OFFSET 2
+#endif
+
+#if 1
void
cyg_hal_plf_comms_init(void)
{
- static int initialized = 0;
+ static int initialized = 0;
- if (initialized)
- return;
+ if (initialized)
+ return;
- initialized = 1;
+ initialized = 1;
- cyg_hal_plf_serial_init();
+ cyg_hal_plf_serial_init();
}
#endif
//=============================================================================
#ifdef UART_WIDTH_32
struct mxc_serial {
- volatile cyg_uint32 urxd[16];
- volatile cyg_uint32 utxd[16];
- volatile cyg_uint32 ucr1;
- volatile cyg_uint32 ucr2;
- volatile cyg_uint32 ucr3;
- volatile cyg_uint32 ucr4;
- volatile cyg_uint32 ufcr;
- volatile cyg_uint32 usr1;
- volatile cyg_uint32 usr2;
- volatile cyg_uint32 uesc;
- volatile cyg_uint32 utim;
- volatile cyg_uint32 ubir;
- volatile cyg_uint32 ubmr;
- volatile cyg_uint32 ubrc;
- volatile cyg_uint32 onems;
- volatile cyg_uint32 uts;
+ volatile cyg_uint32 urxd[16];
+ volatile cyg_uint32 utxd[16];
+ volatile cyg_uint32 ucr1;
+ volatile cyg_uint32 ucr2;
+ volatile cyg_uint32 ucr3;
+ volatile cyg_uint32 ucr4;
+ volatile cyg_uint32 ufcr;
+ volatile cyg_uint32 usr1;
+ volatile cyg_uint32 usr2;
+ volatile cyg_uint32 uesc;
+ volatile cyg_uint32 utim;
+ volatile cyg_uint32 ubir;
+ volatile cyg_uint32 ubmr;
+ volatile cyg_uint32 ubrc;
+ volatile cyg_uint32 onems;
+ volatile cyg_uint32 uts;
};
#else
struct mxc_serial {
- volatile cyg_uint16 urxd[1];
- volatile cyg_uint16 resv0[31];
-
- volatile cyg_uint16 utxd[1];
- volatile cyg_uint16 resv1[31];
- volatile cyg_uint16 ucr1;
- volatile cyg_uint16 resv2;
- volatile cyg_uint16 ucr2;
- volatile cyg_uint16 resv3;
- volatile cyg_uint16 ucr3;
- volatile cyg_uint16 resv4;
- volatile cyg_uint16 ucr4;
- volatile cyg_uint16 resv5;
- volatile cyg_uint16 ufcr;
- volatile cyg_uint16 resv6;
- volatile cyg_uint16 usr1;
- volatile cyg_uint16 resv7;
- volatile cyg_uint16 usr2;
- volatile cyg_uint16 resv8;
- volatile cyg_uint16 uesc;
- volatile cyg_uint16 resv9;
- volatile cyg_uint16 utim;
- volatile cyg_uint16 resv10;
- volatile cyg_uint16 ubir;
- volatile cyg_uint16 resv11;
- volatile cyg_uint16 ubmr;
- volatile cyg_uint16 resv12;
- volatile cyg_uint16 ubrc;
- volatile cyg_uint16 resv13;
- volatile cyg_uint16 onems;
- volatile cyg_uint16 resv14;
- volatile cyg_uint16 uts;
- volatile cyg_uint16 resv15;
+ volatile cyg_uint16 urxd[1];
+ volatile cyg_uint16 resv0[31];
+
+ volatile cyg_uint16 utxd[1];
+ volatile cyg_uint16 resv1[31];
+ volatile cyg_uint16 ucr1;
+ volatile cyg_uint16 resv2;
+ volatile cyg_uint16 ucr2;
+ volatile cyg_uint16 resv3;
+ volatile cyg_uint16 ucr3;
+ volatile cyg_uint16 resv4;
+ volatile cyg_uint16 ucr4;
+ volatile cyg_uint16 resv5;
+ volatile cyg_uint16 ufcr;
+ volatile cyg_uint16 resv6;
+ volatile cyg_uint16 usr1;
+ volatile cyg_uint16 resv7;
+ volatile cyg_uint16 usr2;
+ volatile cyg_uint16 resv8;
+ volatile cyg_uint16 uesc;
+ volatile cyg_uint16 resv9;
+ volatile cyg_uint16 utim;
+ volatile cyg_uint16 resv10;
+ volatile cyg_uint16 ubir;
+ volatile cyg_uint16 resv11;
+ volatile cyg_uint16 ubmr;
+ volatile cyg_uint16 resv12;
+ volatile cyg_uint16 ubrc;
+ volatile cyg_uint16 resv13;
+ volatile cyg_uint16 onems;
+ volatile cyg_uint16 resv14;
+ volatile cyg_uint16 uts;
+ volatile cyg_uint16 resv15;
};
#endif
typedef struct {
- volatile struct mxc_serial* base;
- cyg_int32 msec_timeout;
- int isr_vector;
- int baud_rate;
+ volatile struct mxc_serial *base;
+ cyg_int32 msec_timeout;
+ int isr_vector;
+ int baud_rate;
} channel_data_t;
static channel_data_t channels[] = {
#if CYGHWR_HAL_ARM_SOC_UART1 != 0
- {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
#if CYGHWR_HAL_ARM_SOC_UART2 != 0
- {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
#if CYGHWR_HAL_ARM_SOC_UART3 != 0
- {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
- CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+ {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+ CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
#endif
};
/*---------------------------------------------------------------------------*/
-static void init_serial_channel(channel_data_t* __ch_data)
+static void init_serial_channel(channel_data_t *__ch_data)
{
- volatile struct mxc_serial* base = __ch_data->base;
-
- /* Wait for UART to finish transmitting */
- while (!(base->uts & EUartUTS_TXEMPTY));
-
- /* Disable UART */
- base->ucr1 &= ~EUartUCR1_UARTEN;
-
- /* Set to default POR state */
- base->ucr1 = 0x00000000;
- base->ucr2 = 0x00000000;
-
- while (!(base->ucr2 & EUartUCR2_SRST_));
-
- base->ucr3 = 0x00000704;
- base->ucr4 = 0x00008000;
- base->ufcr = 0x00000801;
- base->uesc = 0x0000002B;
- base->utim = 0x00000000;
- base->ubir = 0x00000000;
- base->ubmr = 0x00000000;
- base->onems = 0x00000000;
- base->uts = 0x00000000;
-
- /* Configure FIFOs */
- base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
- | (2 << EUartUFCR_TXTL_SHF);
-
- /* Setup One MS timer */
- base->onems = (MXC_UART_REFFREQ / 1000);
-
- /* Set to 8N1 */
- base->ucr2 &= ~EUartUCR2_PREN;
- base->ucr2 |= EUartUCR2_WS;
- base->ucr2 &= ~EUartUCR2_STPB;
-
- /* Ignore RTS */
- base->ucr2 |= EUartUCR2_IRTS;
-
- /* Enable UART */
- base->ucr1 |= EUartUCR1_UARTEN;
-
- /* Enable FIFOs */
- base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
-
- /* Clear status flags */
- base->usr2 |= EUartUSR2_ADET |
- EUartUSR2_IDLE |
- EUartUSR2_IRINT |
- EUartUSR2_WAKE |
- EUartUSR2_RTSF |
- EUartUSR2_BRCD |
- EUartUSR2_ORE |
- EUartUSR2_RDR;
-
- /* Clear status flags */
- base->usr1 |= EUartUSR1_PARITYERR |
- EUartUSR1_RTSD |
- EUartUSR1_ESCF |
- EUartUSR1_FRAMERR |
- EUartUSR1_AIRINT |
- EUartUSR1_AWAKE;
-
- /* Set the numerator value minus one of the BRM ratio */
- base->ubir = (__ch_data->baud_rate / 100) - 1;
-
- /* Set the denominator value minus one of the BRM ratio */
- base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
-
+ volatile struct mxc_serial *base = __ch_data->base;
+
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
+
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
+
+ /* Set to default POR state */
+ base->ucr1 = 0x00000000;
+ base->ucr2 = 0x00000000;
+
+ while (!(base->ucr2 & EUartUCR2_SRST_));
+
+ base->ucr3 = 0x00000704;
+ base->ucr4 = 0x00008000;
+ base->ufcr = 0x00000801;
+ base->uesc = 0x0000002B;
+ base->utim = 0x00000000;
+ base->ubir = 0x00000000;
+ base->ubmr = 0x00000000;
+ base->onems = 0x00000000;
+ base->uts = 0x00000000;
+
+ /* Configure FIFOs */
+ base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV |
+ (2 << EUartUFCR_TXTL_SHF);
+
+ /* Setup One MS timer */
+ base->onems = MXC_UART_REFFREQ / 1000;
+
+ /* Set to 8N1 */
+ base->ucr2 &= ~EUartUCR2_PREN;
+ base->ucr2 |= EUartUCR2_WS;
+ base->ucr2 &= ~EUartUCR2_STPB;
+
+ /* Ignore RTS */
+ base->ucr2 |= EUartUCR2_IRTS;
+
+ /* Enable UART */
+ base->ucr1 |= EUartUCR1_UARTEN;
+
+ /* Enable FIFOs */
+ base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+ /* Clear status flags */
+ base->usr2 |= EUartUSR2_ADET |
+ EUartUSR2_IDLE |
+ EUartUSR2_IRINT |
+ EUartUSR2_WAKE |
+ EUartUSR2_RTSF |
+ EUartUSR2_BRCD |
+ EUartUSR2_ORE |
+ EUartUSR2_RDR;
+
+ /* Clear status flags */
+ base->usr1 |= EUartUSR1_PARITYERR |
+ EUartUSR1_RTSD |
+ EUartUSR1_ESCF |
+ EUartUSR1_FRAMERR |
+ EUartUSR1_AIRINT |
+ EUartUSR1_AWAKE;
+
+ /* Set the numerator value minus one of the BRM ratio */
+ base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+ /* Set the denominator value minus one of the BRM ratio */
+ base->ubmr = (MXC_UART_REFFREQ / 1600) - 1;
}
-static void stop_serial_channel(channel_data_t* __ch_data)
+static void stop_serial_channel(channel_data_t *__ch_data)
{
- volatile struct mxc_serial* base = __ch_data->base;
+ volatile struct mxc_serial *base = __ch_data->base;
- /* Wait for UART to finish transmitting */
- while (!(base->uts & EUartUTS_TXEMPTY));
+ /* Wait for UART to finish transmitting */
+ while (!(base->uts & EUartUTS_TXEMPTY));
- /* Disable UART */
- base->ucr1 &= ~EUartUCR1_UARTEN;
+ /* Disable UART */
+ base->ucr1 &= ~EUartUCR1_UARTEN;
}
//#define debug_uart_log_buf
void cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
- volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
-
+ channel_data_t *chan = __ch_data;
+ volatile struct mxc_serial *base = chan->base;
#ifdef debug_uart_log_buf
- __log_buf[diag_bp++] = c;
- return;
+ __log_buf[diag_bp++] = c;
+ return;
#endif
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- // Wait for Tx FIFO not full
- while (base->uts & EUartUTS_TXFULL)
- ;
- base->utxd[0] = c;
+ // Wait for Tx FIFO not full
+ while (base->uts & EUartUTS_TXFULL)
+ ;
+ base->utxd[0] = c;
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
- cyg_uint8* ch)
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void *__ch_data,
+ cyg_uint8 *ch)
{
- volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+ channel_data_t *chan = __ch_data;
+ volatile struct mxc_serial *base = chan->base;
- // If receive fifo is empty, return false
- if (base->uts & EUartUTS_RXEMPTY)
- return false;
+ // If receive fifo is empty, return false
+ if (base->uts & EUartUTS_RXEMPTY)
+ return false;
- *ch = (char)base->urxd[0];
+ *ch = (char)base->urxd[0];
- return true;
+ return true;
}
-cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+cyg_uint8 cyg_hal_plf_serial_getc(void *__ch_data)
{
- cyg_uint8 ch;
- CYGARC_HAL_SAVE_GP();
+ cyg_uint8 ch;
+ CYGARC_HAL_SAVE_GP();
- while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+ while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
- CYGARC_HAL_RESTORE_GP();
- return ch;
+ CYGARC_HAL_RESTORE_GP();
+ return ch;
}
-static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
- cyg_uint32 __len)
+static void cyg_hal_plf_serial_write(void *__ch_data, const cyg_uint8 *__buf,
+ cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while(__len-- > 0)
- cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+ while (__len-- > 0)
+ cyg_hal_plf_serial_putc(__ch_data, *__buf++);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
- cyg_uint32 __len)
+static void cyg_hal_plf_serial_read(void *__ch_data, cyg_uint8 *__buf,
+ cyg_uint32 __len)
{
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- while (__len-- > 0)
- *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+ while (__len-- > 0)
+ *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
- CYGARC_HAL_RESTORE_GP();
+ CYGARC_HAL_RESTORE_GP();
}
-cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
- cyg_uint8* ch)
+cyg_bool cyg_hal_plf_serial_getc_timeout(void *__ch_data,
+ cyg_uint8 *ch)
{
- int delay_count;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- cyg_bool res;
- CYGARC_HAL_SAVE_GP();
+ int delay_count;
+ channel_data_t *chan = __ch_data;
+ cyg_bool res;
+ CYGARC_HAL_SAVE_GP();
- delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+ delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
- for(;;) {
- res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
- if (res || 0 == delay_count--)
- break;
+ for (;;) {
+ res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+ if (res || 0 == delay_count--)
+ break;
- CYGACC_CALL_IF_DELAY_US(100);
- }
+ CYGACC_CALL_IF_DELAY_US(100);
+ }
- CYGARC_HAL_RESTORE_GP();
- return res;
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
static int cyg_hal_plf_serial_control(void *__ch_data,
- __comm_control_cmd_t __func, ...)
+ __comm_control_cmd_t __func, ...)
{
- static int irq_state = 0;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- int ret = -1;
- va_list ap;
-
- CYGARC_HAL_SAVE_GP();
- va_start(ap, __func);
-
- switch (__func) {
- case __COMMCTL_GETBAUD:
- ret = chan->baud_rate;
- break;
- case __COMMCTL_SETBAUD:
- chan->baud_rate = va_arg(ap, cyg_int32);
- // Should we verify this value here?
- init_serial_channel(chan);
- ret = 0;
- break;
- case __COMMCTL_IRQ_ENABLE:
- irq_state = 1;
-
- chan->base->ucr1 |= EUartUCR1_RRDYEN;
-
- HAL_INTERRUPT_UNMASK(chan->isr_vector);
- break;
- case __COMMCTL_IRQ_DISABLE:
- ret = irq_state;
- irq_state = 0;
-
- chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
-
- HAL_INTERRUPT_MASK(chan->isr_vector);
- break;
- case __COMMCTL_DBG_ISR_VECTOR:
- ret = chan->isr_vector;
- break;
- case __COMMCTL_SET_TIMEOUT:
- ret = chan->msec_timeout;
- chan->msec_timeout = va_arg(ap, cyg_uint32);
- break;
- default:
- break;
- }
- va_end(ap);
- CYGARC_HAL_RESTORE_GP();
- return ret;
+ static int irq_state = 0;
+ channel_data_t *chan = __ch_data;
+ int ret = -1;
+ va_list ap;
+
+ CYGARC_HAL_SAVE_GP();
+ va_start(ap, __func);
+
+ switch (__func) {
+ case __COMMCTL_GETBAUD:
+ ret = chan->baud_rate;
+ break;
+ case __COMMCTL_SETBAUD:
+ chan->baud_rate = va_arg(ap, cyg_int32);
+ // Should we verify this value here?
+ init_serial_channel(chan);
+ ret = 0;
+ break;
+ case __COMMCTL_IRQ_ENABLE:
+ irq_state = 1;
+
+ chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_UNMASK(chan->isr_vector);
+ break;
+ case __COMMCTL_IRQ_DISABLE:
+ ret = irq_state;
+ irq_state = 0;
+
+ chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+ HAL_INTERRUPT_MASK(chan->isr_vector);
+ break;
+ case __COMMCTL_DBG_ISR_VECTOR:
+ ret = chan->isr_vector;
+ break;
+ case __COMMCTL_SET_TIMEOUT:
+ ret = chan->msec_timeout;
+ chan->msec_timeout = va_arg(ap, cyg_uint32);
+ break;
+ default:
+ break;
+ }
+ va_end(ap);
+ CYGARC_HAL_RESTORE_GP();
+ return ret;
}
-static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
- CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+static int cyg_hal_plf_serial_isr(void *__ch_data, int *__ctrlc,
+ CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
- int res = 0;
- channel_data_t* chan = (channel_data_t*)__ch_data;
- char c;
+ int res = 0;
+ channel_data_t *chan = __ch_data;
+ char c;
- CYGARC_HAL_SAVE_GP();
+ CYGARC_HAL_SAVE_GP();
- cyg_drv_interrupt_acknowledge(chan->isr_vector);
+ cyg_drv_interrupt_acknowledge(chan->isr_vector);
- *__ctrlc = 0;
- if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
- c = (char)chan->base->urxd[0];
+ *__ctrlc = 0;
+ if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+ c = (char)chan->base->urxd[0];
- if (cyg_hal_is_break( &c , 1 ))
- *__ctrlc = 1;
+ if (cyg_hal_is_break(&c, 1))
+ *__ctrlc = 1;
- res = CYG_ISR_HANDLED;
- }
+ res = CYG_ISR_HANDLED;
+ }
- CYGARC_HAL_RESTORE_GP();
- return res;
+ CYGARC_HAL_RESTORE_GP();
+ return res;
}
void cyg_hal_plf_serial_init(void)
{
- hal_virtual_comm_table_t* comm;
- int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
- int i;
- static int jjj = 0;
-
- // Init channels
-#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
- for (i = 0; i < NUMOF(channels); i++) {
- init_serial_channel(&channels[i]);
- CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
- comm = CYGACC_CALL_IF_CONSOLE_PROCS();
- CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
- CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
- CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
- CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
- CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
- CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
- CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
- CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
- if (jjj == 0) {
- cyg_hal_plf_serial_putc(&channels[i], '+');
- jjj++;
- }
- cyg_hal_plf_serial_putc(&channels[i], '+');
- }
-
- // Restore original console
- CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+ hal_virtual_comm_table_t *comm;
+ int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+ int i;
+ static int jjj = 0;
+
+ // Init channels
+ for (i = 0; i < NUM_ELEMS(channels); i++) {
+ init_serial_channel(&channels[i]);
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(i + MXC_UART_CHAN_OFFSET);
+ comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+ CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+ CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+ CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+ CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+ CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+ CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+ CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+ CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+ if (jjj == 0) {
+ cyg_hal_plf_serial_putc(&channels[i], '+');
+ jjj++;
+ }
+ }
+
+ // Restore original console
+ CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
void cyg_hal_plf_serial_stop(void)
{
- int i;
+ int i;
- // Init channels
-#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
- for (i = 0; i < NUMOF(channels); i++) {
- stop_serial_channel(&channels[i]);
- }
+ // Init channels
+ for (i = 0; i < NUM_ELEMS(channels); i++) {
+ stop_serial_channel(&channels[i]);
+ }
}
//=============================================================================
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
-#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
+#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
-#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define MXC_UART1_CHAN (0 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART2_CHAN (1 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART3_CHAN (2 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART4_CHAN (3 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART5_CHAN (4 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART6_CHAN (5 + MXC_UART_CHAN_OFFSET)
+
+#undef __BASE
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART1_CHAN)
#define __BASE ((void*)UART1_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART2_CHAN)
#define __BASE ((void*)UART2_BASE_ADDR)
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART3_CHAN)
#define __BASE ((void*)UART3_BASE_ADDR)
#endif
#endif
static channel_data_t channel = {
- (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+ __BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
};
#ifdef HAL_DIAG_USES_HARDWARE
void hal_diag_init(void)
{
- static int init = 0;
- char *msg = "\n\rARM eCos\n\r";
- cyg_uint8 lcr;
+ static int init = 0;
+ char *msg = "\n\rARM eCos\n\r";
- if (init++) return;
+ if (init++) return;
- init_serial_channel(&channel);
+ init_serial_channel(&channel);
- while (*msg) hal_diag_write_char(*msg++);
+ while (*msg) hal_diag_write_char(*msg++);
}
#ifdef DEBUG_DIAG
{
#ifdef DEBUG_DIAG
#ifndef CYG_HAL_STARTUP_ROM
- diag_buffer[diag_bp++] = c;
- if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+ diag_buffer[diag_bp++] = c;
+ if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
#endif
#endif
- cyg_hal_plf_serial_putc(&channel, c);
+ cyg_hal_plf_serial_putc(&channel, c);
}
void hal_diag_read_char(char *c)
{
- *c = cyg_hal_plf_serial_getc(&channel);
+ *c = cyg_hal_plf_serial_getc(&channel);
}
#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
void hal_diag_read_char(char *c)
{
- *c = cyg_hal_plf_serial_getc(&channel);
+ *c = cyg_hal_plf_serial_getc(&channel);
}
void hal_diag_write_char(char c)
{
- static char line[100];
- static int pos = 0;
-
- // FIXME: Some LED blinking might be nice right here.
+ static char line[100];
+ static int pos = 0;
- // No need to send CRs
- if( c == '\r' ) return;
+ // FIXME: Some LED blinking might be nice right here.
- line[pos++] = c;
+ // No need to send CRs
+ if (c == '\r') return;
- if (c == '\n' || pos == sizeof(line)) {
- CYG_INTERRUPT_STATE old;
+ line[pos++] = c;
- // Disable interrupts. This prevents GDB trying to interrupt us
- // while we are in the middle of sending a packet. The serial
- // receive interrupt will be seen when we re-enable interrupts
- // later.
+ if (c == '\n' || pos == sizeof(line)) {
+ CYG_INTERRUPT_STATE old;
+ // Disable interrupts. This prevents GDB trying to interrupt us
+ // while we are in the middle of sending a packet. The serial
+ // receive interrupt will be seen when we re-enable interrupts
+ // later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
- HAL_DISABLE_INTERRUPTS(old);
+ HAL_DISABLE_INTERRUPTS(old);
#endif
-
- while (1) {
- static char hex[] = "0123456789ABCDEF";
- cyg_uint8 csum = 0;
- int i;
+ while (1) {
+ static char hex[] = "0123456789ABCDEF";
+ cyg_uint8 csum = 0;
+ int i;
#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- char c1;
+ char c1;
#endif
- cyg_hal_plf_serial_putc(&channel, '$');
- cyg_hal_plf_serial_putc(&channel, 'O');
- csum += 'O';
- for(i = 0; i < pos; i++) {
- char ch = line[i];
- char h = hex[(ch>>4)&0xF];
- char l = hex[ch&0xF];
- cyg_hal_plf_serial_putc(&channel, h);
- cyg_hal_plf_serial_putc(&channel, l);
- csum += h;
- csum += l;
- }
- cyg_hal_plf_serial_putc(&channel, '#');
- cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
- cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+ cyg_hal_plf_serial_putc(&channel, '$');
+ cyg_hal_plf_serial_putc(&channel, 'O');
+ csum += 'O';
+ for (i = 0; i < pos; i++) {
+ char ch = line[i];
+ char h = hex[(ch >> 4) & 0xF];
+ char l = hex[ch & 0xF];
+ cyg_hal_plf_serial_putc(&channel, h);
+ cyg_hal_plf_serial_putc(&channel, l);
+ csum += h;
+ csum += l;
+ }
+ cyg_hal_plf_serial_putc(&channel, '#');
+ cyg_hal_plf_serial_putc(&channel, hex[(csum >> 4) & 0xF]);
+ cyg_hal_plf_serial_putc(&channel, hex[csum & 0xF]);
#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- break; // regardless
+ break; // regardless
#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
- // Wait for the ACK character '+' from GDB here and handle
- // receiving a ^C instead. This is the reason for this clause
- // being a loop.
- c1 = cyg_hal_plf_serial_getc(&channel);
+ // Wait for the ACK character '+' from GDB here and handle
+ // receiving a ^C instead. This is the reason for this clause
+ // being a loop.
+ c1 = cyg_hal_plf_serial_getc(&channel);
- if( c1 == '+' )
- break; // a good acknowledge
+ if (c1 == '+')
+ break; // a good acknowledge
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
- cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
- if( c1 == 3 ) {
- // Ctrl-C: breakpoint.
- cyg_hal_gdb_interrupt(
- (target_register_t)__builtin_return_address(0) );
- break;
- }
+ cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+ if (c1 == '\003') {
+ // Ctrl-C: breakpoint.
+ cyg_hal_gdb_interrupt((target_register_t)__builtin_return_address(0));
+ break;
+ }
#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
- // otherwise, loop round again
- }
+ // otherwise, loop round again
+ }
- pos = 0;
+ pos = 0;
- // And re-enable interrupts
+ // And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
- CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+ CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
- HAL_RESTORE_INTERRUPTS(old);
+ HAL_RESTORE_INTERRUPTS(old);
#endif
-
- }
+ }
}
#endif
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
-#include <cyg/infra/cyg_type.h> // base types
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_misc.h> // Size constants
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/hal_intr.h> // Interrupt names
-#include <cyg/hal/hal_cache.h> // Cache control
-#include <cyg/hal/hal_soc.h> // Hardware definitions
-#include <cyg/hal/hal_mm.h> // MMap table definitions
-
-#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
+#include <cyg/infra/diag.h> // diag_printf
+#ifdef MXCFLASH_SELECT_NAND
+#include <cyg/io/imx_nfc.h>
+#endif
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
// FIXME: some of the stuff in hal_platform_setup could be moved here.
-externC void plf_hardware_init(void);
int _mxc_fis;
/*
*/
unsigned int system_rev = CHIP_REV_1_0;
static int find_correct_chip;
-extern char HAL_PLATFORM_EXTRA[20];
-extern int _mxc_fis;
+
static int _reset_reason;
-struct soc_sbmr {
- unsigned int bt_mem_ctl:2,
- bt_bus_width:1,
- bt_page_size:2,
- rsv2:1,
- bt_spare_size:1,
- bt_mem_type:2,
- rsv1:1,
- bt_ecc_sel:1,
- bt_usb_src_0:1,
- bt_eeprom_cfg:1,
- dir_bt_dis:1,
- bmod:2,
- bt_weim_muxed:2,
- bt_spare:1,
- bt_sdmmc_src:2,
- bt_chih_freq_sel:2,
- bt_i2c_src:2,
- bt_uart_src:2,
- bt_cspi_src:2,
- rsv0:3;
-} __attribute__ ((packed));
-struct soc_sbmr *soc_sbmr = (struct soc_sbmr *) (SRC_BASE_ADDR + 0x4);
+#define SBMR_BT_MEM_CTL_SHIFT 0
+#define SBMR_BT_MEM_CTL_MASK (3 << SBMR_BT_MEM_CTL_SHIFT)
+#define SBMR_BT_MEM_CTL(r) (((r) & SBMR_BT_MEM_CTL_MASK) >> SBMR_BT_MEM_CTL_SHIFT)
+#define SBMR_BT_BUS_WIDTH_SHIFT 2
+#define SBMR_BT_BUS_WIDTH_MASK (1 << SBMR_BT_BUS_WIDTH_SHIFT)
+#define SBMR_BT_BUS_WIDTH(r) (((r) & SBMR_BT_BUS_WIDTH_MASK) >> SBMR_BT_BUS_WIDTH_SHIFT)
+#define SBMR_BT_PAGE_SIZE_SHIFT 3
+#define SBMR_BT_PAGE_SIZE_MASK (3 << SBMR_BT_PAGE_SIZE_SHIFT)
+#define SBMR_BT_PAGE_SIZE(r) (((r) & SBMR_BT_PAGE_SIZE_MASK) >> SBMR_BT_PAGE_SIZE_SHIFT)
+#define SBMR_BT_SPARE_SIZE_SHIFT 6
+#define SBMR_BT_SPARE_SIZE_MASK (1 << SBMR_BT_SPARE_SIZE_SHIFT)
+#define SBMR_BT_SPARE_SIZE(r) (((r) & SBMR_BT_SPARE_SIZE_MASK) >> SBMR_BT_SPARE_SIZE_SHIFT)
+#define SBMR_BT_MEM_TYPE_SHIFT 7
+#define SBMR_BT_MEM_TYPE_MASK (3 << SBMR_BT_MEM_TYPE_SHIFT)
+#define SBMR_BT_MEM_TYPE(r) (((r) & SBMR_BT_MEM_TYPE_MASK) >> SBMR_BT_MEM_TYPE_SHIFT)
+#define SBMR_BT_MLC_SEL_SHIFT 10
+#define SBMR_BT_MLC_SEL_MASK (1 << SBMR_BT_MLC_SEL_SHIFT)
+#define SBMR_BT_MLC_SEL(r) (((r) & SBMR_BT_MLC_SEL_MASK) >> SBMR_BT_MLC_SEL_SHIFT)
+//#define SBMR_BT_USB_SRC_0_SHIFT 11
+//#define SBMR_BT_USB_SRC_0_MASK (1 << ) /* reserved in Ref. Manual *SBMR_BT_USB_SRC_0_SHIFT/
+//#define SBMR_BT_USB_SRC_0(r) (((r) & SBMR_BT_USB_SRC_0_MASK) >> SBMR_BT_USB_SRC_0_SHIFT)
+#ifdef UNUSED
+#define SBMR_BT_EEPROM_CFG_SHIFT 12
+#define SBMR_BT_EEPROM_CFG_MASK (1 << SBMR_BT_EEPROM_CFG_SHIFT)
+#define SBMR_BT_EEPROM_CFG(r) (((r) & SBMR_BT_EEPROM_CFG_MASK) >> SBMR_BT_EEPROM_CFG_SHIFT)
+#endif
+#define SBMR_DIR_BT_DIS_SHIFT 13
+#define SBMR_DIR_BT_DIS_MASK (1 << SBMR_DIR_BT_DIS_SHIFT)
+#define SBMR_DIR_BT_DIS(r) (((r) & SBMR_DIR_BT_DIS_MASK) >> SBMR_DIR_BT_DIS_SHIFT)
+#define SBMR_BMOD_SHIFT 14
+#define SBMR_BMOD_MASK (3 << SBMR_BMOD_SHIFT)
+#define SBMR_BMOD(r) (((r) & SBMR_BMOD_MASK) >> SBMR_BMOD_SHIFT)
+#define SBMR_BT_WEIM_MUXED_SHIFT 16
+#define SBMR_BT_WEIM_MUXED_MASK (3 << SBMR_BT_WEIM_MUXED_SHIFT)
+#ifdef UNUSED
+#define SBMR_BT_WEIM_MUXED(r) (((r) & SBMR_BT_WEIM_MUXED_MASK) >> SBMR_BT_WEIM_MUXED_SHIFT)
+#define SBMR_BT_LPB_EN_SHIFT 18
+#define SBMR_BT_LPB_EN_MASK (1 << SBMR_BT_LPB_EN_SHIFT)
+#define SBMR_BT_LPB_EN(r) (((r) & SBMR_BT_LPB_EN_MASK) >> SBMR_BT_LPB_EN_SHIFT)
+#endif
+#define SBMR_BT_SDMMC_SRC_SHIFT 19
+#define SBMR_BT_SDMMC_SRC_MASK (3 << SBMR_BT_SDMMC_SRC_SHIFT)
+#define SBMR_BT_SDMMC_SRC(r) (((r) & SBMR_BT_SDMMC_SRC_MASK) >> SBMR_BT_SDMMC_SRC_SHIFT)
+#ifdef UNUSED
+#define SBMR_BT_OSC_FREQ_SEL_SHIFT 21
+#define SBMR_BT_OSC_FREQ_SEL_MASK (3 << SBMR_BT_OSC_FREQ_SEL_SHIFT)
+#define SBMR_BT_OSC_FREQ_SEL(r) (((r) & SBMR_BT_OSC_FREQ_SEL_MASK) >> SBMR_BT_OSC_FREQ_SEL_SHIFT)
+#define SBMR_BT_LPB_SHIFT 23
+#define SBMR_BT_LPB_MASK (3 << SBMR_BT_LPB_SHIFT)
+#define SBMR_BT_LPB(r) (((r) & SBMR_BT_LPB_MASK) >> SBMR_BT_LPB_SHIFT)
+#define SBMR_BT_UART_SRC_SHIFT 25
+#define SBMR_BT_UART_SRC_MASK (3 << SBMR_BT_UART_SRC_SHIFT)
+#define SBMR_BT_UART_SRC(r) (((r) & SBMR_BT_UART_SRC_MASK) >> SBMR_BT_UART_SRC_SHIFT)
+#define SBMR_BT_USB_SRC_SHIFT 27
+#define SBMR_BT_USB_SRC_MASK (3 << SBMR_BT_USB_SRC_SHIFT)
+#define SBMR_BT_USB_SRC(r) (((r) & SBMR_BT_USB_SRC_MASK) >> SBMR_BT_USB_SRC_SHIFT)
+#define SBMR_BT_HPN_EN_SHIFT 28
+#define SBMR_BT_HPN_EN_MASK (1 << SBMR_BT_HPN_EN_SHIFT)
+#define SBMR_BT_HPN_EN(r) (((r) & SBMR_BT_HPN_EN_MASK) >> SBMR_BT_HPN_EN_SHIFT)
+#define SBMR_BT_LPB_FREQ_SHIFT 29
+#define SBMR_BT_LPB_FREQ_MASK (7 << SBMR_BT_LPB_FREQ_SHIFT)
+#define SBMR_BT_LPB_FREQ(r) (((r) & SBMR_BT_LPB_FREQ_MASK) >> SBMR_BT_LPB_FREQ_SHIFT)
+#endif
+
/*
* This functions reads the IIM module and returns the system revision number.
* It returns the IIM silicon revision reg value if valid product rev is found.
*/
static int read_system_rev(void)
{
- int val;
- int *rom_id_address;
+ int val;
+ int *rom_id_address;
- rom_id_address = ROM_BASE_ADDRESS_VIRT + ROM_SI_REV_OFFSET;
+ rom_id_address = (int *)((unsigned long)ROM_BASE_ADDR_VIRT + ROM_SI_REV_OFFSET);
- val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
- system_rev = 0x51 << PART_NUMBER_OFFSET; /* For MX51 Platform*/
+ system_rev = 0x51 << PART_NUMBER_OFFSET; /* For MX51 Platform*/
- /* Now trying to retrieve the silicon rev from IIM's SREV register */
- return *rom_id_address;
+ /* Now try to retrieve the silicon rev from IIM's SREV register */
+ return *rom_id_address;
}
#ifdef MXCFLASH_SELECT_NAND
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips);
extern nfc_setup_func_t *nfc_setup;
#endif
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
- unsigned int is_mlc, unsigned int num_of_chips);
+
+#ifdef MXCFLASH_SELECT_MMC
+//extern mxc_mmc_check_sdhc_boot_slot *check_sdhc_slot;
+#endif
+
+int mxc_check_sdhc_boot_slot(unsigned int port, unsigned int *sdhc_addr);
+
void hal_hardware_init(void)
{
- int ver = read_system_rev();
- unsigned int i;
- unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
-
- _reset_reason = readl(SRC_BASE_ADDR + 0x8);
- switch (*fis_addr) {
- case FROM_MMC_FLASH:
- _mxc_fis = FROM_MMC_FLASH;
- break;
- case FROM_NAND_FLASH:
- _mxc_fis = FROM_NAND_FLASH;
- break;
- case FROM_SPI_NOR_FLASH:
- _mxc_fis = FROM_SPI_NOR_FLASH;
- break;
- default:
- if (soc_sbmr->bt_mem_ctl == 0x3) {
- if (soc_sbmr->bt_mem_type == 0) {
- _mxc_fis = MMC_FLASH_BOOT;
- } else if (soc_sbmr->bt_mem_type == 3) {
- _mxc_fis = SPI_NOR_FLASH_BOOT;
- }
- } else if (soc_sbmr->bt_mem_ctl == 1) {
- _mxc_fis = NAND_FLASH_BOOT;
- }
- }
-
- find_correct_chip = ver;
-
- if (ver != CHIP_VERSION_NONE) {
- /* Valid product revision found. Check actual silicon rev from the ROM code. */
- if (ver == 0x1) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else if (ver == 0x2) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else if (ver == 0x10) {
- HAL_PLATFORM_EXTRA[5] = '2';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 2 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else {
- HAL_PLATFORM_EXTRA[5] = 'x';
- HAL_PLATFORM_EXTRA[7] = 'x';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- find_correct_chip = CHIP_VERSION_UNKNOWN;
- }
-
- }
- // Enable caches
- HAL_ICACHE_ENABLE();
- HAL_DCACHE_ENABLE();
-
- // enable EPIT and start it with 32KHz input clock
- writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
-
- // make sure reset is complete
- while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
- }
-
- writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
- writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
-
- writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
-
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- // increase the WDOG timeout value to the max
- writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
- }
-
- // Perform any platform specific initializations
- plf_hardware_init();
-
- // Set up eCos/ROM interfaces
- hal_if_init();
-
- // initial NAND setup
- writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD4_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD5_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD6_REG);
- writel(0xFFFF0000, UNLOCK_BLK_ADD7_REG);
-
- // unlock all the CS's
- for (i = 0; i < 8; i++) {
- writel(0x84 | (i << 3), NFC_WR_PROT_REG);
- }
- writel(0, NFC_IPC_REG);
+ int ver = read_system_rev();
+ unsigned int i;
+#ifndef CYGPKG_HAL_ARM_TX51KARO
+ unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4);
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ switch (*fis_addr) {
+ case FROM_MMC_FLASH:
+ _mxc_fis = FROM_MMC_FLASH;
+ break;
+ case FROM_NAND_FLASH:
+ _mxc_fis = FROM_NAND_FLASH;
+ break;
+ case FROM_SPI_NOR_FLASH:
+ _mxc_fis = FROM_SPI_NOR_FLASH;
+ break;
+ default:
+ if (SBMR_BT_MEM_CTL(sbmr) == 0x3) {
+ if (SBMR_BT_MEM_TYPE(sbmr) == 0) {
+ _mxc_fis = MMC_FLASH_BOOT;
+ *fis_addr = FROM_MMC_FLASH;
+ } else if (SBMR_BT_MEM_TYPE(sbmr) == 3) {
+ _mxc_fis = SPI_NOR_FLASH_BOOT;
+ *fis_addr = FROM_SPI_NOR_FLASH;
+ }
+ } else if (SBMR_BT_MEM_CTL(sbmr) == 1) {
+ _mxc_fis = NAND_FLASH_BOOT;
+ *fis_addr = FROM_NAND_FLASH;
+ }
+ }
+#else
+ _mxc_fis = FROM_NAND_FLASH;
+#endif
+
+ _reset_reason = readl(SRC_BASE_ADDR + 0x8);
+
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev from the ROM code. */
+ if (ver == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x2) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x10) {
+ HAL_PLATFORM_EXTRA[5] = '2';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 2 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x20) {
+ HAL_PLATFORM_EXTRA[5] = '3';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 3 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'x';
+ HAL_PLATFORM_EXTRA[7] = 'x';
+ system_rev |= 3 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+
+ }
+ // Enable caches
+#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+ HAL_ICACHE_ENABLE();
+#endif
+#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+ HAL_DCACHE_ENABLE();
+#endif
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ // initial NAND setup
+ writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD4_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD5_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD6_REG);
+ writel(0xFFFF0000, UNLOCK_BLK_ADD7_REG);
+
+ // unlock all the CS's
+ for (i = 0; i < 8; i++) {
+ writel(0x84 | (i << 3), NFC_WR_PROT_REG);
+ }
+ writel(0, NFC_IPC_REG);
#ifdef MXCFLASH_SELECT_NAND
- nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+ nfc_setup = mxc_nfc_soc_setup;
#endif
}
unsigned int hal_timer_count(void)
{
- return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
}
-#define WDT_MAGIC_1 0x5555
-#define WDT_MAGIC_2 0xAAAA
-#define MXC_WDT_WSR 0x2
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
unsigned int i2c_base_addr[] = {
- I2C_BASE_ADDR,
- I2C2_BASE_ADDR,
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
};
unsigned int i2c_num = 2;
+static unsigned int led_on = 0;
//
// Delay for some number of micro-seconds
//
void hal_delay_us(unsigned int usecs)
{
- /*
- * This causes overflow.
- * unsigned int delayCount = (usecs * 32768) / 1000000;
- * So use the following one instead
- */
- unsigned int delayCount = (usecs * 512) / 15625;
-
- if (delayCount == 0) {
- return;
- }
-
- // issue the service sequence instructions
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
- writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
- }
-
- writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
-
- writel(delayCount, EPIT_BASE_ADDR + EPITLR);
-
- while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32768) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs * 512) / 15625;
+
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
+
+ if (delayCount == 0) {
+ return;
+ }
+
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ if ((++led_on % 3000) == 0)
+ BOARD_DEBUG_LED(0);
}
// -------------------------------------------------------------------------
int hal_IRQ_handler(void)
{
#ifdef HAL_EXTENDED_IRQ_HANDLER
- cyg_uint32 index;
+ cyg_uint32 index;
- // Use platform specific IRQ handler, if defined
- // Note: this macro should do a 'return' with the appropriate
- // interrupt number if such an extended interrupt exists. The
- // assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
#endif
- return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}
//
{
// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_MASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_MASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
}
// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
}
// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
#endif
- // Interrupt priorities are not configurable.
+ // Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+#ifdef MXCFLASH_SELECT_NAND
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips)
{
- unsigned int nfc_config_reg3;
-
- if (pg_sz == 2048 && io_sz == 8) {
- writel(0x70202179, NFC_FLASH_CONFIG2_REG);
- nfc_config_reg3 = 0x00160608 | ((num_of_chips - 1) << 12);
- if (num_of_chips > 1)
- nfc_config_reg3 |= 0x1;
- writel(nfc_config_reg3, NFC_FLASH_CONFIG3_REG);
- } else if (pg_sz == 4096 && io_sz == 8) {
- // This only works for 4KB with 218 spare area size
- writel(0x706D217A, NFC_FLASH_CONFIG2_REG); // default is 0x706D273A
- nfc_config_reg3 = 0x00120608 | ((num_of_chips - 1) << 12);
- if (num_of_chips > 1)
- nfc_config_reg3 |= 0x1;
- writel(nfc_config_reg3, NFC_FLASH_CONFIG3_REG);
- } else {
- diag_printf("not supported nand flash: pg_sz=%d, io_sz=%d\n",
- pg_sz, io_sz);
- while (1) {
- }
- }
- return MXC_NFC_V3;
+ unsigned int src_scr_reg;
+ unsigned int tmp;
+
+ tmp = readl(NFC_FLASH_CONFIG2_REG);
+ /* Set the ST_CMD to be 0x70 for all NAND devices */
+ tmp &= ~(0xFF << 24);
+ tmp |= (0x70 << 24);
+#ifndef CYGPKG_HAL_ARM_TX51KARO
+ /* Set the Spare size */
+ tmp &= ~(0xFF << 16);
+ //tmp |= (((flash_params->spare_size & 0xFF) / 2) << 16);
+ tmp |= (64 / 2) << 16;
+#else
+ tmp = (tmp & ~(0xff << 16)) | ((64 / 2) << 16);
+#endif
+ /* Set the Page Size */
+ tmp &= ~(0x3);
+ switch (pg_sz) {
+ case 512:
+ tmp |= 0x0;
+ break;
+ case 2048:
+ tmp |= 0x1;
+ break;
+ case 4096:
+ default:
+ tmp |= 0x2;
+ break;
+ }
+#ifndef CYGPKG_HAL_ARM_TX51KARO
+ /* Set ECC mode */
+#if 0
+ if (flash_params->spare_size >= 218) {
+ /* Use 8-bit ECC */
+ tmp |= (0x1 << 6);
+ } else {
+ tmp &= ~(0x1 << 6);
+ }
+#else
+ tmp = (tmp & ~(1 << 6)) | (0 << 6);
+#endif
+#else
+ tmp = (tmp & ~(1 << 6)) | (0 << 6);
+#endif
+#ifndef CYGPKG_HAL_ARM_TX51KARO
+ /* Pages per block */
+ tmp &= ~(0x3 << 7);
+#if 0
+ switch (flash_params->pages_per_block) {
+ case 32:
+ tmp |= 0x0;
+ break;
+ case 64:
+ tmp |= (0x1 << 7);
+ break;
+ case 128:
+ tmp |= (0x2 << 7);
+ break;
+ case 256:
+ default:
+ tmp |= (0x3 << 7);
+ break;
+ }
+#else
+ tmp = (tmp & ~(3 << 7)) | (1 << 7);
+#endif
+#else
+ tmp = (tmp & ~(3 << 7)) | (1 << 7);
+#endif
+ /* Set the number of phase bits & ECC enable bit to default value */
+ tmp &= ~(0x3 << 12);
+ tmp |= 0x2038;
+ writel(tmp, NFC_FLASH_CONFIG2_REG);
+
+ tmp = readl(NFC_FLASH_CONFIG3_REG);
+ /* Set the No SDMA bit */
+ tmp |= (0x1 << 20);
+ /* Set the Status Busy Bit to 0x6 (default) */
+ tmp &= ~(0x7 << 8);
+ tmp |= (0x6 << 8);
+ /* Set the Flash Width */
+ if (io_sz == MXC_NAND_16_BIT) {
+ tmp &= ~(1 << 3);
+ } else {
+ tmp |= 1 << 3;
+ }
+ /* Set the Number of Nand Chips */
+ tmp &= ~(0x7 << 12);
+ tmp |= ((num_of_chips - 1) << 12);
+ if (num_of_chips > 1)
+ tmp |= 0x1;
+ writel(tmp, NFC_FLASH_CONFIG3_REG);
+
+ if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
+ unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4);
+
+ /* This issue is fixed in MX51 TO 3.0 */
+ /* Workaround to disable WARM RESET when booting from interleaved NAND devices */
+ if ((num_of_chips > 1) && (SBMR_BT_MEM_CTL(sbmr) == 1)) {
+ diag_printf("%s: Disabling WARM reset due to boot from interleaved NAND\n", __FUNCTION__);
+ src_scr_reg = readl(SRC_BASE_ADDR);
+ src_scr_reg &= ~0x1;
+ writel(src_scr_reg, SRC_BASE_ADDR);
+ }
+ }
+
+ return MXC_NFC_V3;
}
+#endif
static void show_sys_info(void)
{
- if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
- diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
- diag_printf("Assuming chip version=0x%x\n", system_rev);
- } else if (find_correct_chip == CHIP_VERSION_NONE) {
- diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
- }
-
- diag_printf("Reset reason: ");
- switch (_reset_reason) {
- case 0x09:
- diag_printf("User reset\n");
- break;
- case 0x01:
- diag_printf("Power-on reset\n");
- break;
- case 0x10:
- case 0x11:
- diag_printf("WDOG reset\n");
- break;
- default:
- diag_printf("Unknown: 0x%x\n", _reset_reason);
- }
-
- if (_mxc_fis == MMC_FLASH_BOOT) {
- diag_printf("fis/fconfig from MMC\n");
- } else if (_mxc_fis == SPI_NOR_FLASH_BOOT) {
- diag_printf("fis/fconfig from SPI-NOR\n");
- } else if (_mxc_fis == NAND_FLASH_BOOT) {
- diag_printf("fis/fconfig from NAND\n");
- } else {
- diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n");
- }
-
- //diag_printf("SBMR = 0x%x\n", readl(SRC_BASE_ADDR + 0x4));
- diag_printf("Boot switch: ");
- if (soc_sbmr->bmod == 0) {
- diag_printf("INTERNAL\n");
- } else if (soc_sbmr->bmod == 3){
- diag_printf("BOOTSTRAP\n");
- } else if (soc_sbmr->bmod == 0x1 && soc_sbmr->dir_bt_dis == 0) {
- diag_printf("TEST EXEC\n");
- } else {
- diag_printf("UNKNOWN\n");
- }
- diag_printf("\t");
- if (soc_sbmr->bt_mem_ctl == 0) {
- diag_printf("WEIM: ");
- if (soc_sbmr->bt_mem_type == 0) {
- diag_printf("NOR");
- } else if (soc_sbmr->bt_mem_type == 2) {
- diag_printf("ONE NAND");
- } else {
- diag_printf("UNKNOWN");
- }
- } else if (soc_sbmr->bt_mem_ctl == 1) {
- diag_printf("NAND: ADDR CYCLES:");
- if (soc_sbmr->bt_mem_type == 0) {
- diag_printf("3: ");
- } else if (soc_sbmr->bt_mem_type == 1) {
- diag_printf("4: ");
- } else if (soc_sbmr->bt_mem_type == 2) {
- diag_printf("5: ");
- } else {
- diag_printf("UNKNOWN: ");
- }
- if (soc_sbmr->bt_ecc_sel == 0) {
- diag_printf("SLC: ");
- } else {
- diag_printf("MLC: ");
- }
- if (soc_sbmr->bt_spare_size == 0) {
- diag_printf("128B spare (4-bit ECC): ");
- } else {
- diag_printf("218B spare (8-bit ECC): ");
- }
- diag_printf("PAGE SIZE: ");
- if (soc_sbmr->bt_page_size == 0) {
- diag_printf("512: ");
- } else if (soc_sbmr->bt_page_size == 1) {
- diag_printf("2K: ");
- } else if (soc_sbmr->bt_page_size == 2) {
- diag_printf("4K: ");
- } else {
- diag_printf("UNKNOWN: ");
- }
- diag_printf("BUS WIDTH: ");
- if (soc_sbmr->bt_bus_width == 0) {
- diag_printf("8");
- } else {
- diag_printf("16");
- }
- } else if (soc_sbmr->bt_mem_ctl == 3) {
- diag_printf("EXPANSION: ");
- if (soc_sbmr->bt_mem_type == 0) {
- diag_printf("SD/MMC-%d", soc_sbmr->bt_sdmmc_src);
- } else if (soc_sbmr->bt_mem_type == 2) {
- diag_printf("I2C-NOR: ");
- if (soc_sbmr->bt_sdmmc_src == 0) {
- diag_printf("I2C-1");
- } else if (soc_sbmr->bt_sdmmc_src == 1) {
- diag_printf("I2C-2");
- } else if (soc_sbmr->bt_sdmmc_src == 2) {
- diag_printf("HS-I2C");
- } else {
- diag_printf("UNKNOWN");
- }
- } else if (soc_sbmr->bt_mem_type == 3) {
- diag_printf("SPI-NOR: ");
- if (soc_sbmr->bt_sdmmc_src == 0) {
- diag_printf("eCSPI1");
- } else if (soc_sbmr->bt_sdmmc_src == 1) {
- diag_printf("eCSPI2");
- } else if (soc_sbmr->bt_sdmmc_src == 2) {
- diag_printf("CSPI");
- } else {
- diag_printf("UNKNOWN");
- }
- } else {
- diag_printf("UNKNOWN");
- }
- } else {
- diag_printf("UNKNOWN");
- }
- diag_printf("\n");
+ unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4);
+
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%08x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%08x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%08x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
+
+ diag_printf("Reset reason: ");
+ switch (_reset_reason) {
+ case 0x09:
+ diag_printf("User reset\n");
+ break;
+ case 0x01:
+ diag_printf("Power-on reset\n");
+ break;
+ case 0x10:
+ case 0x11:
+ diag_printf("WDOG reset\n");
+ break;
+ default:
+ diag_printf("Unknown: 0x%08x\n", _reset_reason);
+ }
+
+ if (_mxc_fis == MMC_FLASH_BOOT) {
+ diag_printf("fis/fconfig from MMC\n");
+ } else if (_mxc_fis == SPI_NOR_FLASH_BOOT) {
+ diag_printf("fis/fconfig from SPI-NOR\n");
+ } else if (_mxc_fis == NAND_FLASH_BOOT) {
+ diag_printf("fis/fconfig from NAND\n");
+ } else {
+ diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n");
+ }
+
+ diag_printf("SBMR = 0x%08x\n", readl(SRC_BASE_ADDR + 0x4));
+ diag_printf("Boot switch: ");
+ if ((SBMR_BMOD(sbmr)) == 0) {
+ diag_printf("INTERNAL (GPIO)\n");
+ } else if ((SBMR_BMOD(sbmr)) == 2) {
+ diag_printf("INTERNAL (FUSE)\n");
+ } else if ((SBMR_BMOD(sbmr)) == 3){
+ diag_printf("BOOTSTRAP\n");
+ } else if ((SBMR_BMOD(sbmr)) == 0x1 && (SBMR_DIR_BT_DIS(sbmr)) == 0) {
+ diag_printf("TEST EXEC\n");
+ } else {
+ diag_printf("UNKNOWN: 0x%x\n", SBMR_BMOD(sbmr));
+ }
+ diag_printf("\t");
+ if ((SBMR_BT_MEM_CTL(sbmr)) == 0) {
+ diag_printf("WEIM: ");
+ if ((SBMR_BT_MEM_TYPE(sbmr)) == 0) {
+ diag_printf("NOR");
+ } else if ((SBMR_BT_MEM_TYPE(sbmr)) == 2) {
+ diag_printf("ONE NAND");
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_MEM_TYPE(sbmr));
+ }
+ } else if ((SBMR_BT_MEM_CTL(sbmr)) == 1) {
+ diag_printf("NAND: ADDR CYCLES:");
+ if ((SBMR_BT_MEM_TYPE(sbmr)) == 0) {
+ diag_printf("3: ");
+ } else if ((SBMR_BT_MEM_TYPE(sbmr)) == 1) {
+ diag_printf("4: ");
+ } else if ((SBMR_BT_MEM_TYPE(sbmr)) == 2) {
+ diag_printf("5: ");
+ } else {
+ diag_printf("UNKNOWN: 0x%x ", SBMR_BT_MEM_TYPE(sbmr));
+ }
+ if (SBMR_BT_MLC_SEL(sbmr) == 0) {
+ diag_printf("SLC: ");
+ } else {
+ diag_printf("MLC: ");
+ }
+ if ((SBMR_BT_SPARE_SIZE(sbmr)) == 0) {
+ diag_printf("128B spare (4-bit ECC): ");
+ } else {
+ diag_printf("218B spare (8-bit ECC): ");
+ }
+ diag_printf("PAGE SIZE: ");
+ if ((SBMR_BT_PAGE_SIZE(sbmr)) == 0) {
+ diag_printf("512: ");
+ } else if ((SBMR_BT_PAGE_SIZE(sbmr)) == 1) {
+ diag_printf("2K: ");
+ } else if ((SBMR_BT_PAGE_SIZE(sbmr)) == 2) {
+ diag_printf("4K: ");
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_PAGE_SIZE(sbmr));
+ }
+ diag_printf("BUS WIDTH: ");
+ if ((SBMR_BT_BUS_WIDTH(sbmr)) == 0) {
+ diag_printf("8");
+ } else {
+ diag_printf("16");
+ }
+ } else if ((SBMR_BT_MEM_CTL(sbmr)) == 3) {
+ diag_printf("EXPANSION: ");
+ if ((SBMR_BT_MEM_TYPE(sbmr)) == 0) {
+ diag_printf("SD/MMC-%d", (SBMR_BT_SDMMC_SRC(sbmr)));
+ } else if ((SBMR_BT_MEM_TYPE(sbmr)) == 2) {
+ diag_printf("I2C-NOR: ");
+ if ((SBMR_BT_SDMMC_SRC(sbmr)) == 0) {
+ diag_printf("I2C-1");
+ } else if ((SBMR_BT_SDMMC_SRC(sbmr)) == 1) {
+ diag_printf("I2C-2");
+ } else if ((SBMR_BT_SDMMC_SRC(sbmr)) == 2) {
+ diag_printf("HS-I2C");
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_SDMMC_SRC(sbmr));
+ }
+ } else if ((SBMR_BT_MEM_TYPE(sbmr)) == 3) {
+ diag_printf("SPI-NOR: ");
+ if ((SBMR_BT_SDMMC_SRC(sbmr)) == 0) {
+ diag_printf("eCSPI1");
+ } else if ((SBMR_BT_SDMMC_SRC(sbmr)) == 1) {
+ diag_printf("eCSPI2");
+ } else if ((SBMR_BT_SDMMC_SRC(sbmr)) == 2) {
+ diag_printf("CSPI");
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_SDMMC_SRC(sbmr));
+ }
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_MEM_TYPE(sbmr));
+ }
+ } else {
+ diag_printf("UNKNOWN: 0x%x", SBMR_BT_MEM_CTL(sbmr));
+ }
+ diag_printf("\n");
}
RedBoot_init(show_sys_info, RedBoot_INIT_LAST);
projects / karo-tx-redboot.git / commitdiff