arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

   1 /*
   2  * Freescale i.MX28 Boot PMIC init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <config.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14
  15 #include "mxs_init.h"
  16
  17 #ifdef CONFIG_SYS_SPL_VDDD_VAL
  18 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
  19 #else
  20 #define VDDD_VAL        1350
  21 #endif
  22 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
  23 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
  24 #else
  25 #define VDDIO_VAL       3300
  26 #endif
  27 #ifdef CONFIG_SYS_SPL_VDDA_VAL
  28 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
  29 #else
  30 #define VDDA_VAL        1800
  31 #endif
  32 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
  33 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
  34 #else
  35 #define VDDMEM_VAL      1700
  36 #endif
  37
  38 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
  39 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
  40 #else
  41 #define VDDD_BO_VAL     150
  42 #endif
  43 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
  44 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
  45 #else
  46 #define VDDIO_BO_VAL    150
  47 #endif
  48 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
  49 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
  50 #else
  51 #define VDDA_BO_VAL     175
  52 #endif
  53 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
  54 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
  55 #else
  56 #define VDDMEM_BO_VAL   25
  57 #endif
  58
  59 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
  60 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
  61 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
  62 #endif
  63 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
  64 #else
  65 /* Brownout default at 3V */
  66 #define BATT_BO_VAL     ((3000 - 2400) / 40)
  67 #endif
  68
  69 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
  70 static const int fixed_batt_supply = 1;
  71 #else
  72 static const int fixed_batt_supply;
  73 #endif
  74
  75 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
  76
  77 /**
  78  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  79  *
  80  * This function switches the CPU core clock from PLL to 24MHz XTAL
  81  * oscilator. This is necessary if the PLL is being reconfigured to
  82  * prevent crash of the CPU core.
  83  */
  84 static void mxs_power_clock2xtal(void)
  85 {
  86         struct mxs_clkctrl_regs *clkctrl_regs =
  87                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  88
  89         /* Set XTAL as CPU reference clock */
  90         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  91                 &clkctrl_regs->hw_clkctrl_clkseq_set);
  92 }
  93
  94 /**
  95  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  96  *
  97  * This function switches the CPU core clock from 24MHz XTAL oscilator
  98  * to PLL. This can only be called once the PLL has re-locked and once
  99  * the PLL is stable after reconfiguration.
 100  */
 101 static void mxs_power_clock2pll(void)
 102 {
 103         struct mxs_clkctrl_regs *clkctrl_regs =
 104                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 105
 106         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
 107                         CLKCTRL_PLL0CTRL0_POWER);
 108         early_delay(100);
 109         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
 110                         CLKCTRL_CLKSEQ_BYPASS_CPU);
 111 }
 112
 113 static int mxs_power_wait_rtc_stat(u32 mask)
 114 {
 115         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
 116         u32 val;
 117         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 118
 119         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
 120                 early_delay(1);
 121                 if (timeout-- < 0)
 122                         break;
 123         }
 124         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
 125 }
 126
 127 /**
 128  * mxs_power_set_auto_restart() - Set the auto-restart bit
 129  *
 130  * This function ungates the RTC block and sets the AUTO_RESTART
 131  * bit to work around a design bug on MX28EVK Rev. A .
 132  */
 133 static int mxs_power_set_auto_restart(int on)
 134 {
 135         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 136
 137         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
 138                 return 1;
 139
 140         /* Do nothing if flag already set */
 141         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 142                 return 0;
 143
 144         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
 145                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
 146                 return 0;
 147
 148         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 149                 return 1;
 150
 151         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
 152                         !on * RTC_PERSISTENT0_AUTO_RESTART,
 153                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
 154         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 155                 return 1;
 156
 157         return 0;
 158 }
 159
 160 /**
 161  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
 162  *
 163  * This function configures the VDDIO, VDDA and VDDD linear regulators output
 164  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
 165  * converter. This is the recommended setting for the case where we use both
 166  * linear regulators and DC-DC converter to power the VDDIO rail.
 167  */
 168 static void mxs_power_set_linreg(void)
 169 {
 170         /* Set linear regulator 25mV below switching converter */
 171         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 172                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 173                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 174
 175         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 176                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 177                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 178
 179         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 180                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 181                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 182 }
 183
 184 /**
 185  * mxs_get_batt_volt() - Measure battery input voltage
 186  *
 187  * This function retrieves the battery input voltage and returns it.
 188  */
 189 static int mxs_get_batt_volt(void)
 190 {
 191         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 192
 193         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 194         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 195         volt *= 8;
 196         return volt;
 197 }
 198
 199 /**
 200  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
 201  *
 202  * This function checks if the battery input voltage is higher than 3.6V and
 203  * therefore allows the system to successfully boot using this power source.
 204  */
 205 static int mxs_is_batt_ready(void)
 206 {
 207         return (mxs_get_batt_volt() >= 3600);
 208 }
 209
 210 /**
 211  * mxs_is_batt_good() - Test if battery is operational at all
 212  *
 213  * This function starts recharging the battery and tests if the input current
 214  * provided by the 5V input recharging the battery is also sufficient to power
 215  * the DC-DC converter.
 216  */
 217 static int mxs_is_batt_good(void)
 218 {
 219         uint32_t volt = mxs_get_batt_volt();
 220
 221         if ((volt >= 2400) && (volt <= 4300))
 222                 return 1;
 223
 224         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 225                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 226                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 227         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 228                 &power_regs->hw_power_5vctrl_clr);
 229
 230         clrsetbits_le32(&power_regs->hw_power_charge,
 231                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 232                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 233
 234         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 235         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 236                 &power_regs->hw_power_5vctrl_clr);
 237
 238         early_delay(500000);
 239
 240         volt = mxs_get_batt_volt();
 241
 242         if (volt >= 3500)
 243                 return 0;
 244
 245         if (volt >= 2400)
 246                 return 1;
 247
 248         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 249                 &power_regs->hw_power_charge_clr);
 250         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
 257  *
 258  * This function enables the 5V detection comparator and sets the 5V valid
 259  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
 260  * under high load, the voltage drop on the 5V input won't be so critical
 261  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
 262  * converter and thus making the system crash.
 263  */
 264 static void mxs_power_setup_5v_detect(void)
 265 {
 266         /* Start 5V detection */
 267         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 268                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 269                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 270                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 271 }
 272
 273 /**
 274  * mxs_src_power_init() - Preconfigure the power block
 275  *
 276  * This function configures reasonable values for the DC-DC control loop
 277  * and battery monitor.
 278  */
 279 static void mxs_src_power_init(void)
 280 {
 281         /* Improve efficieny and reduce transient ripple */
 282         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 283                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 284
 285         clrsetbits_le32(&power_regs->hw_power_dclimits,
 286                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 287                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 288
 289         if (!fixed_batt_supply) {
 290                 /* FIXME: This requires the LRADC to be set up! */
 291                 setbits_le32(&power_regs->hw_power_battmonitor,
 292                         POWER_BATTMONITOR_EN_BATADJ);
 293         } else {
 294                 clrbits_le32(&power_regs->hw_power_battmonitor,
 295                         POWER_BATTMONITOR_EN_BATADJ);
 296         }
 297
 298         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 299         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 300                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 301                         POWER_LOOPCTRL_RCSCALE_THRESH |
 302                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 303
 304         clrsetbits_le32(&power_regs->hw_power_minpwr,
 305                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 306
 307         if (!fixed_batt_supply) {
 308                 /* 5V to battery handoff ... FIXME */
 309                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 310                 early_delay(30);
 311                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 312         }
 313 }
 314
 315 /**
 316  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
 317  *
 318  * This function configures the necessary parameters for the 4P2 linear
 319  * regulator to supply the DC-DC converter from 5V input.
 320  */
 321 static void mxs_power_init_4p2_params(void)
 322 {
 323         /* Setup 4P2 parameters */
 324         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 325                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 326                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 327
 328         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 329                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 330                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 331
 332         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 333                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 334                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 335                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
 336
 337         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 338                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 339                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 340 }
 341
 342 /**
 343  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
 344  * @xfer:       Select if the input shall be enabled or disabled
 345  *
 346  * This function enables or disables the 4P2 input into the DC-DC converter.
 347  */
 348 static void mxs_enable_4p2_dcdc_input(int xfer)
 349 {
 350         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 351         uint32_t prev_5v_brnout, prev_5v_droop;
 352
 353         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 354                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 355         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 356                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 357
 358         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 359         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 360                 &power_regs->hw_power_reset);
 361
 362         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 363
 364         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 365                         POWER_5VCTRL_ENABLE_DCDC)) {
 366                 return;
 367         }
 368
 369         /*
 370          * Recording orignal values that will be modified temporarlily
 371          * to handle a chip bug. See chip errata for CQ ENGR00115837
 372          */
 373         tmp = readl(&power_regs->hw_power_5vctrl);
 374         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 375         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 376
 377         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 378
 379         /*
 380          * Disable mechanisms that get erroneously tripped by when setting
 381          * the DCDC4P2 EN_DCDC
 382          */
 383         clrbits_le32(&power_regs->hw_power_5vctrl,
 384                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 385                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 386
 387         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 388
 389         if (xfer) {
 390                 setbits_le32(&power_regs->hw_power_5vctrl,
 391                                 POWER_5VCTRL_DCDC_XFER);
 392                 early_delay(20);
 393                 clrbits_le32(&power_regs->hw_power_5vctrl,
 394                                 POWER_5VCTRL_DCDC_XFER);
 395
 396                 setbits_le32(&power_regs->hw_power_5vctrl,
 397                                 POWER_5VCTRL_ENABLE_DCDC);
 398         } else {
 399                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 400                                 POWER_DCDC4P2_ENABLE_DCDC);
 401         }
 402
 403         early_delay(25);
 404
 405         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 406                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 407
 408         if (vbus_5vdetect)
 409                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 410
 411         if (!pwd_bo)
 412                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 413
 414         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 415                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 416                         &power_regs->hw_power_ctrl_clr);
 417
 418         if (prev_5v_brnout) {
 419                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 420                         &power_regs->hw_power_5vctrl_set);
 421                 writel(POWER_RESET_UNLOCK_KEY,
 422                         &power_regs->hw_power_reset);
 423         } else {
 424                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 425                         &power_regs->hw_power_5vctrl_clr);
 426                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 427                         &power_regs->hw_power_reset);
 428         }
 429
 430         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 431                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 432                         &power_regs->hw_power_ctrl_clr);
 433
 434         if (prev_5v_droop)
 435                 clrbits_le32(&power_regs->hw_power_ctrl,
 436                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 437         else
 438                 setbits_le32(&power_regs->hw_power_ctrl,
 439                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 440 }
 441
 442 /**
 443  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
 444  *
 445  * This function enables the 4P2 regulator and switches the DC-DC converter
 446  * to use the 4P2 input.
 447  */
 448 static void mxs_power_init_4p2_regulator(void)
 449 {
 450         uint32_t tmp, tmp2;
 451
 452         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 453
 454         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 455
 456         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 457                 &power_regs->hw_power_5vctrl_clr);
 458         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 459
 460         /* Power up the 4p2 rail and logic/control */
 461         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 462                 &power_regs->hw_power_5vctrl_clr);
 463
 464         /*
 465          * Start charging up the 4p2 capacitor. We ramp of this charge
 466          * gradually to avoid large inrush current from the 5V cable which can
 467          * cause transients/problems
 468          */
 469         mxs_enable_4p2_dcdc_input(0);
 470
 471         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 472                 /*
 473                  * If we arrived here, we were unable to recover from mx23 chip
 474                  * errata 5837. 4P2 is disabled and sufficient battery power is
 475                  * not present. Exiting to not enable DCDC power during 5V
 476                  * connected state.
 477                  */
 478                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 479                         POWER_DCDC4P2_ENABLE_DCDC);
 480                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 481                         &power_regs->hw_power_5vctrl_set);
 482                 hang();
 483         }
 484
 485         /*
 486          * Here we set the 4p2 brownout level to something very close to 4.2V.
 487          * We then check the brownout status. If the brownout status is false,
 488          * the voltage is already close to the target voltage of 4.2V so we
 489          * can go ahead and set the 4P2 current limit to our max target limit.
 490          * If the brownout status is true, we need to ramp us the current limit
 491          * so that we don't cause large inrush current issues. We step up the
 492          * current limit until the brownout status is false or until we've
 493          * reached our maximum defined 4p2 current limit.
 494          */
 495         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 496                         POWER_DCDC4P2_BO_MASK,
 497                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 498
 499         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 500                 setbits_le32(&power_regs->hw_power_5vctrl,
 501                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 502         } else {
 503                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 504                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 505                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 506                 while (tmp < 0x3f) {
 507                         if (!(readl(&power_regs->hw_power_sts) &
 508                                         POWER_STS_DCDC_4P2_BO)) {
 509                                 tmp = readl(&power_regs->hw_power_5vctrl);
 510                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 511                                 early_delay(100);
 512                                 writel(tmp, &power_regs->hw_power_5vctrl);
 513                                 break;
 514                         } else {
 515                                 tmp++;
 516                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 517                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 518                                 tmp2 |= tmp <<
 519                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 520                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 521                                 early_delay(100);
 522                         }
 523                 }
 524         }
 525
 526         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 527         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 528 }
 529
 530 /**
 531  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
 532  *
 533  * This function configures the DC-DC converter to be supplied from the 4P2
 534  * linear regulator.
 535  */
 536 static void mxs_power_init_dcdc_4p2_source(void)
 537 {
 538         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 539                 POWER_DCDC4P2_ENABLE_DCDC)) {
 540                 hang();
 541         }
 542
 543         mxs_enable_4p2_dcdc_input(1);
 544
 545         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 546                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 547                         POWER_DCDC4P2_ENABLE_DCDC);
 548                 writel(POWER_5VCTRL_ENABLE_DCDC,
 549                         &power_regs->hw_power_5vctrl_clr);
 550                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 551                         &power_regs->hw_power_5vctrl_set);
 552         }
 553 }
 554
 555 /**
 556  * mxs_power_enable_4p2() - Power up the 4P2 regulator
 557  *
 558  * This function drives the process of powering up the 4P2 linear regulator
 559  * and switching the DC-DC converter input over to the 4P2 linear regulator.
 560  */
 561 static void mxs_power_enable_4p2(void)
 562 {
 563         uint32_t vdddctrl, vddactrl, vddioctrl;
 564         uint32_t tmp;
 565
 566         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 567         vddactrl = readl(&power_regs->hw_power_vddactrl);
 568         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 569
 570         setbits_le32(&power_regs->hw_power_vdddctrl,
 571                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 572                 POWER_VDDDCTRL_PWDN_BRNOUT);
 573
 574         setbits_le32(&power_regs->hw_power_vddactrl,
 575                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 576                 POWER_VDDACTRL_PWDN_BRNOUT);
 577
 578         setbits_le32(&power_regs->hw_power_vddioctrl,
 579                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 580
 581         mxs_power_init_4p2_params();
 582         mxs_power_init_4p2_regulator();
 583
 584         /* Shutdown battery (none present) */
 585         if (!mxs_is_batt_ready()) {
 586                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 587                                 POWER_DCDC4P2_BO_MASK);
 588                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
 589                                 &power_regs->hw_power_ctrl_clr);
 590                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 591                                 &power_regs->hw_power_ctrl_clr);
 592         }
 593
 594         mxs_power_init_dcdc_4p2_source();
 595
 596         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 597         early_delay(20);
 598         writel(vddactrl, &power_regs->hw_power_vddactrl);
 599         early_delay(20);
 600         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 601
 602         /*
 603          * Check if FET is enabled on either powerout and if so,
 604          * disable load.
 605          */
 606         tmp = 0;
 607         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 608                         POWER_VDDDCTRL_DISABLE_FET);
 609         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 610                         POWER_VDDACTRL_DISABLE_FET);
 611         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 612                         POWER_VDDIOCTRL_DISABLE_FET);
 613         if (tmp)
 614                 writel(POWER_CHARGE_ENABLE_LOAD,
 615                         &power_regs->hw_power_charge_clr);
 616 }
 617
 618 /**
 619  * mxs_boot_valid_5v() - Boot from 5V supply
 620  *
 621  * This function configures the power block to boot from valid 5V input.
 622  * This is called only if the 5V is reliable and can properly supply the
 623  * CPU. This function proceeds to configure the 4P2 converter to be supplied
 624  * from the 5V input.
 625  */
 626 static void mxs_boot_valid_5v(void)
 627 {
 628         /*
 629          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 630          * disconnect event. FIXME
 631          */
 632         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 633                 &power_regs->hw_power_5vctrl_set);
 634
 635         /* Configure polarity to check for 5V disconnection. */
 636         writel(POWER_CTRL_POLARITY_VBUSVALID |
 637                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 638                 &power_regs->hw_power_ctrl_clr);
 639
 640         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 641                 &power_regs->hw_power_ctrl_clr);
 642
 643         mxs_power_enable_4p2();
 644 }
 645
 646 /**
 647  * mxs_powerdown() - Shut down the system
 648  *
 649  * This function powers down the CPU completely.
 650  */
 651 static void mxs_powerdown(void)
 652 {
 653         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 654         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 655                 &power_regs->hw_power_reset);
 656 }
 657
 658 /**
 659  * mxs_batt_boot() - Configure the power block to boot from battery input
 660  *
 661  * This function configures the power block to boot from the battery voltage
 662  * supply.
 663  */
 664 static void mxs_batt_boot(void)
 665 {
 666         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 667         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
 668
 669         clrbits_le32(&power_regs->hw_power_dcdc4p2,
 670                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
 671         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
 672
 673         /* 5V to battery handoff. */
 674         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 675         early_delay(30);
 676         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 677
 678         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 679
 680         clrsetbits_le32(&power_regs->hw_power_minpwr,
 681                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 682
 683         mxs_power_set_linreg();
 684
 685         clrbits_le32(&power_regs->hw_power_vdddctrl,
 686                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
 687
 688         clrbits_le32(&power_regs->hw_power_vddactrl,
 689                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
 690
 691         clrbits_le32(&power_regs->hw_power_vddioctrl,
 692                 POWER_VDDIOCTRL_DISABLE_FET);
 693
 694         setbits_le32(&power_regs->hw_power_5vctrl,
 695                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 696
 697         setbits_le32(&power_regs->hw_power_5vctrl,
 698                 POWER_5VCTRL_ENABLE_DCDC);
 699
 700         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 701                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 702                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 703
 704         mxs_power_enable_4p2();
 705 }
 706
 707 /**
 708  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
 709  *
 710  * This function tests if the 5V input can reliably supply the system. If it
 711  * can, then proceed to configuring the system to boot from 5V source, otherwise
 712  * try booting from battery supply. If we can not boot from battery supply
 713  * either, shut down the system.
 714  */
 715 static void mxs_handle_5v_conflict(void)
 716 {
 717         uint32_t tmp;
 718
 719         setbits_le32(&power_regs->hw_power_vddioctrl,
 720                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 721
 722         for (;;) {
 723                 tmp = readl(&power_regs->hw_power_sts);
 724
 725                 if (tmp & POWER_STS_VDDIO_BO) {
 726                         /*
 727                          * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
 728                          * unreliable
 729                          */
 730                         mxs_powerdown();
 731                         break;
 732                 }
 733
 734                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 735                         mxs_boot_valid_5v();
 736                         break;
 737                 } else {
 738                         mxs_powerdown();
 739                         break;
 740                 }
 741
 742                 if (tmp & POWER_STS_PSWITCH_MASK) {
 743                         mxs_batt_boot();
 744                         break;
 745                 }
 746         }
 747 }
 748
 749 /**
 750  * mxs_5v_boot() - Configure the power block to boot from 5V input
 751  *
 752  * This function handles configuration of the power block when supplied by
 753  * a 5V input.
 754  */
 755 static void mxs_5v_boot(void)
 756 {
 757         /*
 758          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 759          * but their implementation always returns 1 so we omit it here.
 760          */
 761         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 762                 mxs_boot_valid_5v();
 763                 return;
 764         }
 765
 766         early_delay(1000);
 767         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 768                 mxs_boot_valid_5v();
 769                 return;
 770         }
 771
 772         mxs_handle_5v_conflict();
 773 }
 774
 775 /**
 776  * mxs_init_batt_bo() - Configure battery brownout threshold
 777  *
 778  * This function configures the battery input brownout threshold. The value
 779  * at which the battery brownout happens is configured to 3.0V in the code.
 780  */
 781 static void mxs_init_batt_bo(void)
 782 {
 783         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 784
 785         setbits_le32(&power_regs->hw_power_5vctrl,
 786                 POWER_5VCTRL_PWDN_5VBRNOUT |
 787                 POWER_5VCTRL_ENABLE_DCDC |
 788                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
 789                 POWER_5VCTRL_PWDN_5VBRNOUT |
 790                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 791
 792         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 793
 794         clrbits_le32(&power_regs->hw_power_vdddctrl,
 795                 POWER_VDDDCTRL_DISABLE_FET |
 796                 POWER_VDDDCTRL_ENABLE_LINREG |
 797                 POWER_VDDDCTRL_DISABLE_STEPPING);
 798
 799         clrbits_le32(&power_regs->hw_power_vddactrl,
 800                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 801                 POWER_VDDACTRL_DISABLE_STEPPING);
 802
 803         clrbits_le32(&power_regs->hw_power_vddioctrl,
 804                 POWER_VDDIOCTRL_DISABLE_FET |
 805                 POWER_VDDIOCTRL_DISABLE_STEPPING);
 806
 807         /* Stop 5V detection */
 808         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
 809                 &power_regs->hw_power_5vctrl_clr);
 810 }
 811
 812 static void mxs_init_batt_bo(void)
 813 {
 814         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 815                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 816                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 817
 818         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 819         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 820 }
 821
 822 /**
 823  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
 824  *
 825  * This function turns off the VDDD linear regulator and therefore makes
 826  * the VDDD rail be supplied only by the DC-DC converter.
 827  */
 828 static void mxs_switch_vddd_to_dcdc_source(void)
 829 {
 830         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 831                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 832                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 833
 834         clrbits_le32(&power_regs->hw_power_vdddctrl,
 835                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 836                 POWER_VDDDCTRL_DISABLE_STEPPING);
 837 }
 838
 839 /**
 840  * mxs_power_configure_power_source() - Configure power block source
 841  *
 842  * This function is the core of the power configuration logic. The function
 843  * selects the power block input source and configures the whole power block
 844  * accordingly. After the configuration is complete and the system is stable
 845  * again, the function switches the CPU clock source back to PLL. Finally,
 846  * the function switches the voltage rails to DC-DC converter.
 847  */
 848 static void mxs_power_configure_power_source(void)
 849 {
 850         struct mxs_lradc_regs *lradc_regs =
 851                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 852
 853         mxs_src_power_init();
 854
 855         if (!fixed_batt_supply) {
 856                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 857                         if (mxs_is_batt_ready()) {
 858                                 /* 5V source detected, good battery detected. */
 859                                 mxs_batt_boot();
 860                         } else {
 861                                 if (!mxs_is_batt_good()) {
 862                                         /* 5V source detected, bad battery detected. */
 863                                         writel(LRADC_CONVERSION_AUTOMATIC,
 864                                                 &lradc_regs->hw_lradc_conversion_clr);
 865                                         clrbits_le32(&power_regs->hw_power_battmonitor,
 866                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
 867                                 }
 868                                 mxs_5v_boot();
 869                         }
 870                 } else {
 871                         /* 5V not detected, booting from battery. */
 872                         mxs_batt_boot();
 873                 }
 874         } else {
 875                 mxs_fixed_batt_boot();
 876         }
 877
 878         mxs_power_clock2pll();
 879
 880         mxs_init_batt_bo();
 881
 882         mxs_switch_vddd_to_dcdc_source();
 883
 884 #ifdef CONFIG_MX23
 885         /* Fire up the VDDMEM LinReg now that we're all set. */
 886         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
 887                 &power_regs->hw_power_vddmemctrl);
 888 #endif
 889 }
 890
 891 /**
 892  * mxs_enable_output_rail_protection() - Enable power rail protection
 893  *
 894  * This function enables overload protection on the power rails. This is
 895  * triggered if the power rails' voltage drops rapidly due to overload and
 896  * in such case, the supply to the powerrail is cut-off, protecting the
 897  * CPU from damage. Note that under such condition, the system will likely
 898  * crash or misbehave.
 899  */
 900 static void mxs_enable_output_rail_protection(void)
 901 {
 902         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 903                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 904
 905         setbits_le32(&power_regs->hw_power_vdddctrl,
 906                         POWER_VDDDCTRL_PWDN_BRNOUT);
 907
 908         setbits_le32(&power_regs->hw_power_vddactrl,
 909                         POWER_VDDACTRL_PWDN_BRNOUT);
 910
 911         setbits_le32(&power_regs->hw_power_vddioctrl,
 912                         POWER_VDDIOCTRL_PWDN_BRNOUT);
 913 }
 914
 915 /**
 916  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
 917  *
 918  * This function tests if the VDDIO rail is supplied by linear regulator
 919  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
 920  * returns 0 if powered by the DC-DC converter.
 921  */
 922 static int mxs_get_vddio_power_source_off(void)
 923 {
 924         uint32_t tmp;
 925
 926         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
 927                 !(readl(&power_regs->hw_power_5vctrl) &
 928                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
 929
 930                 tmp = readl(&power_regs->hw_power_vddioctrl);
 931                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
 932                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 933                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 934                                 return 1;
 935                         }
 936                 }
 937
 938                 if (!(readl(&power_regs->hw_power_5vctrl) &
 939                         POWER_5VCTRL_ENABLE_DCDC)) {
 940                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 941                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 942                                 return 1;
 943                         }
 944                 }
 945         }
 946
 947         return 0;
 948 }
 949
 950 /**
 951  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
 952  *
 953  * This function tests if the VDDD rail is supplied by linear regulator
 954  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
 955  * returns 0 if powered by the DC-DC converter.
 956  */
 957 static int mxs_get_vddd_power_source_off(void)
 958 {
 959         uint32_t tmp;
 960
 961         tmp = readl(&power_regs->hw_power_vdddctrl);
 962         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
 963                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 964                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 965                         return 1;
 966                 }
 967         }
 968
 969         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 970                 if (!(readl(&power_regs->hw_power_5vctrl) &
 971                         POWER_5VCTRL_ENABLE_DCDC)) {
 972                         return 1;
 973                 }
 974         }
 975
 976         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
 977                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 978                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
 979                         return 1;
 980                 }
 981         }
 982
 983         return 0;
 984 }
 985
 986 static int mxs_get_vdda_power_source_off(void)
 987 {
 988         uint32_t tmp;
 989
 990         tmp = readl(&power_regs->hw_power_vddactrl);
 991         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
 992                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 993                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
 994                         return 1;
 995                 }
 996         }
 997
 998         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 999                 if (!(readl(&power_regs->hw_power_5vctrl) &
1000                         POWER_5VCTRL_ENABLE_DCDC)) {
1001                         return 1;
1002                 }
1003         }
1004
1005         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1006                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1007                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1008                         return 1;
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 struct mxs_vddx_cfg {
1016         uint32_t                *reg;
1017         uint8_t                 step_mV;
1018         uint16_t                lowest_mV;
1019         uint16_t                highest_mV;
1020         int                     (*powered_by_linreg)(void);
1021         uint32_t                trg_mask;
1022         uint32_t                bo_irq;
1023         uint32_t                bo_enirq;
1024         uint32_t                bo_offset_mask;
1025         uint32_t                bo_offset_offset;
1026 };
1027
1028 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1029
1030 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1031         .reg                    = POWER_REG(hw_power_vddioctrl),
1032 #if defined(CONFIG_MX23)
1033         .step_mV                = 25,
1034 #else
1035         .step_mV                = 50,
1036 #endif
1037         .lowest_mV              = 2800,
1038         .highest_mV             = 3600,
1039         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1040         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1041         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1042         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1043         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1044         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1045 };
1046
1047 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1048         .reg                    = POWER_REG(hw_power_vdddctrl),
1049         .step_mV                = 25,
1050         .lowest_mV              = 800,
1051         .highest_mV             = 1575,
1052         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1053         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1054         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1055         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1056         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1057         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1058 };
1059
1060 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1061         .reg                    = POWER_REG(hw_power_vddactrl),
1062         .step_mV                = 50,
1063         .lowest_mV              = 2800,
1064         .highest_mV             = 3600,
1065         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1066         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1067         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1068         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1069         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1070         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1071 };
1072
1073 #ifdef CONFIG_MX23
1074 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1075         .reg                    = POWER_REG(hw_power_vddmemctrl),
1076         .step_mV                = 50,
1077         .lowest_mV              = 1500,
1078         .highest_mV             = 1700,
1079         .powered_by_linreg      = NULL,
1080         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1081         .bo_irq                 = 0,
1082         .bo_enirq               = 0,
1083         .bo_offset_mask         = 0,
1084         .bo_offset_offset       = 0,
1085 };
1086 #endif
1087
1088 /**
1089  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1090  * @cfg:                Configuration data of the DC-DC converter rail
1091  * @new_target:         New target voltage of the DC-DC converter rail
1092  * @new_brownout:       New brownout trigger voltage
1093  *
1094  * This function configures the output voltage on the DC-DC converter rail.
1095  * The rail is selected by the @cfg argument. The new voltage target is
1096  * selected by the @new_target and the voltage is specified in mV. The
1097  * new brownout value is selected by the @new_brownout argument and the
1098  * value is also in mV.
1099  */
1100 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1101                                 uint32_t new_target, uint32_t new_brownout)
1102 {
1103         uint32_t cur_target, diff, bo_int = 0;
1104         int powered_by_linreg = 0;
1105         int adjust_up;
1106
1107         if (new_target < cfg->lowest_mV)
1108                 new_target = cfg->lowest_mV;
1109         if (new_target > cfg->highest_mV)
1110                 new_target = cfg->highest_mV;
1111
1112         new_brownout = DIV_ROUND_CLOSEST(new_target - new_brownout,
1113                                          cfg->step_mV);
1114
1115         cur_target = readl(cfg->reg);
1116         cur_target &= cfg->trg_mask;
1117         cur_target *= cfg->step_mV;
1118         cur_target += cfg->lowest_mV;
1119
1120         adjust_up = new_target > cur_target;
1121         if (cfg->powered_by_linreg)
1122                 powered_by_linreg = cfg->powered_by_linreg();
1123
1124         if (adjust_up && cfg->bo_irq) {
1125                 if (powered_by_linreg) {
1126                         bo_int = readl(cfg->reg);
1127                         clrbits_le32(cfg->reg, cfg->bo_enirq);
1128                 }
1129                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1130         }
1131
1132         do {
1133                 if (abs(new_target - cur_target) > 100) {
1134                         if (adjust_up)
1135                                 diff = cur_target + 100;
1136                         else
1137                                 diff = cur_target - 100;
1138                 } else {
1139                         diff = new_target;
1140                 }
1141
1142                 diff -= cfg->lowest_mV;
1143                 diff /= cfg->step_mV;
1144
1145                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1146
1147                 if (powered_by_linreg ||
1148                         (readl(&power_regs->hw_power_sts) &
1149                                 POWER_STS_VDD5V_GT_VDDIO)) {
1150                         early_delay(500);
1151                 } else {
1152                         while (!(readl(&power_regs->hw_power_sts) &
1153                                         POWER_STS_DC_OK)) {
1154
1155                         }
1156                 }
1157
1158                 cur_target = readl(cfg->reg);
1159                 cur_target &= cfg->trg_mask;
1160                 cur_target *= cfg->step_mV;
1161                 cur_target += cfg->lowest_mV;
1162         } while (new_target > cur_target);
1163
1164         if (cfg->bo_irq) {
1165                 if (adjust_up && powered_by_linreg) {
1166                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1167                         if (bo_int & cfg->bo_enirq)
1168                                 setbits_le32(cfg->reg, cfg->bo_enirq);
1169                 }
1170
1171                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1172                                 new_brownout << cfg->bo_offset_offset);
1173         }
1174 }
1175
1176 /**
1177  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1178  *
1179  * This function starts and configures the LRADC block. This allows the
1180  * power initialization code to measure battery voltage and based on this
1181  * knowledge, decide whether to boot at all, boot from battery or boot
1182  * from 5V input.
1183  */
1184 static void mxs_setup_batt_detect(void)
1185 {
1186         mxs_lradc_init();
1187         mxs_lradc_enable_batt_measurement();
1188         early_delay(10);
1189 }
1190
1191 /**
1192  * mxs_ungate_power() - Ungate the POWER block
1193  *
1194  * This function ungates clock to the power block. In case the power block
1195  * was still gated at this point, it will not be possible to configure the
1196  * block and therefore the power initialization would fail. This function
1197  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1198  */
1199 static void mxs_ungate_power(void)
1200 {
1201 #ifdef CONFIG_MX23
1202         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1203 #endif
1204 }
1205
1206 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1207 #define auto_restart 1
1208 #else
1209 #define auto_restart 0
1210 #endif
1211
1212 /**
1213  * mxs_power_init() - The power block init main function
1214  *
1215  * This function calls all the power block initialization functions in
1216  * proper sequence to start the power block.
1217  */
1218 void mxs_power_init(void)
1219 {
1220         mxs_ungate_power();
1221
1222         mxs_power_clock2xtal();
1223         if (mxs_power_set_auto_restart(auto_restart)) {
1224                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1225         }
1226         mxs_power_set_linreg();
1227
1228         if (!fixed_batt_supply) {
1229                 mxs_power_setup_5v_detect();
1230                 mxs_setup_batt_detect();
1231         }
1232
1233         mxs_power_configure_power_source();
1234         mxs_enable_output_rail_protection();
1235
1236         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1237         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1238         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1239 #ifdef CONFIG_MX23
1240         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1241
1242         setbits_le32(&power_regs->hw_power_vddmemctrl,
1243                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1244         early_delay(500);
1245         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1246                 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1247 #else
1248         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1249                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1250 #endif
1251         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1252                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1253                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1254                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1255         if (!fixed_batt_supply)
1256                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1257                         &power_regs->hw_power_5vctrl_set);
1258 }
1259
1260 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1261 /**
1262  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1263  *
1264  * This function waits until the power-switch was pressed to start booting
1265  * the board.
1266  */
1267 void mxs_power_wait_pswitch(void)
1268 {
1269         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1270                 ;
1271 }
1272 #endif