arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

   1 /*
   2  * Freescale i.MX28 Boot PMIC init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <config.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30
  31 #include "mxs_init.h"
  32
  33 #ifdef CONFIG_SYS_SPL_VDDD_VAL
  34 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
  35 #else
  36 #define VDDD_VAL        1350
  37 #endif
  38 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
  39 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
  40 #else
  41 #define VDDIO_VAL       3300
  42 #endif
  43 #ifdef CONFIG_SYS_SPL_VDDA_VAL
  44 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
  45 #else
  46 #define VDDA_VAL        1800
  47 #endif
  48 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
  49 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
  50 #else
  51 #define VDDMEM_VAL      1500
  52 #endif
  53
  54 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
  55 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
  56 #else
  57 #define VDDD_BO_VAL     150
  58 #endif
  59 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
  60 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
  61 #else
  62 #define VDDIO_BO_VAL    150
  63 #endif
  64 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
  65 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
  66 #else
  67 #define VDDA_BO_VAL     175
  68 #endif
  69 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
  70 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
  71 #else
  72 #define VDDMEM_BO_VAL   25
  73 #endif
  74
  75 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
  76 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
  77 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
  78 #endif
  79 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
  80 #else
  81 /* Brownout default at 3V */
  82 #define BATT_BO_VAL     ((3000 - 2400) / 40)
  83 #endif
  84
  85 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
  86 static const int fixed_batt_supply = 1;
  87 #else
  88 static const int fixed_batt_supply;
  89 #endif
  90
  91 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
  92
  93 static void mxs_power_clock2xtal(void)
  94 {
  95         struct mxs_clkctrl_regs *clkctrl_regs =
  96                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  97
  98         /* Set XTAL as CPU reference clock */
  99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
 101 }
 102
 103 static void mxs_power_clock2pll(void)
 104 {
 105         struct mxs_clkctrl_regs *clkctrl_regs =
 106                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 107
 108         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
 109                         CLKCTRL_PLL0CTRL0_POWER);
 110         early_delay(100);
 111         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
 112                         CLKCTRL_CLKSEQ_BYPASS_CPU);
 113 }
 114
 115 static void mxs_power_clear_auto_restart(void)
 116 {
 117         struct mxs_rtc_regs *rtc_regs =
 118                 (struct mxs_rtc_regs *)MXS_RTC_BASE;
 119
 120         writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
 121         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
 122                 ;
 123
 124         writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
 125         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
 126                 ;
 127
 128         /*
 129          * Due to the hardware design bug of mx28 EVK-A
 130          * we need to set the AUTO_RESTART bit.
 131          */
 132         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 133                 return;
 134
 135         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 136                 ;
 137
 138         setbits_le32(&rtc_regs->hw_rtc_persistent0,
 139                         RTC_PERSISTENT0_AUTO_RESTART);
 140         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
 141         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
 142         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 143                 ;
 144         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
 145                 ;
 146 }
 147
 148 static void mxs_power_set_linreg(void)
 149 {
 150         /* Set linear regulator 25mV below switching converter */
 151         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 152                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 153                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 154
 155         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 156                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 157                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 158
 159         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 160                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 161                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 162 }
 163
 164 static int mxs_get_batt_volt(void)
 165 {
 166         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 167
 168         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 169         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 170         volt *= 8;
 171         return volt;
 172 }
 173
 174 static int mxs_is_batt_ready(void)
 175 {
 176         return (mxs_get_batt_volt() >= 3600);
 177 }
 178
 179 static int mxs_is_batt_good(void)
 180 {
 181         uint32_t volt = mxs_get_batt_volt();
 182
 183         if ((volt >= 2400) && (volt <= 4300))
 184                 return 1;
 185
 186         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 187                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 188                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 189         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 190                 &power_regs->hw_power_5vctrl_clr);
 191
 192         clrsetbits_le32(&power_regs->hw_power_charge,
 193                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 194                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 195
 196         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 197         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 198                 &power_regs->hw_power_5vctrl_clr);
 199
 200         early_delay(500000);
 201
 202         volt = mxs_get_batt_volt();
 203
 204         if (volt >= 3500)
 205                 return 0;
 206
 207         if (volt >= 2400)
 208                 return 1;
 209
 210         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 211                 &power_regs->hw_power_charge_clr);
 212         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 213
 214         return 0;
 215 }
 216
 217 static void mxs_power_setup_5v_detect(void)
 218 {
 219         /* Start 5V detection */
 220         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 221                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 222                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 223                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 224 }
 225
 226 static void mxs_src_power_init(void)
 227 {
 228         /* Improve efficieny and reduce transient ripple */
 229         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 230                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 231
 232         clrsetbits_le32(&power_regs->hw_power_dclimits,
 233                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 234                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 235
 236         if (!fixed_batt_supply) {
 237                 /* FIXME: This requires the LRADC to be set up! */
 238                 setbits_le32(&power_regs->hw_power_battmonitor,
 239                         POWER_BATTMONITOR_EN_BATADJ);
 240         } else {
 241                 clrbits_le32(&power_regs->hw_power_battmonitor,
 242                         POWER_BATTMONITOR_EN_BATADJ);
 243         }
 244
 245         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 246         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 247                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 248                         POWER_LOOPCTRL_RCSCALE_THRESH |
 249                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 250
 251         clrsetbits_le32(&power_regs->hw_power_minpwr,
 252                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 253
 254         if (!fixed_batt_supply) {
 255                 /* 5V to battery handoff ... FIXME */
 256                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 257                 early_delay(30);
 258                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 259         }
 260 }
 261
 262 static void mxs_power_init_4p2_params(void)
 263 {
 264         /* Setup 4P2 parameters */
 265         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 266                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 267                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 268
 269         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 270                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 271                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 272
 273         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 274                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 275                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 276                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
 277
 278         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 279                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 280                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 281 }
 282
 283 static void mxs_enable_4p2_dcdc_input(int xfer)
 284 {
 285         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 286         uint32_t prev_5v_brnout, prev_5v_droop;
 287
 288         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 289                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 290         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 291                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 292
 293         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 294         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 295                 &power_regs->hw_power_reset);
 296
 297         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 298
 299         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 300                         POWER_5VCTRL_ENABLE_DCDC)) {
 301                 return;
 302         }
 303
 304         /*
 305          * Recording orignal values that will be modified temporarlily
 306          * to handle a chip bug. See chip errata for CQ ENGR00115837
 307          */
 308         tmp = readl(&power_regs->hw_power_5vctrl);
 309         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 310         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 311
 312         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 313
 314         /*
 315          * Disable mechanisms that get erroneously tripped by when setting
 316          * the DCDC4P2 EN_DCDC
 317          */
 318         clrbits_le32(&power_regs->hw_power_5vctrl,
 319                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 320                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 321
 322         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 323
 324         if (xfer) {
 325                 setbits_le32(&power_regs->hw_power_5vctrl,
 326                                 POWER_5VCTRL_DCDC_XFER);
 327                 early_delay(20);
 328                 clrbits_le32(&power_regs->hw_power_5vctrl,
 329                                 POWER_5VCTRL_DCDC_XFER);
 330
 331                 setbits_le32(&power_regs->hw_power_5vctrl,
 332                                 POWER_5VCTRL_ENABLE_DCDC);
 333         } else {
 334                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 335                                 POWER_DCDC4P2_ENABLE_DCDC);
 336         }
 337
 338         early_delay(25);
 339
 340         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 341                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 342
 343         if (vbus_5vdetect)
 344                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 345
 346         if (!pwd_bo)
 347                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 348
 349         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 350                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 351                         &power_regs->hw_power_ctrl_clr);
 352
 353         if (prev_5v_brnout) {
 354                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 355                         &power_regs->hw_power_5vctrl_set);
 356                 writel(POWER_RESET_UNLOCK_KEY,
 357                         &power_regs->hw_power_reset);
 358         } else {
 359                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 360                         &power_regs->hw_power_5vctrl_clr);
 361                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 362                         &power_regs->hw_power_reset);
 363         }
 364
 365         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 366                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 367                         &power_regs->hw_power_ctrl_clr);
 368
 369         if (prev_5v_droop)
 370                 clrbits_le32(&power_regs->hw_power_ctrl,
 371                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 372         else
 373                 setbits_le32(&power_regs->hw_power_ctrl,
 374                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 375 }
 376
 377 static void mxs_power_init_4p2_regulator(void)
 378 {
 379         uint32_t tmp, tmp2;
 380
 381         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 382
 383         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 384
 385         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 386                 &power_regs->hw_power_5vctrl_clr);
 387         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 388
 389         /* Power up the 4p2 rail and logic/control */
 390         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 391                 &power_regs->hw_power_5vctrl_clr);
 392
 393         /*
 394          * Start charging up the 4p2 capacitor. We ramp of this charge
 395          * gradually to avoid large inrush current from the 5V cable which can
 396          * cause transients/problems
 397          */
 398         mxs_enable_4p2_dcdc_input(0);
 399
 400         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 401                 /*
 402                  * If we arrived here, we were unable to recover from mx23 chip
 403                  * errata 5837. 4P2 is disabled and sufficient battery power is
 404                  * not present. Exiting to not enable DCDC power during 5V
 405                  * connected state.
 406                  */
 407                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 408                         POWER_DCDC4P2_ENABLE_DCDC);
 409                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 410                         &power_regs->hw_power_5vctrl_set);
 411                 hang();
 412         }
 413
 414         /*
 415          * Here we set the 4p2 brownout level to something very close to 4.2V.
 416          * We then check the brownout status. If the brownout status is false,
 417          * the voltage is already close to the target voltage of 4.2V so we
 418          * can go ahead and set the 4P2 current limit to our max target limit.
 419          * If the brownout status is true, we need to ramp us the current limit
 420          * so that we don't cause large inrush current issues. We step up the
 421          * current limit until the brownout status is false or until we've
 422          * reached our maximum defined 4p2 current limit.
 423          */
 424         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 425                         POWER_DCDC4P2_BO_MASK,
 426                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 427
 428         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 429                 setbits_le32(&power_regs->hw_power_5vctrl,
 430                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 431         } else {
 432                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 433                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 434                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 435                 while (tmp < 0x3f) {
 436                         if (!(readl(&power_regs->hw_power_sts) &
 437                                         POWER_STS_DCDC_4P2_BO)) {
 438                                 tmp = readl(&power_regs->hw_power_5vctrl);
 439                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 440                                 early_delay(100);
 441                                 writel(tmp, &power_regs->hw_power_5vctrl);
 442                                 break;
 443                         } else {
 444                                 tmp++;
 445                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 446                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 447                                 tmp2 |= tmp <<
 448                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 449                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 450                                 early_delay(100);
 451                         }
 452                 }
 453         }
 454
 455         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 456         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 457 }
 458
 459 static void mxs_power_init_dcdc_4p2_source(void)
 460 {
 461         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 462                 POWER_DCDC4P2_ENABLE_DCDC)) {
 463                 hang();
 464         }
 465
 466         mxs_enable_4p2_dcdc_input(1);
 467
 468         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 469                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 470                         POWER_DCDC4P2_ENABLE_DCDC);
 471                 writel(POWER_5VCTRL_ENABLE_DCDC,
 472                         &power_regs->hw_power_5vctrl_clr);
 473                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 474                         &power_regs->hw_power_5vctrl_set);
 475         }
 476 }
 477
 478 static void mxs_power_enable_4p2(void)
 479 {
 480         uint32_t vdddctrl, vddactrl, vddioctrl;
 481         uint32_t tmp;
 482
 483         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 484         vddactrl = readl(&power_regs->hw_power_vddactrl);
 485         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 486
 487         setbits_le32(&power_regs->hw_power_vdddctrl,
 488                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 489                 POWER_VDDDCTRL_PWDN_BRNOUT);
 490
 491         setbits_le32(&power_regs->hw_power_vddactrl,
 492                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 493                 POWER_VDDACTRL_PWDN_BRNOUT);
 494
 495         setbits_le32(&power_regs->hw_power_vddioctrl,
 496                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 497
 498         mxs_power_init_4p2_params();
 499         mxs_power_init_4p2_regulator();
 500
 501         /* Shutdown battery (none present) */
 502         if (!mxs_is_batt_ready()) {
 503                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 504                                 POWER_DCDC4P2_BO_MASK);
 505                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
 506                                 &power_regs->hw_power_ctrl_clr);
 507                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 508                                 &power_regs->hw_power_ctrl_clr);
 509         }
 510
 511         mxs_power_init_dcdc_4p2_source();
 512
 513         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 514         early_delay(20);
 515         writel(vddactrl, &power_regs->hw_power_vddactrl);
 516         early_delay(20);
 517         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 518
 519         /*
 520          * Check if FET is enabled on either powerout and if so,
 521          * disable load.
 522          */
 523         tmp = 0;
 524         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 525                         POWER_VDDDCTRL_DISABLE_FET);
 526         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 527                         POWER_VDDACTRL_DISABLE_FET);
 528         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 529                         POWER_VDDIOCTRL_DISABLE_FET);
 530         if (tmp)
 531                 writel(POWER_CHARGE_ENABLE_LOAD,
 532                         &power_regs->hw_power_charge_clr);
 533 }
 534
 535 static void mxs_boot_valid_5v(void)
 536 {
 537         /*
 538          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 539          * disconnect event. FIXME
 540          */
 541         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 542                 &power_regs->hw_power_5vctrl_set);
 543
 544         /* Configure polarity to check for 5V disconnection. */
 545         writel(POWER_CTRL_POLARITY_VBUSVALID |
 546                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 547                 &power_regs->hw_power_ctrl_clr);
 548
 549         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 550                 &power_regs->hw_power_ctrl_clr);
 551
 552         mxs_power_enable_4p2();
 553 }
 554
 555 static void mxs_powerdown(void)
 556 {
 557         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 558         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 559                 &power_regs->hw_power_reset);
 560 }
 561
 562 static void mxs_batt_boot(void)
 563 {
 564         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 565         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
 566
 567         clrbits_le32(&power_regs->hw_power_dcdc4p2,
 568                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
 569         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
 570
 571         /* 5V to battery handoff. */
 572         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 573         early_delay(30);
 574         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 575
 576         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 577
 578         clrsetbits_le32(&power_regs->hw_power_minpwr,
 579                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 580
 581         mxs_power_set_linreg();
 582
 583         clrbits_le32(&power_regs->hw_power_vdddctrl,
 584                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
 585
 586         clrbits_le32(&power_regs->hw_power_vddactrl,
 587                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
 588
 589         clrbits_le32(&power_regs->hw_power_vddioctrl,
 590                 POWER_VDDIOCTRL_DISABLE_FET);
 591
 592         setbits_le32(&power_regs->hw_power_5vctrl,
 593                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 594
 595         setbits_le32(&power_regs->hw_power_5vctrl,
 596                 POWER_5VCTRL_ENABLE_DCDC);
 597
 598         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 599                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 600                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 601 }
 602
 603 static void mxs_handle_5v_conflict(void)
 604 {
 605         uint32_t tmp;
 606
 607         setbits_le32(&power_regs->hw_power_vddioctrl,
 608                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 609
 610         for (;;) {
 611                 tmp = readl(&power_regs->hw_power_sts);
 612
 613                 if (tmp & POWER_STS_VDDIO_BO) {
 614                         /*
 615                          * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
 616                          * unreliable
 617                          */
 618                         mxs_powerdown();
 619                         break;
 620                 }
 621
 622                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 623                         mxs_boot_valid_5v();
 624                         break;
 625                 } else {
 626                         mxs_powerdown();
 627                         break;
 628                 }
 629
 630                 if (tmp & POWER_STS_PSWITCH_MASK) {
 631                         mxs_batt_boot();
 632                         break;
 633                 }
 634         }
 635 }
 636
 637 static void mxs_5v_boot(void)
 638 {
 639         /*
 640          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 641          * but their implementation always returns 1 so we omit it here.
 642          */
 643         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 644                 mxs_boot_valid_5v();
 645                 return;
 646         }
 647
 648         early_delay(1000);
 649         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 650                 mxs_boot_valid_5v();
 651                 return;
 652         }
 653
 654         mxs_handle_5v_conflict();
 655 }
 656
 657 static void mxs_fixed_batt_boot(void)
 658 {
 659         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 660
 661         setbits_le32(&power_regs->hw_power_5vctrl,
 662                 POWER_5VCTRL_PWDN_5VBRNOUT |
 663                 POWER_5VCTRL_ENABLE_DCDC |
 664                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
 665                 POWER_5VCTRL_PWDN_5VBRNOUT |
 666                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 667
 668         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 669
 670         clrbits_le32(&power_regs->hw_power_vdddctrl,
 671                 POWER_VDDDCTRL_DISABLE_FET |
 672                 POWER_VDDDCTRL_ENABLE_LINREG |
 673                 POWER_VDDDCTRL_DISABLE_STEPPING);
 674
 675         clrbits_le32(&power_regs->hw_power_vddactrl,
 676                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 677                 POWER_VDDACTRL_DISABLE_STEPPING);
 678
 679         clrbits_le32(&power_regs->hw_power_vddioctrl,
 680                 POWER_VDDIOCTRL_DISABLE_FET |
 681                 POWER_VDDIOCTRL_DISABLE_STEPPING);
 682
 683         /* Stop 5V detection */
 684         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
 685                 &power_regs->hw_power_5vctrl_clr);
 686 }
 687
 688 static void mxs_init_batt_bo(void)
 689 {
 690         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 691                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 692                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 693
 694         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 695         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 696 }
 697
 698 static void mxs_switch_vddd_to_dcdc_source(void)
 699 {
 700         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 701                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 702                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 703
 704         clrbits_le32(&power_regs->hw_power_vdddctrl,
 705                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 706                 POWER_VDDDCTRL_DISABLE_STEPPING);
 707 }
 708
 709 static void mxs_power_configure_power_source(void)
 710 {
 711         struct mxs_lradc_regs *lradc_regs =
 712                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 713
 714         mxs_src_power_init();
 715
 716         if (!fixed_batt_supply) {
 717                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 718                         if (mxs_is_batt_ready()) {
 719                                 /* 5V source detected, good battery detected. */
 720                                 mxs_batt_boot();
 721                         } else {
 722                                 if (!mxs_is_batt_good()) {
 723                                         /* 5V source detected, bad battery detected. */
 724                                         writel(LRADC_CONVERSION_AUTOMATIC,
 725                                                 &lradc_regs->hw_lradc_conversion_clr);
 726                                         clrbits_le32(&power_regs->hw_power_battmonitor,
 727                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
 728                                 }
 729                                 mxs_5v_boot();
 730                         }
 731                 } else {
 732                         /* 5V not detected, booting from battery. */
 733                         mxs_batt_boot();
 734                 }
 735         } else {
 736                 mxs_fixed_batt_boot();
 737         }
 738
 739         mxs_power_clock2pll();
 740
 741         mxs_init_batt_bo();
 742
 743         mxs_switch_vddd_to_dcdc_source();
 744 }
 745
 746 static void mxs_enable_output_rail_protection(void)
 747 {
 748         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 749                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 750
 751         setbits_le32(&power_regs->hw_power_vdddctrl,
 752                         POWER_VDDDCTRL_PWDN_BRNOUT);
 753
 754         setbits_le32(&power_regs->hw_power_vddactrl,
 755                         POWER_VDDACTRL_PWDN_BRNOUT);
 756
 757         setbits_le32(&power_regs->hw_power_vddioctrl,
 758                         POWER_VDDIOCTRL_PWDN_BRNOUT);
 759 }
 760
 761 static int mxs_get_vddio_power_source_off(void)
 762 {
 763         uint32_t tmp;
 764
 765         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
 766                 !(readl(&power_regs->hw_power_5vctrl) &
 767                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
 768
 769                 tmp = readl(&power_regs->hw_power_vddioctrl);
 770                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
 771                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 772                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 773                                 return 1;
 774                         }
 775                 }
 776
 777                 if (!(readl(&power_regs->hw_power_5vctrl) &
 778                         POWER_5VCTRL_ENABLE_DCDC)) {
 779                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 780                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
 781                                 return 1;
 782                         }
 783                 }
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int mxs_get_vddd_power_source_off(void)
 790 {
 791         uint32_t tmp;
 792
 793         tmp = readl(&power_regs->hw_power_vdddctrl);
 794         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
 795                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 796                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 797                         return 1;
 798                 }
 799         }
 800
 801         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 802                 if (!(readl(&power_regs->hw_power_5vctrl) &
 803                         POWER_5VCTRL_ENABLE_DCDC)) {
 804                         return 1;
 805                 }
 806         }
 807
 808         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
 809                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 810                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
 811                         return 1;
 812                 }
 813         }
 814
 815         return 0;
 816 }
 817
 818 static int mxs_get_vdda_power_source_off(void)
 819 {
 820         uint32_t tmp;
 821
 822         tmp = readl(&power_regs->hw_power_vddactrl);
 823         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
 824                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 825                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
 826                         return 1;
 827                 }
 828         }
 829
 830         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 831                 if (!(readl(&power_regs->hw_power_5vctrl) &
 832                         POWER_5VCTRL_ENABLE_DCDC)) {
 833                         return 1;
 834                 }
 835         }
 836
 837         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
 838                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 839                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
 840                         return 1;
 841                 }
 842         }
 843
 844         return 0;
 845 }
 846
 847 struct mxs_vddx_cfg {
 848         uint32_t                *reg;
 849         uint8_t                 step_mV;
 850         uint16_t                lowest_mV;
 851         uint16_t                highest_mV;
 852         int                     (*powered_by_linreg)(void);
 853         uint32_t                trg_mask;
 854         uint32_t                bo_irq;
 855         uint32_t                bo_enirq;
 856         uint32_t                bo_offset_mask;
 857         uint32_t                bo_offset_offset;
 858 };
 859
 860 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
 861         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 862                                         hw_power_vddioctrl),
 863         .step_mV                = 50,
 864         .lowest_mV              = 2800,
 865         .highest_mV             = 3600,
 866         .powered_by_linreg      = mxs_get_vddio_power_source_off,
 867         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
 868         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
 869         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
 870         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
 871         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
 872 };
 873
 874 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
 875         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 876                                         hw_power_vdddctrl),
 877         .step_mV                = 25,
 878         .lowest_mV              = 800,
 879         .highest_mV             = 1575,
 880         .powered_by_linreg      = mxs_get_vddd_power_source_off,
 881         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
 882         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
 883         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
 884         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
 885         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
 886 };
 887
 888 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
 889         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 890                                         hw_power_vddactrl),
 891         .step_mV                = 50,
 892         .lowest_mV              = 2800,
 893         .highest_mV             = 3600,
 894         .powered_by_linreg      = mxs_get_vdda_power_source_off,
 895         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
 896         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
 897         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
 898         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
 899         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
 900 };
 901
 902 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
 903         .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
 904                                         hw_power_vddmemctrl),
 905         .step_mV                = 25,
 906         .lowest_mV              = 1100,
 907         .highest_mV             = 1750,
 908         .bo_offset_mask         = POWER_VDDMEMCTRL_BO_OFFSET_MASK,
 909         .bo_offset_offset       = POWER_VDDMEMCTRL_BO_OFFSET_OFFSET,
 910 };
 911
 912 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 913                                 uint32_t new_target, uint32_t new_brownout)
 914 {
 915         uint32_t cur_target, diff, bo_int = 0;
 916         int powered_by_linreg = 0;
 917         int adjust_up;
 918
 919         if (new_target < cfg->lowest_mV)
 920                 new_target = cfg->lowest_mV;
 921         if (new_target > cfg->highest_mV)
 922                 new_target = cfg->highest_mV;
 923
 924         new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
 925
 926         cur_target = readl(cfg->reg);
 927         cur_target &= cfg->trg_mask;
 928         cur_target *= cfg->step_mV;
 929         cur_target += cfg->lowest_mV;
 930
 931         adjust_up = new_target > cur_target;
 932         if (cfg->powered_by_linreg)
 933                 powered_by_linreg = cfg->powered_by_linreg();
 934
 935         if (adjust_up) {
 936                 if (powered_by_linreg) {
 937                         bo_int = readl(cfg->reg);
 938                         clrbits_le32(cfg->reg, cfg->bo_enirq);
 939                 }
 940                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
 941         }
 942
 943         do {
 944                 if (abs(new_target - cur_target) > 100) {
 945                         if (adjust_up)
 946                                 diff = cur_target + 100;
 947                         else
 948                                 diff = cur_target - 100;
 949                 } else {
 950                         diff = new_target;
 951                 }
 952
 953                 diff -= cfg->lowest_mV;
 954                 diff /= cfg->step_mV;
 955
 956                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
 957
 958                 if (powered_by_linreg ||
 959                         (readl(&power_regs->hw_power_sts) &
 960                                 POWER_STS_VDD5V_GT_VDDIO)) {
 961                         early_delay(500);
 962                 } else {
 963                         while (!(readl(&power_regs->hw_power_sts) &
 964                                         POWER_STS_DC_OK)) {
 965
 966                         }
 967                 }
 968
 969                 cur_target = readl(cfg->reg);
 970                 cur_target &= cfg->trg_mask;
 971                 cur_target *= cfg->step_mV;
 972                 cur_target += cfg->lowest_mV;
 973         } while (new_target > cur_target);
 974
 975         if (adjust_up && powered_by_linreg) {
 976                 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
 977                 if (bo_int & cfg->bo_enirq)
 978                         setbits_le32(cfg->reg, cfg->bo_enirq);
 979         }
 980
 981         clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
 982                         new_brownout << cfg->bo_offset_offset);
 983 }
 984
 985 static void mxs_setup_batt_detect(void)
 986 {
 987         mxs_lradc_init();
 988         mxs_lradc_enable_batt_measurement();
 989         early_delay(10);
 990 }
 991
 992 void mxs_power_init(void)
 993 {
 994         mxs_power_clock2xtal();
 995         mxs_power_clear_auto_restart();
 996         mxs_power_set_linreg();
 997
 998         if (!fixed_batt_supply) {
 999                 mxs_power_setup_5v_detect();
1000                 mxs_setup_batt_detect();
1001         }
1002
1003         mxs_power_configure_power_source();
1004         mxs_enable_output_rail_protection();
1005
1006         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1007         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1008         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1009 #if VDDMEM_VAL > 0
1010         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1011
1012         setbits_le32(&power_regs->hw_power_vddmemctrl,
1013                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1014         early_delay(500);
1015         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1016                 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1017 #else
1018         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1019                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1020 #endif
1021         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1022                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1023                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1024                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1025         if (!fixed_batt_supply)
1026                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1027                         &power_regs->hw_power_5vctrl_set);
1028 }
1029
1030 #ifdef  CONFIG_SPL_MX28_PSWITCH_WAIT
1031 void mxs_power_wait_pswitch(void)
1032 {
1033         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1034                 ;
1035 }
1036 #endif