3d26b8d1b37525c924f96d7dd8e1056be19baab6
[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2  * Freescale i.MX28 Boot PMIC init
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14
15 #include "mxs_init.h"
16
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
20 #else
21 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
23 #endif
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
26 #else
27 #define VDDD_VAL        1350
28 #endif
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
31 #else
32 #define VDDIO_VAL       3300
33 #endif
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
36 #else
37 #define VDDA_VAL        1800
38 #endif
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
41 #else
42 #define VDDMEM_VAL      1700
43 #endif
44
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
47 #else
48 #define VDDD_BO_VAL     150
49 #endif
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
52 #else
53 #define VDDIO_BO_VAL    150
54 #endif
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
57 #else
58 #define VDDA_BO_VAL     175
59 #endif
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
62 #else
63 #define VDDMEM_BO_VAL   25
64 #endif
65
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
69 #endif
70 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
71 #else
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL     ((3000 - 2400) / 40)
74 #endif
75
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
78 #else
79 static const int fixed_batt_supply;
80 #endif
81
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
83
84 /**
85  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
86  *
87  * This function switches the CPU core clock from PLL to 24MHz XTAL
88  * oscilator. This is necessary if the PLL is being reconfigured to
89  * prevent crash of the CPU core.
90  */
91 static void mxs_power_clock2xtal(void)
92 {
93         struct mxs_clkctrl_regs *clkctrl_regs =
94                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
95
96         debug("SPL: Switching CPU clock to 24MHz XTAL\n");
97
98         /* Set XTAL as CPU reference clock */
99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
101 }
102
103 /**
104  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
105  *
106  * This function switches the CPU core clock from 24MHz XTAL oscilator
107  * to PLL. This can only be called once the PLL has re-locked and once
108  * the PLL is stable after reconfiguration.
109  */
110 static void mxs_power_clock2pll(void)
111 {
112         struct mxs_clkctrl_regs *clkctrl_regs =
113                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
114
115         debug("SPL: Switching CPU core clock source to PLL\n");
116
117         /*
118          * TODO: Are we really? It looks like we turn on PLL0, but we then
119          * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120          * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121          * introduce some instability (causing the CPU core to hang). Maybe
122          * we aren't giving PLL0 enough time to stabilise?
123          */
124         writel(CLKCTRL_PLL0CTRL0_POWER,
125                 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
126         udelay(100);
127
128         /*
129          * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130          * wait on the PLL0 LOCK bit?
131          */
132         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
133                 &clkctrl_regs->hw_clkctrl_clkseq_clr);
134 }
135
136 static int mxs_power_wait_rtc_stat(u32 mask)
137 {
138         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
139         u32 val;
140         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
141
142         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
143                 udelay(1);
144                 if (timeout-- < 0)
145                         break;
146         }
147         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
148 }
149
150 /**
151  * mxs_power_set_auto_restart() - Set the auto-restart bit
152  *
153  * This function ungates the RTC block and sets the AUTO_RESTART
154  * bit to work around a design bug on MX28EVK Rev. A .
155  */
156 static int mxs_power_set_auto_restart(int on)
157 {
158         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
159
160         debug("SPL: Setting auto-restart bit\n");
161
162         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
163                 return 1;
164
165         /* Do nothing if flag already set */
166         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
167                 return 0;
168
169         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
171                 return 0;
172
173         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
174                 return 1;
175
176         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177                         !on * RTC_PERSISTENT0_AUTO_RESTART,
178                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
179         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
180                 return 1;
181
182         return 0;
183 }
184
185 /**
186  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
187  *
188  * This function configures the VDDIO, VDDA and VDDD linear regulators output
189  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190  * converter. This is the recommended setting for the case where we use both
191  * linear regulators and DC-DC converter to power the VDDIO rail.
192  */
193 static void mxs_power_set_linreg(void)
194 {
195         /* Set linear regulator 25mV below switching converter */
196         debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
200
201         debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202         clrsetbits_le32(&power_regs->hw_power_vddactrl,
203                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
204                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
205
206         debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
210 }
211
212 /**
213  * mxs_get_batt_volt() - Measure battery input voltage
214  *
215  * This function retrieves the battery input voltage and returns it.
216  */
217 static int mxs_get_batt_volt(void)
218 {
219         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
220
221         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
223         volt *= 8;
224
225         debug("SPL: Battery Voltage = %dmV\n", volt);
226         return volt;
227 }
228
229 /**
230  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
231  *
232  * This function checks if the battery input voltage is higher than 3.6V and
233  * therefore allows the system to successfully boot using this power source.
234  */
235 static int mxs_is_batt_ready(void)
236 {
237         return (mxs_get_batt_volt() >= 3600);
238 }
239
240 /**
241  * mxs_is_batt_good() - Test if battery is operational at all
242  *
243  * This function starts recharging the battery and tests if the input current
244  * provided by the 5V input recharging the battery is also sufficient to power
245  * the DC-DC converter.
246  */
247 static int mxs_is_batt_good(void)
248 {
249         uint32_t volt = mxs_get_batt_volt();
250
251         if ((volt >= 2400) && (volt <= 4300)) {
252                 debug("SPL: Battery is good\n");
253                 return 1;
254         }
255
256         clrsetbits_le32(&power_regs->hw_power_5vctrl,
257                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260                 &power_regs->hw_power_5vctrl_clr);
261
262         clrsetbits_le32(&power_regs->hw_power_charge,
263                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
265
266         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268                 &power_regs->hw_power_5vctrl_clr);
269
270         udelay(500000);
271
272         volt = mxs_get_batt_volt();
273
274         if (volt >= 3500) {
275                 debug("SPL: Battery Voltage too high\n");
276                 return 0;
277         }
278
279         if (volt >= 2400) {
280                 debug("SPL: Battery is good\n");
281                 return 1;
282         }
283
284         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285                 &power_regs->hw_power_charge_clr);
286         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
287
288         if (volt >= 3500) {
289                 return 0;
290         }
291         if (volt >= 2400) {
292                 return 1;
293         }
294         debug("SPL: Battery Voltage too low\n");
295         return 0;
296 }
297
298 /**
299  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
300  *
301  * This function enables the 5V detection comparator and sets the 5V valid
302  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303  * under high load, the voltage drop on the 5V input won't be so critical
304  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305  * converter and thus making the system crash.
306  */
307 static void mxs_power_setup_5v_detect(void)
308 {
309         /* Start 5V detection */
310         debug("SPL: Starting 5V input detection comparator\n");
311         clrsetbits_le32(&power_regs->hw_power_5vctrl,
312                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
315 }
316
317 /**
318  * mxs_src_power_init() - Preconfigure the power block
319  *
320  * This function configures reasonable values for the DC-DC control loop
321  * and battery monitor.
322  */
323 static void mxs_src_power_init(void)
324 {
325         debug("SPL: Pre-Configuring power block\n");
326
327         /* Improve efficieny and reduce transient ripple */
328         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
329                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
330
331         clrsetbits_le32(&power_regs->hw_power_dclimits,
332                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
333                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
334
335         if (!fixed_batt_supply) {
336                 /* FIXME: This requires the LRADC to be set up! */
337                 setbits_le32(&power_regs->hw_power_battmonitor,
338                         POWER_BATTMONITOR_EN_BATADJ);
339         } else {
340                 clrbits_le32(&power_regs->hw_power_battmonitor,
341                         POWER_BATTMONITOR_EN_BATADJ);
342         }
343
344         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
345         clrsetbits_le32(&power_regs->hw_power_loopctrl,
346                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
347                         POWER_LOOPCTRL_RCSCALE_THRESH |
348                         POWER_LOOPCTRL_EN_RCSCALE_8X);
349
350         clrsetbits_le32(&power_regs->hw_power_minpwr,
351                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
352
353         if (!fixed_batt_supply) {
354                 /* 5V to battery handoff ... FIXME */
355                 writel(POWER_5VCTRL_DCDC_XFER,
356                         &power_regs->hw_power_5vctrl_set);
357                 udelay(30);
358                 writel(POWER_5VCTRL_DCDC_XFER,
359                         &power_regs->hw_power_5vctrl_clr);
360         }
361 }
362
363 /**
364  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
365  *
366  * This function configures the necessary parameters for the 4P2 linear
367  * regulator to supply the DC-DC converter from 5V input.
368  */
369 static void mxs_power_init_4p2_params(void)
370 {
371         debug("SPL: Configuring common 4P2 regulator params\n");
372
373         /* Setup 4P2 parameters */
374         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
375                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
376                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
377
378         clrsetbits_le32(&power_regs->hw_power_5vctrl,
379                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
380                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
381
382         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
383                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
384                 DCDC4P2_DROPOUT_CONFIG);
385
386         clrsetbits_le32(&power_regs->hw_power_5vctrl,
387                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
388                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
389 }
390
391 /**
392  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
393  * @xfer:       Select if the input shall be enabled or disabled
394  *
395  * This function enables or disables the 4P2 input into the DC-DC converter.
396  */
397 static void mxs_enable_4p2_dcdc_input(int xfer)
398 {
399         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
400         uint32_t prev_5v_brnout, prev_5v_droop;
401
402         debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
403
404         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
405                         POWER_5VCTRL_ENABLE_DCDC)) {
406                 return;
407         }
408
409         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
410                                 POWER_5VCTRL_PWDN_5VBRNOUT;
411         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
412                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
413
414         writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr);
415         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
416                 &power_regs->hw_power_reset);
417
418         writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
419
420         /*
421          * Recording orignal values that will be modified temporarlily
422          * to handle a chip bug. See chip errata for CQ ENGR00115837
423          */
424         tmp = readl(&power_regs->hw_power_5vctrl);
425         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
426         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
427
428         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
429
430         /*
431          * Disable mechanisms that get erroneously tripped by when setting
432          * the DCDC4P2 EN_DCDC
433          */
434         writel(POWER_5VCTRL_VBUSVALID_5VDETECT |
435                 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
436                 &power_regs->hw_power_5vctrl);
437
438         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
439
440         if (xfer) {
441                 writel(POWER_5VCTRL_DCDC_XFER,
442                         &power_regs->hw_power_5vctrl);
443                 udelay(20);
444                 writel(POWER_5VCTRL_DCDC_XFER,
445                         &power_regs->hw_power_5vctrl_clr);
446
447                 writel(POWER_5VCTRL_ENABLE_DCDC,
448                         &power_regs->hw_power_5vctrl_set);
449         } else {
450                 writel(POWER_DCDC4P2_ENABLE_DCDC,
451                         &power_regs->hw_power_dcdc4p2);
452         }
453
454         udelay(25);
455
456         clrsetbits_le32(&power_regs->hw_power_5vctrl,
457                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
458
459         if (vbus_5vdetect)
460                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
461
462         if (!pwd_bo)
463                 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_clr);
464
465         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
466                 writel(POWER_CTRL_VBUS_VALID_IRQ,
467                         &power_regs->hw_power_ctrl_clr);
468
469         if (prev_5v_brnout) {
470                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
471                         &power_regs->hw_power_5vctrl_set);
472                 writel(POWER_RESET_UNLOCK_KEY,
473                         &power_regs->hw_power_reset);
474         } else {
475                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
476                         &power_regs->hw_power_5vctrl_clr);
477                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
478                         &power_regs->hw_power_reset);
479         }
480
481         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
482                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
483                         &power_regs->hw_power_ctrl_clr);
484
485         if (prev_5v_droop)
486                 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
487                         &power_regs->hw_power_ctrl_set);
488         else
489                 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
490                         &power_regs->hw_power_ctrl_clr);
491 }
492
493 /**
494  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
495  *
496  * This function enables the 4P2 regulator and switches the DC-DC converter
497  * to use the 4P2 input.
498  */
499 static void mxs_power_init_4p2_regulator(void)
500 {
501         uint32_t tmp, tmp2;
502
503         debug("SPL: Enabling 4P2 regulator\n");
504
505         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
506
507         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
508
509         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
510                 &power_regs->hw_power_5vctrl_clr);
511         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
512
513         /* Power up the 4p2 rail and logic/control */
514         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
515                 &power_regs->hw_power_5vctrl_clr);
516
517         /*
518          * Start charging up the 4p2 capacitor. We ramp of this charge
519          * gradually to avoid large inrush current from the 5V cable which can
520          * cause transients/problems
521          */
522         debug("SPL: Charging 4P2 capacitor\n");
523         mxs_enable_4p2_dcdc_input(0);
524
525         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
526                 /*
527                  * If we arrived here, we were unable to recover from mx23 chip
528                  * errata 5837. 4P2 is disabled and sufficient battery power is
529                  * not present. Exiting to not enable DCDC power during 5V
530                  * connected state.
531                  */
532                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
533                         POWER_DCDC4P2_ENABLE_DCDC);
534                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
535                         &power_regs->hw_power_5vctrl_set);
536
537                 debug("SPL: Unable to recover from mx23 errata 5837\n");
538                 hang();
539         }
540
541         /*
542          * Here we set the 4p2 brownout level to something very close to 4.2V.
543          * We then check the brownout status. If the brownout status is false,
544          * the voltage is already close to the target voltage of 4.2V so we
545          * can go ahead and set the 4P2 current limit to our max target limit.
546          * If the brownout status is true, we need to ramp up the current limit
547          * so that we don't cause large inrush current issues. We step up the
548          * current limit until the brownout status is false or until we've
549          * reached our maximum defined 4p2 current limit.
550          */
551         debug("SPL: Setting 4P2 brownout level\n");
552         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
553                         POWER_DCDC4P2_BO_MASK,
554                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
555
556         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
557                 writel(0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET,
558                         &power_regs->hw_power_5vctrl_set);
559         } else {
560                 tmp = (readl(&power_regs->hw_power_5vctrl) &
561                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
562                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
563                 while (tmp < 0x3f) {
564                         if (!(readl(&power_regs->hw_power_sts) &
565                                         POWER_STS_DCDC_4P2_BO)) {
566                                 tmp = readl(&power_regs->hw_power_5vctrl);
567                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
568                                 udelay(100);
569                                 writel(tmp, &power_regs->hw_power_5vctrl);
570                                 break;
571                         } else {
572                                 tmp++;
573                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
574                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
575                                 tmp2 |= tmp <<
576                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
577                                 writel(tmp2, &power_regs->hw_power_5vctrl);
578                                 udelay(100);
579                         }
580                 }
581         }
582
583         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
584         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
585 }
586
587 /**
588  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
589  *
590  * This function configures the DC-DC converter to be supplied from the 4P2
591  * linear regulator.
592  */
593 static void mxs_power_init_dcdc_4p2_source(void)
594 {
595         debug("SPL: Switching DC-DC converters to 4P2\n");
596
597         if (!(readl(&power_regs->hw_power_dcdc4p2) &
598                 POWER_DCDC4P2_ENABLE_DCDC)) {
599                 debug("SPL: Already switched - aborting\n");
600                 hang();
601         }
602
603         mxs_enable_4p2_dcdc_input(1);
604
605         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
606                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
607                         POWER_DCDC4P2_ENABLE_DCDC);
608                 writel(POWER_5VCTRL_ENABLE_DCDC,
609                         &power_regs->hw_power_5vctrl_clr);
610                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
611                         &power_regs->hw_power_5vctrl_set);
612         }
613 }
614
615 /**
616  * mxs_power_enable_4p2() - Power up the 4P2 regulator
617  *
618  * This function drives the process of powering up the 4P2 linear regulator
619  * and switching the DC-DC converter input over to the 4P2 linear regulator.
620  */
621 static void mxs_power_enable_4p2(void)
622 {
623         uint32_t vdddctrl, vddactrl, vddioctrl;
624         uint32_t tmp;
625
626         debug("SPL: Powering up 4P2 regulator\n");
627
628         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
629         vddactrl = readl(&power_regs->hw_power_vddactrl);
630         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
631
632         setbits_le32(&power_regs->hw_power_vdddctrl,
633                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
634                 POWER_VDDDCTRL_PWDN_BRNOUT);
635
636         setbits_le32(&power_regs->hw_power_vddactrl,
637                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
638                 POWER_VDDACTRL_PWDN_BRNOUT);
639
640         setbits_le32(&power_regs->hw_power_vddioctrl,
641                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
642
643         mxs_power_init_4p2_params();
644         mxs_power_init_4p2_regulator();
645
646         /* Shutdown battery (none present) */
647         if (!mxs_is_batt_ready()) {
648                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
649                                 POWER_DCDC4P2_BO_MASK);
650                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
651                                 &power_regs->hw_power_ctrl_clr);
652                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
653                                 &power_regs->hw_power_ctrl_clr);
654         }
655
656         mxs_power_init_dcdc_4p2_source();
657
658         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
659         udelay(20);
660         writel(vddactrl, &power_regs->hw_power_vddactrl);
661         udelay(20);
662         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
663
664         /*
665          * Check if FET is enabled on either powerout and if so,
666          * disable load.
667          */
668         tmp = 0;
669         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
670                         POWER_VDDDCTRL_DISABLE_FET);
671         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
672                         POWER_VDDACTRL_DISABLE_FET);
673         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
674                         POWER_VDDIOCTRL_DISABLE_FET);
675         if (tmp)
676                 writel(POWER_CHARGE_ENABLE_LOAD,
677                         &power_regs->hw_power_charge_clr);
678
679         debug("SPL: 4P2 regulator powered-up\n");
680 }
681
682 /**
683  * mxs_boot_valid_5v() - Boot from 5V supply
684  *
685  * This function configures the power block to boot from valid 5V input.
686  * This is called only if the 5V is reliable and can properly supply the
687  * CPU. This function proceeds to configure the 4P2 converter to be supplied
688  * from the 5V input.
689  */
690 static void mxs_boot_valid_5v(void)
691 {
692         debug("SPL: Booting from 5V supply\n");
693
694         /*
695          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
696          * disconnect event. FIXME
697          */
698         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
699                 &power_regs->hw_power_5vctrl_set);
700
701         /* Configure polarity to check for 5V disconnection. */
702         writel(POWER_CTRL_POLARITY_VBUSVALID |
703                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
704                 &power_regs->hw_power_ctrl_clr);
705
706         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
707                 &power_regs->hw_power_ctrl_clr);
708
709         mxs_power_enable_4p2();
710 }
711
712 /**
713  * mxs_powerdown() - Shut down the system
714  *
715  * This function powers down the CPU completely.
716  */
717 static void mxs_powerdown(void)
718 {
719         debug("Powering Down\n");
720
721         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
722         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
723                 &power_regs->hw_power_reset);
724 }
725
726 /**
727  * mxs_batt_boot() - Configure the power block to boot from battery input
728  *
729  * This function configures the power block to boot from the battery voltage
730  * supply.
731  */
732 static void mxs_batt_boot(void)
733 {
734         debug("SPL: Configuring power block to boot from battery\n");
735
736         writel(POWER_5VCTRL_PWDN_5VBRNOUT,
737                 &power_regs->hw_power_5vctrl_clr);
738         writel(POWER_5VCTRL_ENABLE_DCDC,
739                 &power_regs->hw_power_5vctrl_clr);
740
741         clrbits_le32(&power_regs->hw_power_dcdc4p2,
742                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
743         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
744
745         /* 5V to battery handoff. */
746         writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_set);
747         udelay(30);
748         writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_clr);
749
750         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
751
752         clrsetbits_le32(&power_regs->hw_power_minpwr,
753                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
754
755         mxs_power_set_linreg();
756
757         clrbits_le32(&power_regs->hw_power_vdddctrl,
758                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
759
760         clrbits_le32(&power_regs->hw_power_vddactrl,
761                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
762
763         clrbits_le32(&power_regs->hw_power_vddioctrl,
764                 POWER_VDDIOCTRL_DISABLE_FET);
765
766         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
767                 &power_regs->hw_power_5vctrl_set);
768
769         writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_set);
770
771         clrsetbits_le32(&power_regs->hw_power_5vctrl,
772                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
773                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
774
775         mxs_power_enable_4p2();
776 }
777
778 /**
779  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
780  *
781  * This function tests if the 5V input can reliably supply the system. If it
782  * can, then proceed to configuring the system to boot from 5V source, otherwise
783  * try booting from battery supply. If we can not boot from battery supply
784  * either, shut down the system.
785  */
786 static void mxs_handle_5v_conflict(void)
787 {
788         uint32_t tmp;
789
790         debug("SPL: Resolving 5V conflict\n");
791
792         setbits_le32(&power_regs->hw_power_vddioctrl,
793                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
794
795         for (;;) {
796                 tmp = readl(&power_regs->hw_power_sts);
797
798                 if (tmp & POWER_STS_VDDIO_BO) {
799                         /*
800                          * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
801                          * becomes unreliable
802                          */
803                         debug("SPL: VDDIO has a brownout\n");
804                         mxs_powerdown();
805                         break;
806                 }
807
808                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
809                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
810                         mxs_boot_valid_5v();
811                         break;
812                 } else {
813                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
814                         mxs_powerdown();
815                         break;
816                 }
817
818                 /*
819                  * TODO: I can't see this being reached. We'll either
820                  * powerdown or boot from a stable 5V supply.
821                  */
822                 if (tmp & POWER_STS_PSWITCH_MASK) {
823                         debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
824                         mxs_batt_boot();
825                         break;
826                 }
827         }
828 }
829
830 /**
831  * mxs_5v_boot() - Configure the power block to boot from 5V input
832  *
833  * This function handles configuration of the power block when supplied by
834  * a 5V input.
835  */
836 static void mxs_5v_boot(void)
837 {
838         debug("SPL: Configuring power block to boot from 5V input\n");
839
840         /*
841          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
842          * but their implementation always returns 1 so we omit it here.
843          */
844         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
845                 debug("SPL: 5V VDD good\n");
846                 mxs_boot_valid_5v();
847                 return;
848         }
849
850         udelay(1000);
851         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
852                 debug("SPL: 5V VDD good (after delay)\n");
853                 mxs_boot_valid_5v();
854                 return;
855         }
856
857         debug("SPL: 5V VDD not good\n");
858         mxs_handle_5v_conflict();
859 }
860
861 static void mxs_fixed_batt_boot(void)
862 {
863         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
864
865         writel(POWER_5VCTRL_ENABLE_DCDC |
866                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
867                 POWER_5VCTRL_PWDN_5VBRNOUT |
868                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
869                 &power_regs->hw_power_5vctrl_set);
870
871         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
872
873         clrbits_le32(&power_regs->hw_power_vdddctrl,
874                 POWER_VDDDCTRL_DISABLE_FET |
875                 POWER_VDDDCTRL_ENABLE_LINREG |
876                 POWER_VDDDCTRL_DISABLE_STEPPING);
877
878         clrbits_le32(&power_regs->hw_power_vddactrl,
879                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
880                 POWER_VDDACTRL_DISABLE_STEPPING);
881
882         clrbits_le32(&power_regs->hw_power_vddioctrl,
883                 POWER_VDDIOCTRL_DISABLE_FET |
884                 POWER_VDDIOCTRL_DISABLE_STEPPING);
885
886         /* Stop 5V detection */
887         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
888                 &power_regs->hw_power_5vctrl_clr);
889 }
890
891 /**
892  * mxs_init_batt_bo() - Configure battery brownout threshold
893  *
894  * This function configures the battery input brownout threshold. The value
895  * at which the battery brownout happens is configured to 3.0V in the code.
896  */
897 static void mxs_init_batt_bo(void)
898 {
899         debug("SPL: Initialising battery brown-out level to 3.0V\n");
900
901         /* Brownout at 3V */
902         clrsetbits_le32(&power_regs->hw_power_battmonitor,
903                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
904                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
905
906         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
907         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
908 }
909
910 /**
911  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
912  *
913  * This function turns off the VDDD linear regulator and therefore makes
914  * the VDDD rail be supplied only by the DC-DC converter.
915  */
916 static void mxs_switch_vddd_to_dcdc_source(void)
917 {
918         debug("SPL: Switching VDDD to DC-DC converters\n");
919
920         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
921                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
922                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
923
924         clrbits_le32(&power_regs->hw_power_vdddctrl,
925                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
926                 POWER_VDDDCTRL_DISABLE_STEPPING);
927 }
928
929 /**
930  * mxs_power_configure_power_source() - Configure power block source
931  *
932  * This function is the core of the power configuration logic. The function
933  * selects the power block input source and configures the whole power block
934  * accordingly. After the configuration is complete and the system is stable
935  * again, the function switches the CPU clock source back to PLL. Finally,
936  * the function switches the voltage rails to DC-DC converter.
937  */
938 static void mxs_power_configure_power_source(void)
939 {
940         struct mxs_lradc_regs *lradc_regs =
941                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
942
943         debug("SPL: Configuring power source\n");
944
945         mxs_src_power_init();
946
947         if (!fixed_batt_supply) {
948                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
949                         if (mxs_is_batt_ready()) {
950                                 /* 5V source detected, good battery detected. */
951                                 mxs_batt_boot();
952                         } else {
953                                 if (!mxs_is_batt_good()) {
954                                         /* 5V source detected, bad battery detected. */
955                                         writel(LRADC_CONVERSION_AUTOMATIC,
956                                                 &lradc_regs->hw_lradc_conversion_clr);
957                                         clrbits_le32(&power_regs->hw_power_battmonitor,
958                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
959                                 }
960                                 mxs_5v_boot();
961                         }
962                 } else {
963                         /* 5V not detected, booting from battery. */
964                         mxs_batt_boot();
965                 }
966         } else {
967                 mxs_fixed_batt_boot();
968         }
969
970         /*
971          * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
972          * from USB VBUS
973          */
974         mxs_power_clock2pll();
975
976         mxs_init_batt_bo();
977
978         mxs_switch_vddd_to_dcdc_source();
979
980 #ifdef CONFIG_SOC_MX23
981         /* Fire up the VDDMEM LinReg now that we're all set. */
982         debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
983         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
984                 &power_regs->hw_power_vddmemctrl);
985 #endif
986 }
987
988 /**
989  * mxs_enable_output_rail_protection() - Enable power rail protection
990  *
991  * This function enables overload protection on the power rails. This is
992  * triggered if the power rails' voltage drops rapidly due to overload and
993  * in such case, the supply to the powerrail is cut-off, protecting the
994  * CPU from damage. Note that under such condition, the system will likely
995  * crash or misbehave.
996  */
997 static void mxs_enable_output_rail_protection(void)
998 {
999         debug("SPL: Enabling output rail protection\n");
1000
1001         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1002                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1003
1004         setbits_le32(&power_regs->hw_power_vdddctrl,
1005                         POWER_VDDDCTRL_PWDN_BRNOUT);
1006
1007         setbits_le32(&power_regs->hw_power_vddactrl,
1008                         POWER_VDDACTRL_PWDN_BRNOUT);
1009
1010         setbits_le32(&power_regs->hw_power_vddioctrl,
1011                         POWER_VDDIOCTRL_PWDN_BRNOUT);
1012 }
1013
1014 /**
1015  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1016  *
1017  * This function tests if the VDDIO rail is supplied by linear regulator
1018  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1019  * returns 0 if powered by the DC-DC converter.
1020  */
1021 static int mxs_get_vddio_power_source_off(void)
1022 {
1023         uint32_t tmp;
1024
1025         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1026                 !(readl(&power_regs->hw_power_5vctrl) &
1027                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1028
1029                 tmp = readl(&power_regs->hw_power_vddioctrl);
1030                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1031                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1032                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1033                                 return 1;
1034                         }
1035                 }
1036
1037                 if (!(readl(&power_regs->hw_power_5vctrl) &
1038                         POWER_5VCTRL_ENABLE_DCDC)) {
1039                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1040                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1041                                 return 1;
1042                         }
1043                 }
1044         }
1045
1046         return 0;
1047 }
1048
1049 /**
1050  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1051  *
1052  * This function tests if the VDDD rail is supplied by linear regulator
1053  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1054  * returns 0 if powered by the DC-DC converter.
1055  */
1056 static int mxs_get_vddd_power_source_off(void)
1057 {
1058         uint32_t tmp;
1059
1060         tmp = readl(&power_regs->hw_power_vdddctrl);
1061         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1062                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1063                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1064                         return 1;
1065                 }
1066         }
1067
1068         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1069                 if (!(readl(&power_regs->hw_power_5vctrl) &
1070                         POWER_5VCTRL_ENABLE_DCDC)) {
1071                         return 1;
1072                 }
1073         }
1074
1075         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1076                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1077                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1078                         return 1;
1079                 }
1080         }
1081
1082         return 0;
1083 }
1084
1085 static int mxs_get_vdda_power_source_off(void)
1086 {
1087         uint32_t tmp;
1088
1089         tmp = readl(&power_regs->hw_power_vddactrl);
1090         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1091                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1092                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1093                         return 1;
1094                 }
1095         }
1096
1097         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1098                 if (!(readl(&power_regs->hw_power_5vctrl) &
1099                         POWER_5VCTRL_ENABLE_DCDC)) {
1100                         return 1;
1101                 }
1102         }
1103
1104         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1105                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1106                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1107                         return 1;
1108                 }
1109         }
1110
1111         return 0;
1112 }
1113
1114 struct mxs_vddx_cfg {
1115         uint32_t                *reg;
1116         uint8_t                 step_mV;
1117         uint16_t                lowest_mV;
1118         uint16_t                highest_mV;
1119         int                     (*powered_by_linreg)(void);
1120         uint32_t                trg_mask;
1121         uint32_t                bo_irq;
1122         uint32_t                bo_enirq;
1123         uint32_t                bo_offset_mask;
1124         uint32_t                bo_offset_offset;
1125         uint16_t                bo_min_mV;
1126         uint16_t                bo_max_mV;
1127 };
1128
1129 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1130
1131 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1132         .reg                    = POWER_REG(hw_power_vddioctrl),
1133 #if defined(CONFIG_SOC_MX23)
1134         .step_mV                = 25,
1135 #else
1136         .step_mV                = 50,
1137 #endif
1138         .lowest_mV              = 2800,
1139         .highest_mV             = 3600,
1140         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1141         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1142         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1143         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1144         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1145         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1146         .bo_min_mV              = 2700,
1147         .bo_max_mV              = 3475,
1148 };
1149
1150 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1151         .reg                    = POWER_REG(hw_power_vdddctrl),
1152         .step_mV                = 25,
1153         .lowest_mV              = 800,
1154         .highest_mV             = 1575,
1155         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1156         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1157         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1158         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1159         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1160         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1161         .bo_min_mV              = 800,
1162         .bo_max_mV              = 1475,
1163 };
1164
1165 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1166         .reg                    = POWER_REG(hw_power_vddactrl),
1167         .step_mV                = 25,
1168         .lowest_mV              = 1800,
1169         .highest_mV             = 3600,
1170         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1171         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1172         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1173         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1174         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1175         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1176         .bo_min_mV              = 1400,
1177         .bo_max_mV              = 2175,
1178 };
1179
1180 #ifdef CONFIG_SOC_MX23
1181 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1182         .reg                    = POWER_REG(hw_power_vddmemctrl),
1183         .step_mV                = 50,
1184         .lowest_mV              = 1500,
1185         .highest_mV             = 1700,
1186         .powered_by_linreg      = NULL,
1187         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1188         .bo_irq                 = 0,
1189         .bo_enirq               = 0,
1190         .bo_offset_mask         = 0,
1191         .bo_offset_offset       = 0,
1192 };
1193 #endif
1194
1195 /**
1196  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1197  * @cfg:                Configuration data of the DC-DC converter rail
1198  * @new_target:         New target voltage of the DC-DC converter rail
1199  * @new_brownout:       New brownout trigger voltage
1200  *
1201  * This function configures the output voltage on the DC-DC converter rail.
1202  * The rail is selected by the @cfg argument. The new voltage target is
1203  * selected by the @new_target and the voltage is specified in mV. The
1204  * new brownout value is selected by the @new_brownout argument and the
1205  * value is also in mV.
1206  */
1207 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1208                                 uint32_t new_target, uint32_t bo_offset)
1209 {
1210         uint32_t cur_target, diff, bo_int = 0;
1211         int powered_by_linreg = 0;
1212         int adjust_up;
1213
1214         if (new_target < cfg->lowest_mV) {
1215                 new_target = cfg->lowest_mV;
1216         }
1217         if (new_target > cfg->highest_mV) {
1218                 new_target = cfg->highest_mV;
1219         }
1220
1221         if (new_target - bo_offset < cfg->bo_min_mV) {
1222                 bo_offset = new_target - cfg->bo_min_mV;
1223         } else if (new_target - bo_offset > cfg->bo_max_mV) {
1224                 bo_offset = new_target - cfg->bo_max_mV;
1225         }
1226
1227         bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1228
1229         cur_target = readl(cfg->reg);
1230         cur_target &= cfg->trg_mask;
1231         cur_target *= cfg->step_mV;
1232         cur_target += cfg->lowest_mV;
1233
1234         adjust_up = new_target > cur_target;
1235         if (cfg->powered_by_linreg)
1236                 powered_by_linreg = cfg->powered_by_linreg();
1237
1238         if (adjust_up && cfg->bo_irq) {
1239                 if (powered_by_linreg) {
1240                         bo_int = readl(&power_regs->hw_power_ctrl);
1241                         writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1242                 }
1243                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1244         }
1245
1246         do {
1247                 if (abs(new_target - cur_target) > 100) {
1248                         if (adjust_up)
1249                                 diff = cur_target + 100;
1250                         else
1251                                 diff = cur_target - 100;
1252                 } else {
1253                         diff = new_target;
1254                 }
1255
1256                 diff -= cfg->lowest_mV;
1257                 diff /= cfg->step_mV;
1258
1259                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1260
1261                 if (powered_by_linreg ||
1262                         (readl(&power_regs->hw_power_sts) &
1263                                 POWER_STS_VDD5V_GT_VDDIO)) {
1264                         udelay(500);
1265                 } else {
1266                         while (!(readl(&power_regs->hw_power_sts) &
1267                                         POWER_STS_DC_OK)) {
1268
1269                         }
1270                 }
1271
1272                 cur_target = readl(cfg->reg);
1273                 cur_target &= cfg->trg_mask;
1274                 cur_target *= cfg->step_mV;
1275                 cur_target += cfg->lowest_mV;
1276         } while (new_target > cur_target);
1277
1278         if (cfg->bo_irq) {
1279                 if (adjust_up && powered_by_linreg) {
1280                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1281                         if (bo_int & cfg->bo_enirq)
1282                                 writel(cfg->bo_enirq,
1283                                         &power_regs->hw_power_ctrl_set);
1284                 }
1285
1286                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1287                                 bo_offset << cfg->bo_offset_offset);
1288         }
1289 }
1290
1291 /**
1292  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1293  *
1294  * This function starts and configures the LRADC block. This allows the
1295  * power initialization code to measure battery voltage and based on this
1296  * knowledge, decide whether to boot at all, boot from battery or boot
1297  * from 5V input.
1298  */
1299 static void mxs_setup_batt_detect(void)
1300 {
1301         debug("SPL: Starting battery voltage measurement logic\n");
1302
1303         mxs_lradc_init();
1304         mxs_lradc_enable_batt_measurement();
1305         udelay(10);
1306 }
1307
1308 /**
1309  * mxs_ungate_power() - Ungate the POWER block
1310  *
1311  * This function ungates clock to the power block. In case the power block
1312  * was still gated at this point, it will not be possible to configure the
1313  * block and therefore the power initialization would fail. This function
1314  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1315  */
1316 static void mxs_ungate_power(void)
1317 {
1318 #ifdef CONFIG_SOC_MX23
1319         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1320 #endif
1321 }
1322
1323 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1324 #define auto_restart 1
1325 #else
1326 #define auto_restart 0
1327 #endif
1328
1329 /**
1330  * mxs_power_init() - The power block init main function
1331  *
1332  * This function calls all the power block initialization functions in
1333  * proper sequence to start the power block.
1334  */
1335 #define VDDX_VAL(v)     (v) / 1000, (v) / 100 % 10
1336
1337 void mxs_power_init(void)
1338 {
1339         debug("SPL: Initialising Power Block\n");
1340
1341         mxs_ungate_power();
1342
1343         mxs_power_clock2xtal();
1344         if (mxs_power_set_auto_restart(auto_restart)) {
1345                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1346         }
1347         mxs_power_set_linreg();
1348
1349         if (!fixed_batt_supply) {
1350                 mxs_power_setup_5v_detect();
1351                 mxs_setup_batt_detect();
1352         }
1353
1354         mxs_power_configure_power_source();
1355         mxs_enable_output_rail_protection();
1356
1357         debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1358                 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1359         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1360         debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1361                 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1362         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1363         debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1364                 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1365         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1366 #ifdef CONFIG_SOC_MX23
1367         debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1368                 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1369         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1370 #else
1371         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1372                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1373 #endif
1374         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1375                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1376                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1377                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1378         if (!fixed_batt_supply)
1379                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1380                         &power_regs->hw_power_5vctrl_set);
1381 }
1382
1383 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1384 /**
1385  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1386  *
1387  * This function waits until the power-switch was pressed to start booting
1388  * the board.
1389  */
1390 void mxs_power_wait_pswitch(void)
1391 {
1392         debug("SPL: Waiting for power switch input\n");
1393         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1394                 ;
1395 }
1396 #endif