ARM: mxs: various bug fixes for power init code
[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2  * Freescale i.MX28 Boot PMIC init
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14
15 #include "mxs_init.h"
16
17 #ifdef CONFIG_SYS_SPL_VDDD_VAL
18 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
19 #else
20 #define VDDD_VAL        1350
21 #endif
22 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
23 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
24 #else
25 #define VDDIO_VAL       3300
26 #endif
27 #ifdef CONFIG_SYS_SPL_VDDA_VAL
28 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
29 #else
30 #define VDDA_VAL        1800
31 #endif
32 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
33 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
34 #else
35 #define VDDMEM_VAL      1700
36 #endif
37
38 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
39 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
40 #else
41 #define VDDD_BO_VAL     150
42 #endif
43 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
44 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
45 #else
46 #define VDDIO_BO_VAL    150
47 #endif
48 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
49 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
50 #else
51 #define VDDA_BO_VAL     175
52 #endif
53 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
54 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
55 #else
56 #define VDDMEM_BO_VAL   25
57 #endif
58
59 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
60 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
61 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
62 #endif
63 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
64 #else
65 /* Brownout default at 3V */
66 #define BATT_BO_VAL     ((3000 - 2400) / 40)
67 #endif
68
69 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
70 static const int fixed_batt_supply = 1;
71 #else
72 static const int fixed_batt_supply;
73 #endif
74
75 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
76
77 /**
78  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
79  *
80  * This function switches the CPU core clock from PLL to 24MHz XTAL
81  * oscilator. This is necessary if the PLL is being reconfigured to
82  * prevent crash of the CPU core.
83  */
84 static void mxs_power_clock2xtal(void)
85 {
86         struct mxs_clkctrl_regs *clkctrl_regs =
87                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
88
89         /* Set XTAL as CPU reference clock */
90         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
91                 &clkctrl_regs->hw_clkctrl_clkseq_set);
92 }
93
94 /**
95  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
96  *
97  * This function switches the CPU core clock from 24MHz XTAL oscilator
98  * to PLL. This can only be called once the PLL has re-locked and once
99  * the PLL is stable after reconfiguration.
100  */
101 static void mxs_power_clock2pll(void)
102 {
103         struct mxs_clkctrl_regs *clkctrl_regs =
104                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
105
106         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
107                         CLKCTRL_PLL0CTRL0_POWER);
108         early_delay(100);
109         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
110                         CLKCTRL_CLKSEQ_BYPASS_CPU);
111 }
112
113 static int mxs_power_wait_rtc_stat(u32 mask)
114 {
115         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
116         u32 val;
117         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
118
119         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
120                 early_delay(1);
121                 if (timeout-- < 0)
122                         break;
123         }
124         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
125 }
126
127 /**
128  * mxs_power_set_auto_restart() - Set the auto-restart bit
129  *
130  * This function ungates the RTC block and sets the AUTO_RESTART
131  * bit to work around a design bug on MX28EVK Rev. A .
132  */
133 static int mxs_power_set_auto_restart(int on)
134 {
135         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
136
137         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
138                 return 1;
139
140         /* Do nothing if flag already set */
141         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
142                 return 0;
143
144         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
145                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
146                 return 0;
147
148         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
149                 return 1;
150
151         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
152                         !on * RTC_PERSISTENT0_AUTO_RESTART,
153                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
154         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
155                 return 1;
156
157         return 0;
158 }
159
160 /**
161  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
162  *
163  * This function configures the VDDIO, VDDA and VDDD linear regulators output
164  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
165  * converter. This is the recommended setting for the case where we use both
166  * linear regulators and DC-DC converter to power the VDDIO rail.
167  */
168 static void mxs_power_set_linreg(void)
169 {
170         /* Set linear regulator 25mV below switching converter */
171         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
172                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
173                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
174
175         clrsetbits_le32(&power_regs->hw_power_vddactrl,
176                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
177                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
178
179         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
180                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
181                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
182 }
183
184 /**
185  * mxs_get_batt_volt() - Measure battery input voltage
186  *
187  * This function retrieves the battery input voltage and returns it.
188  */
189 static int mxs_get_batt_volt(void)
190 {
191         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
192
193         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
194         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
195         volt *= 8;
196         return volt;
197 }
198
199 /**
200  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
201  *
202  * This function checks if the battery input voltage is higher than 3.6V and
203  * therefore allows the system to successfully boot using this power source.
204  */
205 static int mxs_is_batt_ready(void)
206 {
207         return (mxs_get_batt_volt() >= 3600);
208 }
209
210 /**
211  * mxs_is_batt_good() - Test if battery is operational at all
212  *
213  * This function starts recharging the battery and tests if the input current
214  * provided by the 5V input recharging the battery is also sufficient to power
215  * the DC-DC converter.
216  */
217 static int mxs_is_batt_good(void)
218 {
219         uint32_t volt = mxs_get_batt_volt();
220
221         if ((volt >= 2400) && (volt <= 4300))
222                 return 1;
223
224         clrsetbits_le32(&power_regs->hw_power_5vctrl,
225                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
226                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
227         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
228                 &power_regs->hw_power_5vctrl_clr);
229
230         clrsetbits_le32(&power_regs->hw_power_charge,
231                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
232                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
233
234         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
235         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
236                 &power_regs->hw_power_5vctrl_clr);
237
238         early_delay(500000);
239
240         volt = mxs_get_batt_volt();
241
242         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
243                 &power_regs->hw_power_charge_clr);
244         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
245
246         if (volt >= 3500) {
247                 return 0;
248         }
249         if (volt >= 2400) {
250                 return 1;
251         }
252         return 0;
253 }
254
255 /**
256  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
257  *
258  * This function enables the 5V detection comparator and sets the 5V valid
259  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
260  * under high load, the voltage drop on the 5V input won't be so critical
261  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
262  * converter and thus making the system crash.
263  */
264 static void mxs_power_setup_5v_detect(void)
265 {
266         /* Start 5V detection */
267         clrsetbits_le32(&power_regs->hw_power_5vctrl,
268                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
269                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
270                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
271 }
272
273 /**
274  * mxs_src_power_init() - Preconfigure the power block
275  *
276  * This function configures reasonable values for the DC-DC control loop
277  * and battery monitor.
278  */
279 static void mxs_src_power_init(void)
280 {
281         /* Improve efficieny and reduce transient ripple */
282         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
283                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
284
285         clrsetbits_le32(&power_regs->hw_power_dclimits,
286                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
287                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
288
289         if (!fixed_batt_supply) {
290                 /* FIXME: This requires the LRADC to be set up! */
291                 setbits_le32(&power_regs->hw_power_battmonitor,
292                         POWER_BATTMONITOR_EN_BATADJ);
293         } else {
294                 clrbits_le32(&power_regs->hw_power_battmonitor,
295                         POWER_BATTMONITOR_EN_BATADJ);
296         }
297
298         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
299         clrsetbits_le32(&power_regs->hw_power_loopctrl,
300                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
301                         POWER_LOOPCTRL_RCSCALE_THRESH |
302                         POWER_LOOPCTRL_EN_RCSCALE_8X);
303
304         clrsetbits_le32(&power_regs->hw_power_minpwr,
305                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
306
307         if (!fixed_batt_supply) {
308                 /* 5V to battery handoff ... FIXME */
309                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
310                 early_delay(30);
311                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
312         }
313 }
314
315 /**
316  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
317  *
318  * This function configures the necessary parameters for the 4P2 linear
319  * regulator to supply the DC-DC converter from 5V input.
320  */
321 static void mxs_power_init_4p2_params(void)
322 {
323         /* Setup 4P2 parameters */
324         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
325                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
326                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
327
328         clrsetbits_le32(&power_regs->hw_power_5vctrl,
329                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
330                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
331
332         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
333                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
334                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
335                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
336
337         clrsetbits_le32(&power_regs->hw_power_5vctrl,
338                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
339                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
340 }
341
342 /**
343  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
344  * @xfer:       Select if the input shall be enabled or disabled
345  *
346  * This function enables or disables the 4P2 input into the DC-DC converter.
347  */
348 static void mxs_enable_4p2_dcdc_input(int xfer)
349 {
350         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
351         uint32_t prev_5v_brnout, prev_5v_droop;
352
353         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
354                                 POWER_5VCTRL_PWDN_5VBRNOUT;
355         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
356                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
357
358         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
359         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
360                 &power_regs->hw_power_reset);
361
362         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
363
364         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
365                         POWER_5VCTRL_ENABLE_DCDC)) {
366                 return;
367         }
368
369         /*
370          * Recording orignal values that will be modified temporarlily
371          * to handle a chip bug. See chip errata for CQ ENGR00115837
372          */
373         tmp = readl(&power_regs->hw_power_5vctrl);
374         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
375         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
376
377         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
378
379         /*
380          * Disable mechanisms that get erroneously tripped by when setting
381          * the DCDC4P2 EN_DCDC
382          */
383         clrbits_le32(&power_regs->hw_power_5vctrl,
384                 POWER_5VCTRL_VBUSVALID_5VDETECT |
385                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
386
387         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
388
389         if (xfer) {
390                 setbits_le32(&power_regs->hw_power_5vctrl,
391                                 POWER_5VCTRL_DCDC_XFER);
392                 early_delay(20);
393                 clrbits_le32(&power_regs->hw_power_5vctrl,
394                                 POWER_5VCTRL_DCDC_XFER);
395
396                 setbits_le32(&power_regs->hw_power_5vctrl,
397                                 POWER_5VCTRL_ENABLE_DCDC);
398         } else {
399                 setbits_le32(&power_regs->hw_power_dcdc4p2,
400                                 POWER_DCDC4P2_ENABLE_DCDC);
401         }
402
403         early_delay(25);
404
405         clrsetbits_le32(&power_regs->hw_power_5vctrl,
406                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
407
408         if (vbus_5vdetect)
409                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
410
411         if (!pwd_bo)
412                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
413
414         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
415                 writel(POWER_CTRL_VBUS_VALID_IRQ,
416                         &power_regs->hw_power_ctrl_clr);
417
418         if (prev_5v_brnout) {
419                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
420                         &power_regs->hw_power_5vctrl_set);
421                 writel(POWER_RESET_UNLOCK_KEY,
422                         &power_regs->hw_power_reset);
423         } else {
424                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
425                         &power_regs->hw_power_5vctrl_clr);
426                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
427                         &power_regs->hw_power_reset);
428         }
429
430         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
431                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
432                         &power_regs->hw_power_ctrl_clr);
433
434         if (prev_5v_droop)
435                 clrbits_le32(&power_regs->hw_power_ctrl,
436                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
437         else
438                 setbits_le32(&power_regs->hw_power_ctrl,
439                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
440 }
441
442 /**
443  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
444  *
445  * This function enables the 4P2 regulator and switches the DC-DC converter
446  * to use the 4P2 input.
447  */
448 static void mxs_power_init_4p2_regulator(void)
449 {
450         uint32_t tmp, tmp2;
451
452         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
453
454         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
455
456         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
457                 &power_regs->hw_power_5vctrl_clr);
458         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
459
460         /* Power up the 4p2 rail and logic/control */
461         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
462                 &power_regs->hw_power_5vctrl_clr);
463
464         /*
465          * Start charging up the 4p2 capacitor. We ramp of this charge
466          * gradually to avoid large inrush current from the 5V cable which can
467          * cause transients/problems
468          */
469         mxs_enable_4p2_dcdc_input(0);
470
471         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
472                 /*
473                  * If we arrived here, we were unable to recover from mx23 chip
474                  * errata 5837. 4P2 is disabled and sufficient battery power is
475                  * not present. Exiting to not enable DCDC power during 5V
476                  * connected state.
477                  */
478                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
479                         POWER_DCDC4P2_ENABLE_DCDC);
480                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
481                         &power_regs->hw_power_5vctrl_set);
482                 hang();
483         }
484
485         /*
486          * Here we set the 4p2 brownout level to something very close to 4.2V.
487          * We then check the brownout status. If the brownout status is false,
488          * the voltage is already close to the target voltage of 4.2V so we
489          * can go ahead and set the 4P2 current limit to our max target limit.
490          * If the brownout status is true, we need to ramp up the current limit
491          * so that we don't cause large inrush current issues. We step up the
492          * current limit until the brownout status is false or until we've
493          * reached our maximum defined 4p2 current limit.
494          */
495         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
496                         POWER_DCDC4P2_BO_MASK,
497                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
498
499         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
500                 setbits_le32(&power_regs->hw_power_5vctrl,
501                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
502         } else {
503                 tmp = (readl(&power_regs->hw_power_5vctrl) &
504                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
505                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
506                 while (tmp < 0x3f) {
507                         if (!(readl(&power_regs->hw_power_sts) &
508                                         POWER_STS_DCDC_4P2_BO)) {
509                                 tmp = readl(&power_regs->hw_power_5vctrl);
510                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
511                                 early_delay(100);
512                                 writel(tmp, &power_regs->hw_power_5vctrl);
513                                 break;
514                         } else {
515                                 tmp++;
516                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
517                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
518                                 tmp2 |= tmp <<
519                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
520                                 writel(tmp2, &power_regs->hw_power_5vctrl);
521                                 early_delay(100);
522                         }
523                 }
524         }
525
526         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
527         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
528 }
529
530 /**
531  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
532  *
533  * This function configures the DC-DC converter to be supplied from the 4P2
534  * linear regulator.
535  */
536 static void mxs_power_init_dcdc_4p2_source(void)
537 {
538         if (!(readl(&power_regs->hw_power_dcdc4p2) &
539                 POWER_DCDC4P2_ENABLE_DCDC)) {
540                 hang();
541         }
542
543         mxs_enable_4p2_dcdc_input(1);
544
545         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
546                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
547                         POWER_DCDC4P2_ENABLE_DCDC);
548                 writel(POWER_5VCTRL_ENABLE_DCDC,
549                         &power_regs->hw_power_5vctrl_clr);
550                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
551                         &power_regs->hw_power_5vctrl_set);
552         }
553 }
554
555 /**
556  * mxs_power_enable_4p2() - Power up the 4P2 regulator
557  *
558  * This function drives the process of powering up the 4P2 linear regulator
559  * and switching the DC-DC converter input over to the 4P2 linear regulator.
560  */
561 static void mxs_power_enable_4p2(void)
562 {
563         uint32_t vdddctrl, vddactrl, vddioctrl;
564         uint32_t tmp;
565
566         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
567         vddactrl = readl(&power_regs->hw_power_vddactrl);
568         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
569
570         setbits_le32(&power_regs->hw_power_vdddctrl,
571                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
572                 POWER_VDDDCTRL_PWDN_BRNOUT);
573
574         setbits_le32(&power_regs->hw_power_vddactrl,
575                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
576                 POWER_VDDACTRL_PWDN_BRNOUT);
577
578         setbits_le32(&power_regs->hw_power_vddioctrl,
579                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
580
581         mxs_power_init_4p2_params();
582         mxs_power_init_4p2_regulator();
583
584         /* Shutdown battery (none present) */
585         if (!mxs_is_batt_ready()) {
586                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
587                                 POWER_DCDC4P2_BO_MASK);
588                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
589                                 &power_regs->hw_power_ctrl_clr);
590                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
591                                 &power_regs->hw_power_ctrl_clr);
592         }
593
594         mxs_power_init_dcdc_4p2_source();
595
596         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
597         early_delay(20);
598         writel(vddactrl, &power_regs->hw_power_vddactrl);
599         early_delay(20);
600         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
601
602         /*
603          * Check if FET is enabled on either powerout and if so,
604          * disable load.
605          */
606         tmp = 0;
607         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
608                         POWER_VDDDCTRL_DISABLE_FET);
609         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
610                         POWER_VDDACTRL_DISABLE_FET);
611         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
612                         POWER_VDDIOCTRL_DISABLE_FET);
613         if (tmp)
614                 writel(POWER_CHARGE_ENABLE_LOAD,
615                         &power_regs->hw_power_charge_clr);
616 }
617
618 /**
619  * mxs_boot_valid_5v() - Boot from 5V supply
620  *
621  * This function configures the power block to boot from valid 5V input.
622  * This is called only if the 5V is reliable and can properly supply the
623  * CPU. This function proceeds to configure the 4P2 converter to be supplied
624  * from the 5V input.
625  */
626 static void mxs_boot_valid_5v(void)
627 {
628         /*
629          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
630          * disconnect event. FIXME
631          */
632         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
633                 &power_regs->hw_power_5vctrl_set);
634
635         /* Configure polarity to check for 5V disconnection. */
636         writel(POWER_CTRL_POLARITY_VBUSVALID |
637                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
638                 &power_regs->hw_power_ctrl_clr);
639
640         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
641                 &power_regs->hw_power_ctrl_clr);
642
643         mxs_power_enable_4p2();
644 }
645
646 /**
647  * mxs_powerdown() - Shut down the system
648  *
649  * This function powers down the CPU completely.
650  */
651 static void mxs_powerdown(void)
652 {
653         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
654         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
655                 &power_regs->hw_power_reset);
656 }
657
658 /**
659  * mxs_batt_boot() - Configure the power block to boot from battery input
660  *
661  * This function configures the power block to boot from the battery voltage
662  * supply.
663  */
664 static void mxs_batt_boot(void)
665 {
666         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
667         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
668
669         clrbits_le32(&power_regs->hw_power_dcdc4p2,
670                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
671         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
672
673         /* 5V to battery handoff. */
674         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
675         early_delay(30);
676         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
677
678         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
679
680         clrsetbits_le32(&power_regs->hw_power_minpwr,
681                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
682
683         mxs_power_set_linreg();
684
685         clrbits_le32(&power_regs->hw_power_vdddctrl,
686                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
687
688         clrbits_le32(&power_regs->hw_power_vddactrl,
689                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
690
691         clrbits_le32(&power_regs->hw_power_vddioctrl,
692                 POWER_VDDIOCTRL_DISABLE_FET);
693
694         setbits_le32(&power_regs->hw_power_5vctrl,
695                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
696
697         setbits_le32(&power_regs->hw_power_5vctrl,
698                 POWER_5VCTRL_ENABLE_DCDC);
699
700         clrsetbits_le32(&power_regs->hw_power_5vctrl,
701                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
702                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
703
704         mxs_power_enable_4p2();
705 }
706
707 /**
708  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
709  *
710  * This function tests if the 5V input can reliably supply the system. If it
711  * can, then proceed to configuring the system to boot from 5V source, otherwise
712  * try booting from battery supply. If we can not boot from battery supply
713  * either, shut down the system.
714  */
715 static void mxs_handle_5v_conflict(void)
716 {
717         uint32_t tmp;
718
719         setbits_le32(&power_regs->hw_power_vddioctrl,
720                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
721
722         for (;;) {
723                 tmp = readl(&power_regs->hw_power_sts);
724
725                 if (tmp & POWER_STS_VDDIO_BO) {
726                         /*
727                          * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
728                          * becomes unreliable
729                          */
730                         mxs_powerdown();
731                         break;
732                 }
733
734                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
735                         mxs_boot_valid_5v();
736                         break;
737                 } else {
738                         mxs_powerdown();
739                         break;
740                 }
741
742                 if (tmp & POWER_STS_PSWITCH_MASK) {
743                         mxs_batt_boot();
744                         break;
745                 }
746         }
747 }
748
749 /**
750  * mxs_5v_boot() - Configure the power block to boot from 5V input
751  *
752  * This function handles configuration of the power block when supplied by
753  * a 5V input.
754  */
755 static void mxs_5v_boot(void)
756 {
757         /*
758          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
759          * but their implementation always returns 1 so we omit it here.
760          */
761         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
762                 mxs_boot_valid_5v();
763                 return;
764         }
765
766         early_delay(1000);
767         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
768                 mxs_boot_valid_5v();
769                 return;
770         }
771
772         mxs_handle_5v_conflict();
773 }
774
775 /**
776  * mxs_init_batt_bo() - Configure battery brownout threshold
777  *
778  * This function configures the battery input brownout threshold. The value
779  * at which the battery brownout happens is configured to 3.0V in the code.
780  */
781 static void mxs_fixed_batt_boot(void)
782 {
783         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
784
785         setbits_le32(&power_regs->hw_power_5vctrl,
786                 POWER_5VCTRL_ENABLE_DCDC |
787                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
788                 POWER_5VCTRL_PWDN_5VBRNOUT |
789                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
790
791         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
792
793         clrbits_le32(&power_regs->hw_power_vdddctrl,
794                 POWER_VDDDCTRL_DISABLE_FET |
795                 POWER_VDDDCTRL_ENABLE_LINREG |
796                 POWER_VDDDCTRL_DISABLE_STEPPING);
797
798         clrbits_le32(&power_regs->hw_power_vddactrl,
799                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
800                 POWER_VDDACTRL_DISABLE_STEPPING);
801
802         clrbits_le32(&power_regs->hw_power_vddioctrl,
803                 POWER_VDDIOCTRL_DISABLE_FET |
804                 POWER_VDDIOCTRL_DISABLE_STEPPING);
805
806         /* Stop 5V detection */
807         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
808                 &power_regs->hw_power_5vctrl_clr);
809 }
810
811 static void mxs_init_batt_bo(void)
812 {
813         clrsetbits_le32(&power_regs->hw_power_battmonitor,
814                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
815                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
816
817         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
818         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
819 }
820
821 /**
822  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
823  *
824  * This function turns off the VDDD linear regulator and therefore makes
825  * the VDDD rail be supplied only by the DC-DC converter.
826  */
827 static void mxs_switch_vddd_to_dcdc_source(void)
828 {
829         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
830                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
831                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
832
833         clrbits_le32(&power_regs->hw_power_vdddctrl,
834                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
835                 POWER_VDDDCTRL_DISABLE_STEPPING);
836 }
837
838 /**
839  * mxs_power_configure_power_source() - Configure power block source
840  *
841  * This function is the core of the power configuration logic. The function
842  * selects the power block input source and configures the whole power block
843  * accordingly. After the configuration is complete and the system is stable
844  * again, the function switches the CPU clock source back to PLL. Finally,
845  * the function switches the voltage rails to DC-DC converter.
846  */
847 static void mxs_power_configure_power_source(void)
848 {
849         struct mxs_lradc_regs *lradc_regs =
850                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
851
852         mxs_src_power_init();
853
854         if (!fixed_batt_supply) {
855                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
856                         if (mxs_is_batt_ready()) {
857                                 /* 5V source detected, good battery detected. */
858                                 mxs_batt_boot();
859                         } else {
860                                 if (!mxs_is_batt_good()) {
861                                         /* 5V source detected, bad battery detected. */
862                                         writel(LRADC_CONVERSION_AUTOMATIC,
863                                                 &lradc_regs->hw_lradc_conversion_clr);
864                                         clrbits_le32(&power_regs->hw_power_battmonitor,
865                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
866                                 }
867                                 mxs_5v_boot();
868                         }
869                 } else {
870                         /* 5V not detected, booting from battery. */
871                         mxs_batt_boot();
872                 }
873         } else {
874                 mxs_fixed_batt_boot();
875         }
876
877         mxs_power_clock2pll();
878
879         mxs_init_batt_bo();
880
881         mxs_switch_vddd_to_dcdc_source();
882
883 #ifdef CONFIG_SOC_MX23
884         /* Fire up the VDDMEM LinReg now that we're all set. */
885         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
886                 &power_regs->hw_power_vddmemctrl);
887 #endif
888 }
889
890 /**
891  * mxs_enable_output_rail_protection() - Enable power rail protection
892  *
893  * This function enables overload protection on the power rails. This is
894  * triggered if the power rails' voltage drops rapidly due to overload and
895  * in such case, the supply to the powerrail is cut-off, protecting the
896  * CPU from damage. Note that under such condition, the system will likely
897  * crash or misbehave.
898  */
899 static void mxs_enable_output_rail_protection(void)
900 {
901         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
902                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
903
904         setbits_le32(&power_regs->hw_power_vdddctrl,
905                         POWER_VDDDCTRL_PWDN_BRNOUT);
906
907         setbits_le32(&power_regs->hw_power_vddactrl,
908                         POWER_VDDACTRL_PWDN_BRNOUT);
909
910         setbits_le32(&power_regs->hw_power_vddioctrl,
911                         POWER_VDDIOCTRL_PWDN_BRNOUT);
912 }
913
914 /**
915  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
916  *
917  * This function tests if the VDDIO rail is supplied by linear regulator
918  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
919  * returns 0 if powered by the DC-DC converter.
920  */
921 static int mxs_get_vddio_power_source_off(void)
922 {
923         uint32_t tmp;
924
925         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
926                 !(readl(&power_regs->hw_power_5vctrl) &
927                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
928
929                 tmp = readl(&power_regs->hw_power_vddioctrl);
930                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
931                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
932                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
933                                 return 1;
934                         }
935                 }
936
937                 if (!(readl(&power_regs->hw_power_5vctrl) &
938                         POWER_5VCTRL_ENABLE_DCDC)) {
939                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
940                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
941                                 return 1;
942                         }
943                 }
944         }
945
946         return 0;
947 }
948
949 /**
950  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
951  *
952  * This function tests if the VDDD rail is supplied by linear regulator
953  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
954  * returns 0 if powered by the DC-DC converter.
955  */
956 static int mxs_get_vddd_power_source_off(void)
957 {
958         uint32_t tmp;
959
960         tmp = readl(&power_regs->hw_power_vdddctrl);
961         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
962                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
963                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
964                         return 1;
965                 }
966         }
967
968         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
969                 if (!(readl(&power_regs->hw_power_5vctrl) &
970                         POWER_5VCTRL_ENABLE_DCDC)) {
971                         return 1;
972                 }
973         }
974
975         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
976                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
977                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
978                         return 1;
979                 }
980         }
981
982         return 0;
983 }
984
985 static int mxs_get_vdda_power_source_off(void)
986 {
987         uint32_t tmp;
988
989         tmp = readl(&power_regs->hw_power_vddactrl);
990         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
991                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
992                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
993                         return 1;
994                 }
995         }
996
997         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
998                 if (!(readl(&power_regs->hw_power_5vctrl) &
999                         POWER_5VCTRL_ENABLE_DCDC)) {
1000                         return 1;
1001                 }
1002         }
1003
1004         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1005                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1006                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1007                         return 1;
1008                 }
1009         }
1010
1011         return 0;
1012 }
1013
1014 struct mxs_vddx_cfg {
1015         uint32_t                *reg;
1016         uint8_t                 step_mV;
1017         uint16_t                lowest_mV;
1018         uint16_t                highest_mV;
1019         int                     (*powered_by_linreg)(void);
1020         uint32_t                trg_mask;
1021         uint32_t                bo_irq;
1022         uint32_t                bo_enirq;
1023         uint32_t                bo_offset_mask;
1024         uint32_t                bo_offset_offset;
1025         uint16_t                bo_min_mV;
1026         uint16_t                bo_max_mV;
1027 };
1028
1029 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1030
1031 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1032         .reg                    = POWER_REG(hw_power_vddioctrl),
1033 #if defined(CONFIG_SOC_MX23)
1034         .step_mV                = 25,
1035 #else
1036         .step_mV                = 50,
1037 #endif
1038         .lowest_mV              = 2800,
1039         .highest_mV             = 3600,
1040         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1041         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1042         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1043         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1044         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1045         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1046         .bo_min_mV              = 2700,
1047         .bo_max_mV              = 3475,
1048 };
1049
1050 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1051         .reg                    = POWER_REG(hw_power_vdddctrl),
1052         .step_mV                = 25,
1053         .lowest_mV              = 800,
1054         .highest_mV             = 1575,
1055         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1056         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1057         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1058         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1059         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1060         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1061         .bo_min_mV              = 800,
1062         .bo_max_mV              = 1475,
1063 };
1064
1065 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1066         .reg                    = POWER_REG(hw_power_vddactrl),
1067         .step_mV                = 25,
1068         .lowest_mV              = 1800,
1069         .highest_mV             = 3600,
1070         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1071         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1072         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1073         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1074         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1075         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1076         .bo_min_mV              = 1400,
1077         .bo_max_mV              = 2175,
1078 };
1079
1080 #ifdef CONFIG_SOC_MX23
1081 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1082         .reg                    = POWER_REG(hw_power_vddmemctrl),
1083         .step_mV                = 50,
1084         .lowest_mV              = 1500,
1085         .highest_mV             = 1700,
1086         .powered_by_linreg      = NULL,
1087         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1088         .bo_irq                 = 0,
1089         .bo_enirq               = 0,
1090         .bo_offset_mask         = 0,
1091         .bo_offset_offset       = 0,
1092 };
1093 #endif
1094
1095 /**
1096  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1097  * @cfg:                Configuration data of the DC-DC converter rail
1098  * @new_target:         New target voltage of the DC-DC converter rail
1099  * @new_brownout:       New brownout trigger voltage
1100  *
1101  * This function configures the output voltage on the DC-DC converter rail.
1102  * The rail is selected by the @cfg argument. The new voltage target is
1103  * selected by the @new_target and the voltage is specified in mV. The
1104  * new brownout value is selected by the @new_brownout argument and the
1105  * value is also in mV.
1106  */
1107 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1108                                 uint32_t new_target, uint32_t bo_offset)
1109 {
1110         uint32_t cur_target, diff, bo_int = 0;
1111         int powered_by_linreg = 0;
1112         int adjust_up;
1113
1114         if (new_target < cfg->lowest_mV) {
1115                 new_target = cfg->lowest_mV;
1116         }
1117         if (new_target > cfg->highest_mV) {
1118                 new_target = cfg->highest_mV;
1119         }
1120
1121         if (new_target - bo_offset < cfg->bo_min_mV) {
1122                 bo_offset = new_target - cfg->bo_min_mV;
1123         } else if (new_target - bo_offset > cfg->bo_max_mV) {
1124                 bo_offset = new_target - cfg->bo_max_mV;
1125         }
1126
1127         bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1128
1129         cur_target = readl(cfg->reg);
1130         cur_target &= cfg->trg_mask;
1131         cur_target *= cfg->step_mV;
1132         cur_target += cfg->lowest_mV;
1133
1134         adjust_up = new_target > cur_target;
1135         if (cfg->powered_by_linreg)
1136                 powered_by_linreg = cfg->powered_by_linreg();
1137
1138         if (adjust_up && cfg->bo_irq) {
1139                 if (powered_by_linreg) {
1140                         bo_int = readl(&power_regs->hw_power_ctrl);
1141                         writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1142                 }
1143                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1144         }
1145
1146         do {
1147                 if (abs(new_target - cur_target) > 100) {
1148                         if (adjust_up)
1149                                 diff = cur_target + 100;
1150                         else
1151                                 diff = cur_target - 100;
1152                 } else {
1153                         diff = new_target;
1154                 }
1155
1156                 diff -= cfg->lowest_mV;
1157                 diff /= cfg->step_mV;
1158
1159                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1160
1161                 if (powered_by_linreg ||
1162                         (readl(&power_regs->hw_power_sts) &
1163                                 POWER_STS_VDD5V_GT_VDDIO)) {
1164                         early_delay(500);
1165                 } else {
1166                         while (!(readl(&power_regs->hw_power_sts) &
1167                                         POWER_STS_DC_OK)) {
1168
1169                         }
1170                 }
1171
1172                 cur_target = readl(cfg->reg);
1173                 cur_target &= cfg->trg_mask;
1174                 cur_target *= cfg->step_mV;
1175                 cur_target += cfg->lowest_mV;
1176         } while (new_target > cur_target);
1177
1178         if (cfg->bo_irq) {
1179                 if (adjust_up && powered_by_linreg) {
1180                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1181                         if (bo_int & cfg->bo_enirq)
1182                                 writel(cfg->bo_enirq,
1183                                         &power_regs->hw_power_ctrl_set);
1184                 }
1185
1186                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1187                                 bo_offset << cfg->bo_offset_offset);
1188         }
1189 }
1190
1191 /**
1192  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1193  *
1194  * This function starts and configures the LRADC block. This allows the
1195  * power initialization code to measure battery voltage and based on this
1196  * knowledge, decide whether to boot at all, boot from battery or boot
1197  * from 5V input.
1198  */
1199 static void mxs_setup_batt_detect(void)
1200 {
1201         mxs_lradc_init();
1202         mxs_lradc_enable_batt_measurement();
1203         early_delay(10);
1204 }
1205
1206 /**
1207  * mxs_ungate_power() - Ungate the POWER block
1208  *
1209  * This function ungates clock to the power block. In case the power block
1210  * was still gated at this point, it will not be possible to configure the
1211  * block and therefore the power initialization would fail. This function
1212  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1213  */
1214 static void mxs_ungate_power(void)
1215 {
1216 #ifdef CONFIG_SOC_MX23
1217         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1218 #endif
1219 }
1220
1221 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1222 #define auto_restart 1
1223 #else
1224 #define auto_restart 0
1225 #endif
1226
1227 /**
1228  * mxs_power_init() - The power block init main function
1229  *
1230  * This function calls all the power block initialization functions in
1231  * proper sequence to start the power block.
1232  */
1233 void mxs_power_init(void)
1234 {
1235         mxs_ungate_power();
1236
1237         mxs_power_clock2xtal();
1238         if (mxs_power_set_auto_restart(auto_restart)) {
1239                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1240         }
1241         mxs_power_set_linreg();
1242
1243         if (!fixed_batt_supply) {
1244                 mxs_power_setup_5v_detect();
1245                 mxs_setup_batt_detect();
1246         }
1247
1248         mxs_power_configure_power_source();
1249         mxs_enable_output_rail_protection();
1250
1251         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1252         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1253         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1254 #ifdef CONFIG_SOC_MX23
1255         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1256
1257         setbits_le32(&power_regs->hw_power_vddmemctrl,
1258                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1259         early_delay(500);
1260         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1261                 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
1262 #else
1263         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1264                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1265 #endif
1266         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1267                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1268                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1269                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1270         if (!fixed_batt_supply)
1271                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1272                         &power_regs->hw_power_5vctrl_set);
1273 }
1274
1275 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1276 /**
1277  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1278  *
1279  * This function waits until the power-switch was pressed to start booting
1280  * the board.
1281  */
1282 void mxs_power_wait_pswitch(void)
1283 {
1284         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1285                 ;
1286 }
1287 #endif