arch/arm/cpu/armv7/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <spl.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/omap.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/io.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  40 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  41
  42 static const struct gpio_bank gpio_bank_am33xx[4] = {
  43         { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
  44         { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
  45         { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
  46         { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
  47 };
  48
  49 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  50
  51 /* MII mode defines */
  52 #define MII_MODE_ENABLE         0x0
  53 #define RGMII_MODE_ENABLE       0xA
  54
  55 /* GPIO that controls power to DDR on EVM-SK */
  56 #define GPIO_DDR_VTT_EN         7
  57
  58 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  59
  60 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  61
  62 static inline int board_is_bone(void)
  63 {
  64         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
  65 }
  66
  67 static inline int board_is_bone_lt(void)
  68 {
  69         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
  70 }
  71
  72 static inline int board_is_evm_sk(void)
  73 {
  74         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
  75 }
  76
  77 /*
  78  * Read header information from EEPROM into global structure.
  79  */
  80 static int read_eeprom(void)
  81 {
  82         /* Check if baseboard eeprom is available */
  83         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  84                 puts("Could not probe the EEPROM; something fundamentally "
  85                         "wrong on the I2C bus.\n");
  86                 return -ENODEV;
  87         }
  88
  89         /* read the eeprom using i2c */
  90         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  91                                                         sizeof(header))) {
  92                 puts("Could not read the EEPROM; something fundamentally"
  93                         " wrong on the I2C bus.\n");
  94                 return -EIO;
  95         }
  96
  97         if (header.magic != 0xEE3355AA) {
  98                 /*
  99                  * read the eeprom using i2c again,
 100                  * but use only a 1 byte address
 101                  */
 102                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
 103                                         (uchar *)&header, sizeof(header))) {
 104                         puts("Could not read the EEPROM; something "
 105                                 "fundamentally wrong on the I2C bus.\n");
 106                         return -EIO;
 107                 }
 108
 109                 if (header.magic != 0xEE3355AA) {
 110                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 111                                         header.magic);
 112                         return -EINVAL;
 113                 }
 114         }
 115
 116         return 0;
 117 }
 118
 119 /* UART Defines */
 120 #ifdef CONFIG_SPL_BUILD
 121 #define UART_RESET              (0x1 << 1)
 122 #define UART_CLK_RUNNING_MASK   0x1
 123 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 124 #endif
 125
 126 /*
 127  * Determine what type of DDR we have.
 128  */
 129 static short inline board_memory_type(void)
 130 {
 131         /* The following boards are known to use DDR3. */
 132         if (board_is_evm_sk() || board_is_bone_lt())
 133                 return EMIF_REG_SDRAM_TYPE_DDR3;
 134
 135         return EMIF_REG_SDRAM_TYPE_DDR2;
 136 }
 137
 138 /*
 139  * early system init of muxing and clocks.
 140  */
 141 void s_init(void)
 142 {
 143         /* WDT1 is already running when the bootloader gets control
 144          * Disable it to avoid "random" resets
 145          */
 146         writel(0xAAAA, &wdtimer->wdtwspr);
 147         while (readl(&wdtimer->wdtwwps) != 0x0)
 148                 ;
 149         writel(0x5555, &wdtimer->wdtwspr);
 150         while (readl(&wdtimer->wdtwwps) != 0x0)
 151                 ;
 152
 153 #ifdef CONFIG_SPL_BUILD
 154         /* Setup the PLLs and the clocks for the peripherals */
 155         pll_init();
 156
 157         /* UART softreset */
 158         u32 regVal;
 159
 160         enable_uart0_pin_mux();
 161
 162         regVal = readl(&uart_base->uartsyscfg);
 163         regVal |= UART_RESET;
 164         writel(regVal, &uart_base->uartsyscfg);
 165         while ((readl(&uart_base->uartsyssts) &
 166                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 167                 ;
 168
 169         /* Disable smart idle */
 170         regVal = readl(&uart_base->uartsyscfg);
 171         regVal |= UART_SMART_IDLE_EN;
 172         writel(regVal, &uart_base->uartsyscfg);
 173
 174         gd = &gdata;
 175
 176         preloader_console_init();
 177
 178         /* Initalize the board header */
 179         enable_i2c0_pin_mux();
 180         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 181         if (read_eeprom() < 0)
 182                 puts("Could not get board ID.\n");
 183
 184         enable_board_pin_mux(&header);
 185         if (board_is_evm_sk()) {
 186                 /*
 187                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 188                  * This is safe enough to do on older revs.
 189                  */
 190                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 191                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 192         }
 193
 194         config_ddr(board_memory_type());
 195 #endif
 196 }
 197
 198 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 199 int board_mmc_init(bd_t *bis)
 200 {
 201         int ret;
 202
 203         ret = omap_mmc_init(0, 0, 0);
 204         if (ret)
 205                 return ret;
 206
 207         return omap_mmc_init(1, 0, 0);
 208 }
 209 #endif
 210
 211 void setup_clocks_for_console(void)
 212 {
 213         /* Not yet implemented */
 214         return;
 215 }
 216
 217 /*
 218  * Basic board specific setup.  Pinmux has been handled already.
 219  */
 220 int board_init(void)
 221 {
 222         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 223         if (read_eeprom() < 0)
 224                 puts("Could not get board ID.\n");
 225
 226         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 227
 228         return 0;
 229 }
 230
 231 #ifdef CONFIG_DRIVER_TI_CPSW
 232 static void cpsw_control(int enabled)
 233 {
 234         /* VTP can be added here */
 235
 236         return;
 237 }
 238
 239 static struct cpsw_slave_data cpsw_slaves[] = {
 240         {
 241                 .slave_reg_ofs  = 0x208,
 242                 .sliver_reg_ofs = 0xd80,
 243                 .phy_id         = 0,
 244         },
 245         {
 246                 .slave_reg_ofs  = 0x308,
 247                 .sliver_reg_ofs = 0xdc0,
 248                 .phy_id         = 1,
 249         },
 250 };
 251
 252 static struct cpsw_platform_data cpsw_data = {
 253         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 254         .cpsw_base              = AM335X_CPSW_BASE,
 255         .mdio_div               = 0xff,
 256         .channels               = 8,
 257         .cpdma_reg_ofs          = 0x800,
 258         .slaves                 = 1,
 259         .slave_data             = cpsw_slaves,
 260         .ale_reg_ofs            = 0xd00,
 261         .ale_entries            = 1024,
 262         .host_port_reg_ofs      = 0x108,
 263         .hw_stats_reg_ofs       = 0x900,
 264         .mac_control            = (1 << 5),
 265         .control                = cpsw_control,
 266         .host_port_num          = 0,
 267         .version                = CPSW_CTRL_VERSION_2,
 268 };
 269
 270 int board_eth_init(bd_t *bis)
 271 {
 272         uint8_t mac_addr[6];
 273         uint32_t mac_hi, mac_lo;
 274
 275         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 276                 debug("<ethaddr> not set. Reading from E-fuse\n");
 277                 /* try reading mac address from efuse */
 278                 mac_lo = readl(&cdev->macid0l);
 279                 mac_hi = readl(&cdev->macid0h);
 280                 mac_addr[0] = mac_hi & 0xFF;
 281                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 282                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 283                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 284                 mac_addr[4] = mac_lo & 0xFF;
 285                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 286
 287                 if (is_valid_ether_addr(mac_addr))
 288                         eth_setenv_enetaddr("ethaddr", mac_addr);
 289                 else
 290                         return -1;
 291         }
 292
 293         if (board_is_bone() || board_is_bone_lt()) {
 294                 writel(MII_MODE_ENABLE, &cdev->miisel);
 295                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 296                                 PHY_INTERFACE_MODE_MII;
 297         } else {
 298                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 299                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 300                                 PHY_INTERFACE_MODE_RGMII;
 301         }
 302
 303         return cpsw_register(&cpsw_data);
 304 }
 305 #endif