arch/arm/cpu/armv7/am33xx/clock_am43xx.c

   1 /*
   2  * clock_am43xx.c
   3  *
   4  * clocks for AM43XX based boards
   5  * Derived from AM33XX based boards
   6  *
   7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/io.h>
  18
  19 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  20 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
  21
  22 const struct dpll_regs dpll_mpu_regs = {
  23         .cm_clkmode_dpll        = CM_WKUP + 0x560,
  24         .cm_idlest_dpll         = CM_WKUP + 0x564,
  25         .cm_clksel_dpll         = CM_WKUP + 0x56c,
  26         .cm_div_m2_dpll         = CM_WKUP + 0x570,
  27 };
  28
  29 const struct dpll_regs dpll_core_regs = {
  30         .cm_clkmode_dpll        = CM_WKUP + 0x520,
  31         .cm_idlest_dpll         = CM_WKUP + 0x524,
  32         .cm_clksel_dpll         = CM_WKUP + 0x52C,
  33         .cm_div_m4_dpll         = CM_WKUP + 0x538,
  34         .cm_div_m5_dpll         = CM_WKUP + 0x53C,
  35         .cm_div_m6_dpll         = CM_WKUP + 0x540,
  36 };
  37
  38 const struct dpll_regs dpll_per_regs = {
  39         .cm_clkmode_dpll        = CM_WKUP + 0x5E0,
  40         .cm_idlest_dpll         = CM_WKUP + 0x5E4,
  41         .cm_clksel_dpll         = CM_WKUP + 0x5EC,
  42         .cm_div_m2_dpll         = CM_WKUP + 0x5F0,
  43 };
  44
  45 const struct dpll_regs dpll_ddr_regs = {
  46         .cm_clkmode_dpll        = CM_WKUP + 0x5A0,
  47         .cm_idlest_dpll         = CM_WKUP + 0x5A4,
  48         .cm_clksel_dpll         = CM_WKUP + 0x5AC,
  49         .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
  50 };
  51
  52 const struct dpll_params dpll_mpu = {
  53                 -1, -1, -1, -1, -1, -1, -1};
  54 const struct dpll_params dpll_core = {
  55                 -1, -1, -1, -1, -1, -1, -1};
  56 const struct dpll_params dpll_per = {
  57                 -1, -1, -1, -1, -1, -1, -1};
  58
  59 void setup_clocks_for_console(void)
  60 {
  61         /* Do not add any spl_debug prints in this function */
  62         clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  63                         CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  64                         CD_CLKCTRL_CLKTRCTRL_SHIFT);
  65
  66         /* Enable UART0 */
  67         clrsetbits_le32(&cmwkup->wkup_uart0ctrl,
  68                         MODULE_CLKCTRL_MODULEMODE_MASK,
  69                         MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  70                         MODULE_CLKCTRL_MODULEMODE_SHIFT);
  71 }
  72
  73 void enable_basic_clocks(void)
  74 {
  75         u32 *const clk_domains[] = {
  76                 &cmper->l3clkstctrl,
  77                 &cmper->l3sclkstctrl,
  78                 &cmper->l4lsclkstctrl,
  79                 &cmwkup->wkclkstctrl,
  80                 &cmper->emifclkstctrl,
  81                 0
  82         };
  83
  84         u32 *const clk_modules_explicit_en[] = {
  85                 &cmper->l3clkctrl,
  86                 &cmper->l4lsclkctrl,
  87                 &cmper->l4fwclkctrl,
  88                 &cmwkup->wkl4wkclkctrl,
  89                 &cmper->l3instrclkctrl,
  90                 &cmper->l4hsclkctrl,
  91                 &cmwkup->wkgpio0clkctrl,
  92                 &cmwkup->wkctrlclkctrl,
  93                 &cmper->timer2clkctrl,
  94                 &cmper->gpmcclkctrl,
  95                 &cmper->elmclkctrl,
  96                 &cmper->mmc0clkctrl,
  97                 &cmper->mmc1clkctrl,
  98                 &cmwkup->wkup_i2c0ctrl,
  99                 &cmper->gpio1clkctrl,
 100                 &cmper->gpio2clkctrl,
 101                 &cmper->gpio3clkctrl,
 102                 &cmper->i2c1clkctrl,
 103                 &cmper->emiffwclkctrl,
 104                 &cmper->emifclkctrl,
 105                 &cmper->otfaemifclkctrl,
 106                 0
 107         };
 108
 109         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 110 }