2c67c322cae5ee25b61c868cfeafc0f5098919b4
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / emif4.c
1 /*
2  * emif4.c
3  *
4  * AM33XX emif4 configuration file
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/ddr_defs.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/io.h>
18 #include <asm/emif.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 int dram_init(void)
23 {
24         /* dram_init must store complete ramsize in gd->ram_size */
25         gd->ram_size = get_ram_size(
26                         (void *)CONFIG_SYS_SDRAM_BASE,
27                         CONFIG_MAX_RAM_BANK_SIZE);
28         return 0;
29 }
30
31 void dram_init_banksize(void)
32 {
33         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
34         gd->bd->bi_dram[0].size = gd->ram_size;
35 }
36
37
38 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
39 #ifdef CONFIG_TI81XX
40 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
41                                 (struct dmm_lisa_map_regs *)DMM_BASE;
42 #endif
43 #ifndef CONFIG_TI816X
44 static struct vtp_reg *vtpreg[2] = {
45                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
46                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
47 #endif
48 #ifdef CONFIG_AM33XX
49 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
50 #endif
51 #ifdef CONFIG_AM43XX
52 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
53 static struct cm_device_inst *cm_device =
54                                 (struct cm_device_inst *)CM_DEVICE_INST;
55 #endif
56
57 #ifdef CONFIG_TI81XX
58 void config_dmm(const struct dmm_lisa_map_regs *regs)
59 {
60         enable_dmm_clocks();
61
62         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
63         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
64         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
65         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
66
67         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
68         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
69         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
70         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
71 }
72 #endif
73
74 #ifndef CONFIG_TI816X
75 static void config_vtp(int nr)
76 {
77         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
78                         &vtpreg[nr]->vtp0ctrlreg);
79         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
80                         &vtpreg[nr]->vtp0ctrlreg);
81         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
82                         &vtpreg[nr]->vtp0ctrlreg);
83
84         /* Poll for READY */
85         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
86                         VTP_CTRL_READY)
87                 ;
88 }
89 #endif
90
91 void __weak ddr_pll_config(unsigned int ddrpll_m)
92 {
93 }
94
95 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
96                 const struct ddr_data *data, const struct cmd_control *ctrl,
97                 const struct emif_regs *regs, int nr)
98 {
99         ddr_pll_config(pll);
100 #ifndef CONFIG_TI816X
101         config_vtp(nr);
102 #endif
103         config_cmd_ctrl(ctrl, nr);
104
105         config_ddr_data(data, nr);
106 #ifdef CONFIG_AM33XX
107         config_io_ctrl(ioregs);
108
109         /* Set CKE to be controlled by EMIF/DDR PHY */
110         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
111 #endif
112 #ifdef CONFIG_AM43XX
113         writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
114         while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
115                 ;
116         writel(0x80000000, &ddrctrl->ddrioctrl);
117
118         config_io_ctrl(ioregs);
119
120         /* Set CKE to be controlled by EMIF/DDR PHY */
121         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
122 #endif
123
124         /* Program EMIF instance */
125         config_ddr_phy(regs, nr);
126         set_sdram_timings(regs, nr);
127         if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
128                 config_sdram_emif4d5(regs, nr);
129         else
130                 config_sdram(regs, nr);
131 }
132 #endif