arm:am33xx: Make dram_init call sdram_init() in some contexts
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / emif4.c
1 /*
2  * emif4.c
3  *
4  * AM33XX emif4 configuration file
5  *
6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #include <common.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/ddr_defs.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/io.h>
18 #include <asm/emif.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 int dram_init(void)
23 {
24 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
25         sdram_init();
26 #endif
27
28         /* dram_init must store complete ramsize in gd->ram_size */
29         gd->ram_size = get_ram_size(
30                         (void *)CONFIG_SYS_SDRAM_BASE,
31                         CONFIG_MAX_RAM_BANK_SIZE);
32         return 0;
33 }
34
35 void dram_init_banksize(void)
36 {
37         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
38         gd->bd->bi_dram[0].size = gd->ram_size;
39 }
40
41
42 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
43 #ifdef CONFIG_TI81XX
44 static struct dmm_lisa_map_regs *hw_lisa_map_regs =
45                                 (struct dmm_lisa_map_regs *)DMM_BASE;
46 #endif
47 #ifndef CONFIG_TI816X
48 static struct vtp_reg *vtpreg[2] = {
49                                 (struct vtp_reg *)VTP0_CTRL_ADDR,
50                                 (struct vtp_reg *)VTP1_CTRL_ADDR};
51 #endif
52 #ifdef CONFIG_AM33XX
53 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
54 #endif
55 #ifdef CONFIG_AM43XX
56 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
57 static struct cm_device_inst *cm_device =
58                                 (struct cm_device_inst *)CM_DEVICE_INST;
59 #endif
60
61 #ifdef CONFIG_TI81XX
62 void config_dmm(const struct dmm_lisa_map_regs *regs)
63 {
64         enable_dmm_clocks();
65
66         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
67         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
68         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
69         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
70
71         writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
72         writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
73         writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
74         writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
75 }
76 #endif
77
78 #ifndef CONFIG_TI816X
79 static void config_vtp(int nr)
80 {
81         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
82                         &vtpreg[nr]->vtp0ctrlreg);
83         writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
84                         &vtpreg[nr]->vtp0ctrlreg);
85         writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
86                         &vtpreg[nr]->vtp0ctrlreg);
87
88         /* Poll for READY */
89         while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
90                         VTP_CTRL_READY)
91                 ;
92 }
93 #endif
94
95 void __weak ddr_pll_config(unsigned int ddrpll_m)
96 {
97 }
98
99 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
100                 const struct ddr_data *data, const struct cmd_control *ctrl,
101                 const struct emif_regs *regs, int nr)
102 {
103         ddr_pll_config(pll);
104 #ifndef CONFIG_TI816X
105         config_vtp(nr);
106 #endif
107         config_cmd_ctrl(ctrl, nr);
108
109         config_ddr_data(data, nr);
110 #ifdef CONFIG_AM33XX
111         config_io_ctrl(ioregs);
112
113         /* Set CKE to be controlled by EMIF/DDR PHY */
114         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
115 #endif
116 #ifdef CONFIG_AM43XX
117         writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
118         while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
119                 ;
120         writel(0x80000000, &ddrctrl->ddrioctrl);
121
122         config_io_ctrl(ioregs);
123
124         /* Set CKE to be controlled by EMIF/DDR PHY */
125         writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
126 #endif
127
128         /* Program EMIF instance */
129         config_ddr_phy(regs, nr);
130         set_sdram_timings(regs, nr);
131         if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
132                 config_sdram_emif4d5(regs, nr);
133         else
134                 config_sdram(regs, nr);
135 }
136 #endif