arch/arm/cpu/armv7/am33xx/emif4.c

   1 /*
   2  * emif4.c
   3  *
   4  * AM33XX emif4 configuration file
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/ddr_defs.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <asm/io.h>
  26 #include <asm/emif.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
  31 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
  32 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
  33
  34 int dram_init(void)
  35 {
  36         /* dram_init must store complete ramsize in gd->ram_size */
  37         gd->ram_size = get_ram_size(
  38                         (void *)CONFIG_SYS_SDRAM_BASE,
  39                         CONFIG_MAX_RAM_BANK_SIZE);
  40         return 0;
  41 }
  42
  43 void dram_init_banksize(void)
  44 {
  45         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  46         gd->bd->bi_dram[0].size = gd->ram_size;
  47 }
  48
  49
  50 #ifdef CONFIG_SPL_BUILD
  51 static const struct ddr_data ddr2_data = {
  52         .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
  53                                 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
  54         .datardsratio1 = DDR2_RD_DQS>>2,
  55         .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
  56                                 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
  57         .datawdsratio1 = DDR2_WR_DQS>>2,
  58         .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
  59                                 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
  60         .datawiratio1 = DDR2_PHY_WRLVL>>2,
  61         .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
  62                                 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
  63         .datagiratio1 = DDR2_PHY_GATELVL>>2,
  64         .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
  65                                 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
  66         .datafwsratio1 = DDR2_PHY_FIFO_WE>>2,
  67         .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
  68                                 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
  69         .datawrsratio1 = DDR2_PHY_WR_DATA>>2,
  70         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  71 };
  72
  73 static const struct cmd_control ddr2_cmd_ctrl_data = {
  74         .cmd0csratio = DDR2_RATIO,
  75         .cmd0csforce = CMD_FORCE,
  76         .cmd0csdelay = CMD_DELAY,
  77         .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
  78         .cmd0iclkout = DDR2_INVERT_CLKOUT,
  79
  80         .cmd1csratio = DDR2_RATIO,
  81         .cmd1csforce = CMD_FORCE,
  82         .cmd1csdelay = CMD_DELAY,
  83         .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
  84         .cmd1iclkout = DDR2_INVERT_CLKOUT,
  85
  86         .cmd2csratio = DDR2_RATIO,
  87         .cmd2csforce = CMD_FORCE,
  88         .cmd2csdelay = CMD_DELAY,
  89         .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
  90         .cmd2iclkout = DDR2_INVERT_CLKOUT,
  91 };
  92
  93 static void config_vtp(void)
  94 {
  95         writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
  96                         &vtpreg->vtp0ctrlreg);
  97         writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
  98                         &vtpreg->vtp0ctrlreg);
  99         writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
 100                         &vtpreg->vtp0ctrlreg);
 101
 102         /* Poll for READY */
 103         while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
 104                         VTP_CTRL_READY)
 105                 ;
 106 }
 107
 108 static void config_emif_ddr2(void)
 109 {
 110         int ret;
 111         struct sdram_config cfg;
 112         struct sdram_timing tmg;
 113         struct ddr_phy_control phyc;
 114
 115         /* Program EMIF0 CFG Registers */
 116         phyc.reg = DDR2_EMIF_READ_LATENCY;
 117         phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
 118         phyc.reg2 = DDR2_EMIF_READ_LATENCY;
 119
 120         tmg.time1 = DDR2_EMIF_TIM1;
 121         tmg.time1_sh = DDR2_EMIF_TIM1;
 122         tmg.time2 = DDR2_EMIF_TIM2;
 123         tmg.time2_sh = DDR2_EMIF_TIM2;
 124         tmg.time3 = DDR2_EMIF_TIM3;
 125         tmg.time3_sh = DDR2_EMIF_TIM3;
 126
 127         cfg.sdrcr = DDR2_EMIF_SDCFG;
 128         cfg.sdrcr2 = DDR2_EMIF_SDCFG;
 129         cfg.refresh = DDR2_EMIF_SDREF;
 130         cfg.refresh_sh = DDR2_EMIF_SDREF;
 131
 132         /* Program EMIF instance */
 133         ret = config_ddr_phy(&phyc);
 134         if (ret < 0)
 135                 printf("Couldn't configure phyc\n");
 136
 137
 138         ret = set_sdram_timings(&tmg);
 139         if (ret < 0)
 140                 printf("Couldn't configure timings\n");
 141
 142         ret = config_sdram(&cfg);
 143         if (ret < 0)
 144                 printf("Couldn't configure SDRAM\n");
 145 }
 146
 147 void config_ddr(short ddr_type)
 148 {
 149         struct ddr_ioctrl ioctrl;
 150
 151         enable_emif_clocks();
 152
 153         if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
 154                 ddr_pll_config(266);
 155                 config_vtp();
 156
 157                 config_cmd_ctrl(&ddr2_cmd_ctrl_data);
 158
 159                 config_ddr_data(0, &ddr2_data);
 160                 config_ddr_data(1, &ddr2_data);
 161
 162                 writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
 163                 writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 164
 165                 ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
 166                 ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
 167                 ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
 168                 ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
 169                 ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
 170
 171                 config_io_ctrl(&ioctrl);
 172
 173                 writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
 174                                 &ddrctrl->ddrioctrl);
 175                 writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
 176                                 &ddrctrl->ddrckectrl);
 177
 178                 config_emif_ddr2();
 179         }
 180 }
 181 #endif