arch/arm/cpu/armv7/am33xx/mem.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Mansoor Ahamed <mansoor.ahamed@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Manikandan Pillai <mani.pillai@ti.com>
  10  *     Richard Woodruff <r-woodruff2@ti.com>
  11  *     Syed Mohammed Khasim <khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/mem.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <command.h>
  22
  23 struct gpmc *gpmc_cfg;
  24
  25
  26 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  27                         u32 size)
  28 {
  29         writel(0, &cs->config7);
  30         sdelay(1000);
  31         /* Delay for settling */
  32         writel(gpmc_config[0], &cs->config1);
  33         writel(gpmc_config[1], &cs->config2);
  34         writel(gpmc_config[2], &cs->config3);
  35         writel(gpmc_config[3], &cs->config4);
  36         writel(gpmc_config[4], &cs->config5);
  37         writel(gpmc_config[5], &cs->config6);
  38         /* Enable the config */
  39         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  40                 (1 << 6)), &cs->config7);
  41         sdelay(2000);
  42 }
  43
  44 /*****************************************************
  45  * gpmc_init(): init gpmc bus
  46  * Init GPMC for x16, MuxMode (SDRAM in x32).
  47  * This code can only be executed from SRAM or SDRAM.
  48  *****************************************************/
  49 void gpmc_init(void)
  50 {
  51         /* putting a blanket check on GPMC based on ZeBu for now */
  52         gpmc_cfg = (struct gpmc *)GPMC_BASE;
  53 #if defined(CONFIG_NOR)
  54 /* configure GPMC for NOR */
  55         const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
  56                                                 STNOR_GPMC_CONFIG2,
  57                                                 STNOR_GPMC_CONFIG3,
  58                                                 STNOR_GPMC_CONFIG4,
  59                                                 STNOR_GPMC_CONFIG5,
  60                                                 STNOR_GPMC_CONFIG6,
  61                                                 STNOR_GPMC_CONFIG7
  62                                                 };
  63         u32 size = GPMC_SIZE_16M;
  64         u32 base = CONFIG_SYS_FLASH_BASE;
  65 #elif defined(CONFIG_NAND)
  66 /* configure GPMC for NAND */
  67         const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
  68                                                 M_NAND_GPMC_CONFIG2,
  69                                                 M_NAND_GPMC_CONFIG3,
  70                                                 M_NAND_GPMC_CONFIG4,
  71                                                 M_NAND_GPMC_CONFIG5,
  72                                                 M_NAND_GPMC_CONFIG6,
  73                                                 0
  74                                                 };
  75         u32 size = GPMC_SIZE_256M;
  76         u32 base = CONFIG_SYS_NAND_BASE;
  77 #else
  78         const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
  79         u32 size = 0;
  80         u32 base = 0;
  81 #endif
  82         /* global settings */
  83         writel(0x00000008, &gpmc_cfg->sysconfig);
  84         writel(0x00000000, &gpmc_cfg->irqstatus);
  85         writel(0x00000000, &gpmc_cfg->irqenable);
  86 #ifdef CONFIG_NOR
  87         writel(0x00000200, &gpmc_cfg->config);
  88 #else
  89         writel(0x00000012, &gpmc_cfg->config);
  90 #endif
  91         /*
  92          * Disable the GPMC0 config set by ROM code
  93          */
  94         writel(0, &gpmc_cfg->cs[0].config7);
  95         sdelay(1000);
  96         /* enable chip-select specific configurations */
  97         enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
  98 }