arch/arm/cpu/armv7/keystone/ddr3.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <asm/arch/hardware.h>
  11 #include <asm/io.h>
  12
  13 void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  14 {
  15         unsigned int tmp;
  16
  17         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  18                  & 0x00000001) != 0x00000001)
  19                 ;
  20
  21         __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  22
  23         tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  24         tmp &= ~(phy_cfg->pgcr1_mask);
  25         tmp |= phy_cfg->pgcr1_val;
  26         __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  27
  28         __raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
  29         __raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
  30         __raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
  31         __raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);
  32
  33         tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  34         tmp &= ~(phy_cfg->dcr_mask);
  35         tmp |= phy_cfg->dcr_val;
  36         __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  37
  38         __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  39         __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  40         __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  41         __raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
  42         __raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
  43         __raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
  44         __raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
  45         __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  46
  47         __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  48         __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  49         __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  50
  51         __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  52         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  53                 ;
  54
  55         __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  56         while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  57                 ;
  58 }
  59
  60 void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  61 {
  62         __raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
  63         __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  64         __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  65         __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  66         __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  67         __raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
  68         __raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
  69 }