keystone: init: enable UART1 to be able use it from kernel
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / keystone / init.c
1 /*
2  * Keystone2: Architecture initialization
3  *
4  * (C) Copyright 2012-2014
5  *     Texas Instruments Incorporated, <www.ti.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <ns16550.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
15
16 void chip_configuration_unlock(void)
17 {
18         __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
19         __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
20 }
21
22 int arch_cpu_init(void)
23 {
24         chip_configuration_unlock();
25         icache_enable();
26
27 #ifdef CONFIG_SOC_K2HK
28         share_all_segments(8);
29         share_all_segments(9);
30         share_all_segments(10); /* QM PDSP */
31         share_all_segments(11); /* PCIE */
32 #endif
33
34         /*
35          * just initialise the COM2 port so that TI specific
36          * UART register PWREMU_MGMT is initialized. Linux UART
37          * driver doesn't handle this.
38          */
39         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
40                      CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
41
42         return 0;
43 }
44
45 void reset_cpu(ulong addr)
46 {
47         volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
48         u32 tmp;
49
50         tmp = *rstctrl & KS2_RSTCTRL_MASK;
51         *rstctrl = tmp | KS2_RSTCTRL_KEY;
52
53         *rstctrl &= KS2_RSTCTRL_SWRST;
54
55         for (;;)
56                 ;
57 }
58
59 void enable_caches(void)
60 {
61 #ifndef CONFIG_SYS_DCACHE_OFF
62         /* Enable D-cache. I-cache is already enabled in start.S */
63         dcache_enable();
64 #endif
65 }