2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #define PLL_LOCK_BIT (1 << 31)
121 static inline int wait_pll_lock(u32 *reg)
126 while (!((val = readl(reg)) & PLL_LOCK_BIT)) {
132 if (!(val & PLL_LOCK_BIT) && !(readl(reg) & PLL_LOCK_BIT))
137 #ifdef CONFIG_MXC_OCOTP
138 void enable_ocotp_clk(unsigned char enable)
142 reg = __raw_readl(&imx_ccm->CCGR2);
144 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
146 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
147 __raw_writel(reg, &imx_ccm->CCGR2);
151 #ifdef CONFIG_NAND_MXS
152 void setup_gpmi_io_clk(u32 cfg)
154 /* Disable clocks per ERR007177 from MX6 errata */
155 clrbits_le32(&imx_ccm->CCGR4,
156 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
158 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
159 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
160 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
164 clrsetbits_le32(&imx_ccm->cs2cdr,
165 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
166 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
167 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
170 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
171 setbits_le32(&imx_ccm->CCGR4,
172 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
173 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
174 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
175 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
176 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
180 void enable_usboh3_clk(unsigned char enable)
184 reg = __raw_readl(&imx_ccm->CCGR6);
186 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
188 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
189 __raw_writel(reg, &imx_ccm->CCGR6);
193 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
194 void enable_enet_clk(unsigned char enable)
198 if (is_cpu_type(MXC_CPU_MX6UL)) {
199 mask = MXC_CCM_CCGR3_ENET_MASK;
200 addr = &imx_ccm->CCGR3;
202 mask = MXC_CCM_CCGR1_ENET_MASK;
203 addr = &imx_ccm->CCGR1;
207 setbits_le32(addr, mask);
209 clrbits_le32(addr, mask);
213 #ifdef CONFIG_MXC_UART
214 void enable_uart_clk(unsigned char enable)
218 if (is_cpu_type(MXC_CPU_MX6UL))
219 mask = MXC_CCM_CCGR5_UART_MASK;
221 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
224 setbits_le32(&imx_ccm->CCGR5, mask);
226 clrbits_le32(&imx_ccm->CCGR5, mask);
231 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
238 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
240 setbits_le32(&imx_ccm->CCGR6, mask);
242 clrbits_le32(&imx_ccm->CCGR6, mask);
248 #ifdef CONFIG_SYS_I2C_MXC
249 /* i2c_num can be from 0 - 3 */
250 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
259 mask = MXC_CCM_CCGR_CG_MASK
260 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
262 reg = __raw_readl(&imx_ccm->CCGR2);
267 __raw_writel(reg, &imx_ccm->CCGR2);
269 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
270 mask = MXC_CCM_CCGR6_I2C4_MASK;
271 addr = &imx_ccm->CCGR6;
273 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
274 addr = &imx_ccm->CCGR1;
276 reg = __raw_readl(addr);
281 __raw_writel(reg, addr);
287 /* spi_num can be from 0 - SPI_MAX_NUM */
288 int enable_spi_clk(unsigned char enable, unsigned spi_num)
293 if (spi_num > SPI_MAX_NUM)
296 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
297 reg = __raw_readl(&imx_ccm->CCGR1);
302 __raw_writel(reg, &imx_ccm->CCGR1);
306 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
312 div = __raw_readl(&anatop->pll_arm);
313 if (div & BM_ANADIG_PLL_ARM_BYPASS)
314 /* Assume the bypass clock is always derived from OSC */
316 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
318 return infreq * div / 2;
320 div = __raw_readl(&anatop->pll_528);
321 if (div & BM_ANADIG_PLL_528_BYPASS)
323 div &= BM_ANADIG_PLL_528_DIV_SELECT;
325 return infreq * (20 + div * 2);
327 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
328 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
330 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
332 return infreq * (20 + div * 2);
334 div = __raw_readl(&anatop->pll_audio);
335 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
337 post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
338 BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
339 post_div = 1 << (2 - post_div);
340 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
342 return lldiv((u64)infreq * div, post_div);
344 div = __raw_readl(&anatop->pll_video);
345 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
347 post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
348 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
349 post_div = 1 << (2 - post_div);
350 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
352 return lldiv((u64)infreq * div, post_div);
354 div = __raw_readl(&anatop->pll_enet);
355 if (div & BM_ANADIG_PLL_ENET_BYPASS)
357 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
359 return 25000000 * (div + (div >> 1) + 1);
361 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
362 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
364 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
366 return infreq * (20 + div * 2);
368 div = __raw_readl(&anatop->pll_mlb);
369 if (div & BM_ANADIG_PLL_MLB_BYPASS)
371 /* unknown external clock provided on MLB_CLK pin */
377 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
384 if (!is_cpu_type(MXC_CPU_MX6UL)) {
386 /* No PFD3 on PPL2 */
390 div = __raw_readl(&anatop->pfd_528);
391 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
394 div = __raw_readl(&anatop->pfd_480);
395 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
398 /* No PFD on other PLL */
402 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
403 ANATOP_PFD_FRAC_SHIFT(pfd_num));
406 static u32 get_mcu_main_clk(void)
410 reg = __raw_readl(&imx_ccm->cacrr);
411 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
412 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
413 freq = decode_pll(PLL_ARM, MXC_HCLK);
415 return freq / (reg + 1);
418 u32 get_periph_clk(void)
420 u32 reg, div = 0, freq = 0;
422 reg = __raw_readl(&imx_ccm->cbcdr);
423 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
424 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
425 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
426 reg = __raw_readl(&imx_ccm->cbcmr);
427 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
428 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
432 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
440 reg = __raw_readl(&imx_ccm->cbcmr);
441 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
442 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
446 freq = decode_pll(PLL_528, MXC_HCLK);
449 freq = mxc_get_pll_pfd(PLL_528, 2);
452 freq = mxc_get_pll_pfd(PLL_528, 0);
455 /* static / 2 divider */
456 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
461 return freq / (div + 1);
464 static u32 get_ipg_clk(void)
468 reg = __raw_readl(&imx_ccm->cbcdr);
469 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
470 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
472 return get_ahb_clk() / (ipg_podf + 1);
475 static u32 get_ipg_per_clk(void)
477 u32 reg, perclk_podf;
479 reg = __raw_readl(&imx_ccm->cscmr1);
480 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
481 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
482 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
483 return MXC_HCLK; /* OSC 24Mhz */
486 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
488 return get_ipg_clk() / (perclk_podf + 1);
491 static u32 get_uart_clk(void)
494 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
495 reg = __raw_readl(&imx_ccm->cscdr1);
497 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
498 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
499 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
503 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
504 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
506 return freq / (uart_podf + 1);
509 static u32 get_cspi_clk(void)
513 reg = __raw_readl(&imx_ccm->cscdr2);
514 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
515 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
517 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
518 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
519 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
520 return MXC_HCLK / (cspi_podf + 1);
523 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
526 static u32 get_axi_clk(void)
528 u32 root_freq, axi_podf;
529 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
531 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
532 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
534 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
535 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
536 root_freq = mxc_get_pll_pfd(PLL_528, 2);
538 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
540 root_freq = get_periph_clk();
542 return root_freq / (axi_podf + 1);
545 static u32 get_emi_slow_clk(void)
547 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
549 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
550 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
551 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
552 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
553 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
555 switch (emi_clk_sel) {
557 root_freq = get_axi_clk();
560 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
563 root_freq = mxc_get_pll_pfd(PLL_528, 2);
566 root_freq = mxc_get_pll_pfd(PLL_528, 0);
570 return root_freq / (emi_slow_podf + 1);
573 static u32 get_nfc_clk(void)
575 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
576 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
577 MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
578 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
579 MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
580 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
581 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
584 switch (nfc_clk_sel) {
586 root_freq = mxc_get_pll_pfd(PLL_528, 0);
589 root_freq = decode_pll(PLL_528, MXC_HCLK);
592 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
595 root_freq = mxc_get_pll_pfd(PLL_528, 2);
598 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
604 return root_freq / (pred + 1) / (podf + 1);
607 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
608 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
609 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
611 static int set_nfc_clk(u32 ref, u32 freq_khz)
613 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
620 u32 freq = freq_khz * 1000;
622 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
626 if (ref < 4 && ref != nfc_clk_sel)
629 switch (nfc_clk_sel) {
631 root_freq = mxc_get_pll_pfd(PLL_528, 0);
634 root_freq = decode_pll(PLL_528, MXC_HCLK);
637 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
640 root_freq = mxc_get_pll_pfd(PLL_528, 2);
643 if (root_freq < freq)
646 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
647 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
648 act_freq = root_freq / pred / podf;
649 err = (freq - act_freq) * 100 / freq;
650 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
651 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
655 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
656 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
657 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
664 if (nfc_val == ~0 || min_err > 10)
667 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
668 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
669 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
670 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
673 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
678 static u32 get_mmdc_ch0_clk(void)
680 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
681 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
683 u32 freq, podf, per2_clk2_podf;
685 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
686 is_cpu_type(MXC_CPU_MX6SL)) {
687 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
688 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
689 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
690 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
691 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
692 if (is_cpu_type(MXC_CPU_MX6SL)) {
693 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
696 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
698 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
699 freq = decode_pll(PLL_528, MXC_HCLK);
701 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
706 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
707 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
709 freq = decode_pll(PLL_528, MXC_HCLK);
712 freq = mxc_get_pll_pfd(PLL_528, 2);
715 freq = mxc_get_pll_pfd(PLL_528, 0);
718 /* static / 2 divider */
719 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
723 return freq / (podf + 1) / (per2_clk2_podf + 1);
725 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
726 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
727 return get_periph_clk() / (podf + 1);
731 #ifdef CONFIG_FSL_QSPI
732 /* qspi_num can be from 0 - 1 */
733 void enable_qspi_clk(int qspi_num)
736 /* Enable QuadSPI clock */
739 /* disable the clock gate */
740 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
742 /* set 50M : (50 = 396 / 2 / 4) */
743 reg = readl(&imx_ccm->cscmr1);
744 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
745 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
746 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
747 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
748 writel(reg, &imx_ccm->cscmr1);
750 /* enable the clock gate */
751 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
755 * disable the clock gate
756 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
757 * disable both of them.
759 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
760 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
762 /* set 50M : (50 = 396 / 2 / 4) */
763 reg = readl(&imx_ccm->cs2cdr);
764 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
765 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
766 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
767 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
768 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
769 writel(reg, &imx_ccm->cs2cdr);
771 /*enable the clock gate*/
772 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
773 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
781 #ifdef CONFIG_FEC_MXC
782 int enable_fec_anatop_clock(enum enet_freq freq)
785 s32 timeout = 100000;
787 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
790 reg = readl(&anatop->pll_enet);
791 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
794 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
795 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
796 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
797 writel(reg, &anatop->pll_enet);
799 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
806 /* Enable FEC clock */
807 reg |= BM_ANADIG_PLL_ENET_ENABLE;
808 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
809 writel(reg, &anatop->pll_enet);
811 #ifdef CONFIG_SOC_MX6SX
813 * Set enet ahb clock to 200MHz
814 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
816 reg = readl(&imx_ccm->chsccdr);
817 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
818 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
819 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
821 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
823 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
824 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
825 writel(reg, &imx_ccm->chsccdr);
827 /* Enable enet system clock */
828 reg = readl(&imx_ccm->CCGR3);
829 reg |= MXC_CCM_CCGR3_ENET_MASK;
830 writel(reg, &imx_ccm->CCGR3);
836 static u32 get_usdhc_clk(u32 port)
838 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
839 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
840 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
844 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
845 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
846 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
850 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
851 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
852 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
856 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
857 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
858 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
862 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
863 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
864 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
872 root_freq = mxc_get_pll_pfd(PLL_528, 0);
874 root_freq = mxc_get_pll_pfd(PLL_528, 2);
876 return root_freq / (usdhc_podf + 1);
879 u32 imx_get_uartclk(void)
881 return get_uart_clk();
884 u32 imx_get_fecclk(void)
886 return mxc_get_clock(MXC_IPG_CLK);
889 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
890 static int enable_enet_pll(uint32_t en)
893 s32 timeout = 100000;
896 reg = readl(&anatop->pll_enet);
897 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
898 writel(reg, &anatop->pll_enet);
899 reg |= BM_ANADIG_PLL_ENET_ENABLE;
901 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
906 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
907 writel(reg, &anatop->pll_enet);
909 writel(reg, &anatop->pll_enet);
914 #ifdef CONFIG_CMD_SATA
915 static void ungate_sata_clock(void)
917 /* Enable SATA clock. */
918 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
921 int enable_sata_clock(void)
924 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
927 void disable_sata_clock(void)
929 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
933 #ifdef CONFIG_PCIE_IMX
934 static void ungate_pcie_clock(void)
936 /* Enable PCIe clock. */
937 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
940 int enable_pcie_clock(void)
947 * The register ANATOP_MISC1 is not documented in the Freescale
948 * MX6RM. The register that is mapped in the ANATOP space and
949 * marked as ANATOP_MISC1 is actually documented in the PMU section
950 * of the datasheet as PMU_MISC1.
952 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
953 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
954 * for PCI express link that is clocked from the i.MX6.
956 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
957 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
958 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
959 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
960 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
962 if (is_cpu_type(MXC_CPU_MX6SX))
963 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
965 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
967 clrsetbits_le32(&anatop_regs->ana_misc1,
968 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
969 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
970 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
972 /* PCIe reference clock sourced from AXI. */
973 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
975 /* Party time! Ungate the clock to the PCIe. */
976 #ifdef CONFIG_CMD_SATA
981 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
982 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
986 #ifdef CONFIG_SECURE_BOOT
987 void hab_caam_clock_enable(unsigned char enable)
991 /* CG4 ~ CG6, CAAM clocks */
992 reg = __raw_readl(&imx_ccm->CCGR0);
994 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
995 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
996 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
998 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
999 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
1000 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
1001 __raw_writel(reg, &imx_ccm->CCGR0);
1004 reg = __raw_readl(&imx_ccm->CCGR6);
1006 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
1008 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
1009 __raw_writel(reg, &imx_ccm->CCGR6);
1013 static void enable_pll3(void)
1015 /* make sure pll3 is enabled */
1016 if ((readl(&anatop->usb1_pll_480_ctrl) &
1017 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1018 /* enable pll's power */
1019 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1020 &anatop->usb1_pll_480_ctrl_set);
1021 writel(0x80, &anatop->ana_misc2_clr);
1022 /* wait for pll lock */
1023 while ((readl(&anatop->usb1_pll_480_ctrl) &
1024 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1026 /* disable bypass */
1027 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1028 &anatop->usb1_pll_480_ctrl_clr);
1029 /* enable pll output */
1030 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1031 &anatop->usb1_pll_480_ctrl_set);
1035 void enable_thermal_clk(void)
1040 void ipu_clk_enable(void)
1042 u32 reg = readl(&imx_ccm->CCGR3);
1043 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1044 writel(reg, &imx_ccm->CCGR3);
1047 void ipu_clk_disable(void)
1049 u32 reg = readl(&imx_ccm->CCGR3);
1050 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1051 writel(reg, &imx_ccm->CCGR3);
1054 void ipu_di_clk_enable(int di)
1058 setbits_le32(&imx_ccm->CCGR3,
1059 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1062 setbits_le32(&imx_ccm->CCGR3,
1063 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1066 printf("%s: Invalid DI index %d\n", __func__, di);
1070 void ipu_di_clk_disable(int di)
1074 clrbits_le32(&imx_ccm->CCGR3,
1075 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1078 clrbits_le32(&imx_ccm->CCGR3,
1079 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1082 printf("%s: Invalid DI index %d\n", __func__, di);
1086 void ldb_clk_enable(int ldb)
1090 setbits_le32(&imx_ccm->CCGR3,
1091 MXC_CCM_CCGR3_LDB_DI0_MASK);
1094 setbits_le32(&imx_ccm->CCGR3,
1095 MXC_CCM_CCGR3_LDB_DI1_MASK);
1098 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1102 void ldb_clk_disable(int ldb)
1106 clrbits_le32(&imx_ccm->CCGR3,
1107 MXC_CCM_CCGR3_LDB_DI0_MASK);
1110 clrbits_le32(&imx_ccm->CCGR3,
1111 MXC_CCM_CCGR3_LDB_DI1_MASK);
1114 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1118 #ifdef CONFIG_VIDEO_MXS
1119 void lcdif_clk_enable(void)
1121 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1122 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1125 void lcdif_clk_disable(void)
1127 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_LCD_MASK);
1128 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_LCDIF_MASK);
1131 #define CBCMR_LCDIF_MASK MXC_CCM_CBCMR_LCDIF_PODF_MASK
1132 #define CSCDR2_LCDIF_MASK (MXC_CCM_CSCDR2_LCDIF_PRED_MASK | \
1133 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK)
1135 static u32 get_lcdif_root_clk(u32 cscdr2)
1137 int lcdif_pre_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) >>
1138 MXC_CCM_CSCDR2_LCDIF_PRE_CLK_SEL_OFFSET;
1139 int lcdif_clk_sel = (cscdr2 & MXC_CCM_CSCDR2_LCDIF_CLK_SEL_MASK) >>
1140 MXC_CCM_CSCDR2_LCDIF_CLK_SEL_OFFSET;
1143 switch (lcdif_clk_sel) {
1145 switch (lcdif_pre_clk_sel) {
1147 root_freq = decode_pll(PLL_528, MXC_HCLK);
1150 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
1153 root_freq = decode_pll(PLL_VIDEO, MXC_HCLK);
1156 root_freq = mxc_get_pll_pfd(PLL_528, 0);
1159 root_freq = mxc_get_pll_pfd(PLL_528, 1);
1162 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
1169 root_freq = mxc_get_pll_pfd(PLL_VIDEO, 0);
1172 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
1175 root_freq = mxc_get_pll_pfd(PLL_528, 2);
1184 static int set_lcdif_pll(u32 ref, u32 freq_khz,
1188 u64 freq = freq_khz * 1000;
1189 u32 post_div_mask = 1 << (2 - post_div);
1195 const int min_div = 27;
1196 const int max_div = 54;
1197 const int div_mask = 0x7f;
1198 const u32 max_freq = ref * max_div / post_div;
1199 const u32 min_freq = ref * min_div / post_div;
1201 if (freq > max_freq || freq < min_freq) {
1202 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03uMHz\n",
1203 freq_khz / 1000, freq_khz % 1000,
1204 min_freq / 1000000, min_freq / 1000 % 1000,
1205 max_freq / 1000000, max_freq / 1000 % 1000);
1210 int m = lldiv(freq * d + ref - 1, ref);
1214 debug("%s@%d: d=%d m=%d max_div=%u min_div=%u\n", __func__, __LINE__,
1215 d, m, max_div, min_div);
1216 if (m > max_div || m < min_div)
1221 debug("%s@%d: d=%d m=%d f=%u freq=%llu\n", __func__, __LINE__,
1226 debug("%s@%d: d=%d m=%d f=%u freq=%llu err=%d\n", __func__, __LINE__,
1227 d, m, f, freq, err);
1228 if (err < min_err) {
1233 if (min_err == ~0) {
1234 printf("Cannot set VIDEO PLL to %u.%03uMHz\n",
1235 freq_khz / 1000, freq_khz % 1000);
1239 debug("Setting M=%3u D=%u N=%d DE=%u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1240 mul, post_div, num, denom,
1241 freq_khz / post_div / 1000, freq_khz / post_div % 1000,
1242 ref * mul / post_div / 1000000,
1243 ref * mul / post_div / 1000 % 1000);
1245 reg = readl(&anatop->pll_video);
1246 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1248 reg = (reg & ~(div_mask |
1249 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)) |
1250 mul | (post_div_mask << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT);
1251 writel(reg, &anatop->pll_video);
1253 ret = wait_pll_lock(&anatop->pll_video);
1255 printf("Video PLL failed to lock\n");
1259 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_VIDEO_BYPASS);
1263 static int set_lcdif_clk(u32 ref, u32 freq_khz)
1265 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1266 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1269 u32 freq = freq_khz * 1000;
1274 u32 min_pll_khz = ref * min_div / 4 / 1000;
1275 u32 max_pll_khz = ref * max_div / 1000;
1286 if (freq_khz > max_pll_khz)
1289 for (pd = 1; min_err && pd <= 4; pd <<= 1) {
1290 for (m = max(min_div, DIV_ROUND_UP(648000 / pd, freq_khz * 64));
1291 m <= max_div; m++) {
1295 u32 root_freq = ref * m / pd;
1297 div = DIV_ROUND_UP(root_freq, freq);
1299 while (pred * podf == 0 && div <= 64) {
1302 for (p1 = 1; p1 <= 8; p1++) {
1303 for (p2 = 1; p2 <= 8; p2++) {
1304 if (p1 * p2 == div) {
1311 if (pred * podf == 0) {
1315 if (pred * podf == 0)
1318 /* relative error in per mille */
1319 act_freq = root_freq / div;
1320 err = abs(act_freq - freq) / freq_khz;
1322 if (err < min_err) {
1336 pll_khz = ref / 1000 * best_m;
1337 if (pll_khz > max_pll_khz)
1340 if (pll_khz < min_pll_khz)
1343 err = set_lcdif_pll(ref, pll_khz / post_div, post_div);
1347 cbcmr_val = (best_podf - 1) << MXC_CCM_CBCMR_LCDIF_PODF_OFFSET;
1348 cscdr2_val = (best_pred - 1) << MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET;
1350 if ((cbcmr & CBCMR_LCDIF_MASK) != cbcmr_val) {
1351 debug("changing cbcmr from %08x to %08x\n", cbcmr,
1352 (cbcmr & ~CBCMR_LCDIF_MASK) | cbcmr_val);
1353 clrsetbits_le32(&imx_ccm->cbcmr,
1357 debug("Leaving cbcmr unchanged [%08x]\n", cbcmr);
1359 if ((cscdr2 & CSCDR2_LCDIF_MASK) != cscdr2_val) {
1360 debug("changing cscdr2 from %08x to %08x\n", cscdr2,
1361 (cscdr2 & ~CSCDR2_LCDIF_MASK) | cscdr2_val);
1362 clrsetbits_le32(&imx_ccm->cscdr2,
1366 debug("Leaving cscdr2 unchanged [%08x]\n", cscdr2);
1371 void mxs_set_lcdclk(u32 khz)
1373 set_lcdif_clk(CONFIG_SYS_MX6_HCLK, khz);
1376 static u32 get_lcdif_clk(void)
1378 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
1379 u32 podf = ((cbcmr & MXC_CCM_CBCMR_LCDIF_PODF_MASK) >>
1380 MXC_CCM_CBCMR_LCDIF_PODF_OFFSET) + 1;
1381 u32 cscdr2 = __raw_readl(&imx_ccm->cscdr2);
1382 u32 pred = ((cscdr2 & MXC_CCM_CSCDR2_LCDIF_PRED_MASK) >>
1383 MXC_CCM_CSCDR2_LCDIF_PRED_OFFSET) + 1;
1384 u32 root_freq = get_lcdif_root_clk(cscdr2);
1386 return root_freq / pred / podf;
1390 unsigned int mxc_get_clock(enum mxc_clock clk)
1394 return get_mcu_main_clk();
1396 return get_periph_clk();
1398 return get_ahb_clk();
1400 return get_ipg_clk();
1401 case MXC_IPG_PERCLK:
1403 return get_ipg_per_clk();
1405 return get_uart_clk();
1407 return get_cspi_clk();
1409 return get_axi_clk();
1410 case MXC_EMI_SLOW_CLK:
1411 return get_emi_slow_clk();
1413 return get_mmdc_ch0_clk();
1415 return get_usdhc_clk(0);
1416 case MXC_ESDHC2_CLK:
1417 return get_usdhc_clk(1);
1418 case MXC_ESDHC3_CLK:
1419 return get_usdhc_clk(2);
1420 case MXC_ESDHC4_CLK:
1421 return get_usdhc_clk(3);
1423 return get_ahb_clk();
1425 return get_nfc_clk();
1426 #ifdef CONFIG_VIDEO_MXS
1428 return get_lcdif_clk();
1431 printf("Unsupported MXC CLK: %d\n", clk);
1437 /* Config CPU clock */
1438 static int set_arm_clk(u32 ref, u32 freq_khz)
1446 const int min_div = 54;
1447 const int max_div = 108;
1448 const int div_mask = 0x7f;
1449 const u32 max_freq = ref * max_div / 2;
1450 const u32 min_freq = ref * min_div / 8 / 2;
1452 if (freq_khz > max_freq / 1000 || freq_khz < min_freq / 1000) {
1453 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1454 freq_khz / 1000, freq_khz % 1000,
1455 min_freq / 1000000, min_freq / 1000 % 1000,
1456 max_freq / 1000000, max_freq / 1000 % 1000);
1460 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1461 int m = freq_khz * 2 * d / (ref / 1000);
1466 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1471 f = ref * m / d / 2;
1472 if (f > freq_khz * 1000) {
1473 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1477 f = ref * m / d / 2;
1479 err = freq_khz * 1000 - f;
1480 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1481 d, m, f, freq_khz, err);
1482 if (err < min_err) {
1492 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1493 mul, div, freq_khz / 1000, freq_khz % 1000,
1494 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1496 reg = readl(&anatop->pll_arm);
1497 setbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1499 reg = (reg & ~div_mask) | mul;
1500 writel(reg, &anatop->pll_arm);
1502 writel(div - 1, &imx_ccm->cacrr);
1504 ret = wait_pll_lock(&anatop->pll_video);
1506 printf("ARM PLL failed to lock\n");
1510 clrbits_le32(&anatop->pll_video, BM_ANADIG_PLL_ARM_BYPASS);
1516 * This function assumes the expected core clock has to be changed by
1517 * modifying the PLL. This is NOT true always but for most of the times,
1518 * it is. So it assumes the PLL output freq is the same as the expected
1519 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1520 * In the latter case, it will try to increase the presc value until
1521 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1522 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1523 * on the targeted PLL and reference input clock to the PLL. Lastly,
1524 * it sets the register based on these values along with the dividers.
1525 * Note 1) There is no value checking for the passed-in divider values
1526 * so the caller has to make sure those values are sensible.
1527 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1528 * exceed NFC_CLK_MAX.
1530 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1538 ret = set_arm_clk(ref, freq);
1542 ret = set_nfc_clk(ref, freq);
1546 printf("Warning: Unsupported or invalid clock type: %d\n",
1555 * Dump some core clocks.
1557 #define print_pll(pll) { \
1558 u32 __pll = decode_pll(pll, MXC_HCLK); \
1559 printf("%-12s %4d.%03d MHz\n", #pll, \
1560 __pll / 1000000, __pll / 1000 % 1000); \
1563 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1565 #define print_clk(clk) { \
1566 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1567 printf("%-12s %4d.%03d MHz\n", #clk, \
1568 __clk / 1000000, __clk / 1000 % 1000); \
1571 #define print_pfd(pll, pfd) { \
1572 u32 __pfd = readl(&anatop->pfd_##pll); \
1573 if (__pfd & (0x80 << 8 * pfd)) { \
1574 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1576 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1577 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1579 pll * 18 * 1000 / __pfd % 1000); \
1583 static void do_mx6_showclocks(void)
1587 print_pll(PLL_USBOTG);
1588 print_pll(PLL_AUDIO);
1589 print_pll(PLL_VIDEO);
1590 print_pll(PLL_ENET);
1591 print_pll(PLL_USB2);
1613 print_clk(EMI_SLOW);
1617 #ifdef CONFIG_VIDEO_MXS
1622 static struct clk_lookup {
1625 } mx6_clk_lookup[] = {
1626 { "arm", MXC_ARM_CLK, },
1627 { "nfc", MXC_NFC_CLK, },
1630 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1634 unsigned long ref = ~0UL;
1637 do_mx6_showclocks();
1638 return CMD_RET_SUCCESS;
1639 } else if (argc == 2 || argc > 4) {
1640 return CMD_RET_USAGE;
1643 freq = simple_strtoul(argv[2], NULL, 0);
1645 printf("Invalid clock frequency %lu\n", freq);
1646 return CMD_RET_FAILURE;
1649 ref = simple_strtoul(argv[3], NULL, 0);
1651 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1652 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1653 switch (mx6_clk_lookup[i].index) {
1656 return CMD_RET_USAGE;
1661 if (argc > 3 && ref > 3) {
1662 printf("Invalid clock selector value: %lu\n", ref);
1663 return CMD_RET_FAILURE;
1667 printf("Setting %s clock to %lu MHz\n",
1668 mx6_clk_lookup[i].name, freq);
1669 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1671 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1672 printf("%s clock set to %lu.%03lu MHz\n",
1673 mx6_clk_lookup[i].name,
1674 freq / 1000000, freq / 1000 % 1000);
1675 return CMD_RET_SUCCESS;
1678 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1679 printf("clock %s not found; supported clocks are:\n", argv[1]);
1680 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1681 printf("\t%s\n", mx6_clk_lookup[i].name);
1684 printf("Failed to set clock %s to %s MHz\n",
1687 return CMD_RET_FAILURE;
1690 #ifndef CONFIG_SOC_MX6SX
1691 void enable_ipu_clock(void)
1693 int reg = readl(&imx_ccm->CCGR3);
1694 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1695 writel(reg, &imx_ccm->CCGR3);
1698 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1699 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1703 /***************************************************/
1706 clocks, 4, 0, do_clocks,
1707 "display/set clocks",
1708 " - display clock settings\n"
1709 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"