arch/arm/cpu/armv7/mx6/clock.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <div64.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 enum pll_clocks {
  17         PLL_ARM,        /* PLL1: ARM PLL */
  18         PLL_528,        /* PLL2: System Bus PLL*/
  19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
  20         PLL_AUDIO,      /* PLL4: Audio PLL */
  21         PLL_VIDEO,      /* PLL5: Video PLL */
  22         PLL_ENET,       /* PLL6: ENET PLL */
  23         PLL_USB2,       /* PLL7: USB2 PLL */
  24         PLL_MLB,        /* PLL8: MLB PLL */
  25 };
  26
  27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
  28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
  29
  30 int clk_enable(struct clk *clk)
  31 {
  32         int ret = 0;
  33
  34         if (!clk)
  35                 return 0;
  36         if (clk->usecount == 0) {
  37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
  38                 ret = clk->enable(clk);
  39                 if (ret)
  40                         return ret;
  41                 clk->usecount++;
  42         }
  43         assert(clk->usecount > 0);
  44         return ret;
  45 }
  46
  47 void clk_disable(struct clk *clk)
  48 {
  49         if (!clk)
  50                 return;
  51
  52         assert(clk->usecount > 0);
  53         if (!(--clk->usecount)) {
  54                 if (clk->disable) {
  55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
  56                         clk->disable(clk);
  57                 }
  58         }
  59 }
  60
  61 int clk_get_usecount(struct clk *clk)
  62 {
  63         if (clk == NULL)
  64                 return 0;
  65
  66         return clk->usecount;
  67 }
  68
  69 u32 clk_get_rate(struct clk *clk)
  70 {
  71         if (!clk)
  72                 return 0;
  73
  74         return clk->rate;
  75 }
  76
  77 struct clk *clk_get_parent(struct clk *clk)
  78 {
  79         if (!clk)
  80                 return 0;
  81
  82         return clk->parent;
  83 }
  84
  85 int clk_set_rate(struct clk *clk, unsigned long rate)
  86 {
  87         if (clk && clk->set_rate)
  88                 clk->set_rate(clk, rate);
  89         return clk->rate;
  90 }
  91
  92 long clk_round_rate(struct clk *clk, unsigned long rate)
  93 {
  94         if (clk == NULL || !clk->round_rate)
  95                 return 0;
  96
  97         return clk->round_rate(clk, rate);
  98 }
  99
 100 int clk_set_parent(struct clk *clk, struct clk *parent)
 101 {
 102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
 103                 clk ? clk->parent : NULL);
 104
 105         if (!clk || clk == parent)
 106                 return 0;
 107
 108         if (clk->set_parent) {
 109                 int ret;
 110
 111                 ret = clk->set_parent(clk, parent);
 112                 if (ret)
 113                         return ret;
 114         }
 115         clk->parent = parent;
 116         return 0;
 117 }
 118
 119 #ifdef CONFIG_MXC_OCOTP
 120 void enable_ocotp_clk(unsigned char enable)
 121 {
 122         u32 reg;
 123
 124         reg = __raw_readl(&imx_ccm->CCGR2);
 125         if (enable)
 126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 127         else
 128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
 129         __raw_writel(reg, &imx_ccm->CCGR2);
 130 }
 131 #endif
 132
 133 #ifdef CONFIG_NAND_MXS
 134 void setup_gpmi_io_clk(u32 cfg)
 135 {
 136         /* Disable clocks per ERR007177 from MX6 errata */
 137         clrbits_le32(&imx_ccm->CCGR4,
 138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 143
 144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 145
 146         clrsetbits_le32(&imx_ccm->cs2cdr,
 147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 150                         cfg);
 151
 152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 153         setbits_le32(&imx_ccm->CCGR4,
 154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 159 }
 160 #endif
 161
 162 void enable_usboh3_clk(unsigned char enable)
 163 {
 164         u32 reg;
 165
 166         reg = __raw_readl(&imx_ccm->CCGR6);
 167         if (enable)
 168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
 169         else
 170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
 171         __raw_writel(reg, &imx_ccm->CCGR6);
 172
 173 }
 174
 175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
 176 void enable_enet_clk(unsigned char enable)
 177 {
 178         u32 mask, *addr;
 179
 180         if (is_cpu_type(MXC_CPU_MX6UL)) {
 181                 mask = MXC_CCM_CCGR3_ENET_MASK;
 182                 addr = &imx_ccm->CCGR3;
 183         } else {
 184                 mask = MXC_CCM_CCGR1_ENET_MASK;
 185                 addr = &imx_ccm->CCGR1;
 186         }
 187
 188         if (enable)
 189                 setbits_le32(addr, mask);
 190         else
 191                 clrbits_le32(addr, mask);
 192 }
 193 #endif
 194
 195 #ifdef CONFIG_MXC_UART
 196 void enable_uart_clk(unsigned char enable)
 197 {
 198         u32 mask;
 199
 200         if (is_cpu_type(MXC_CPU_MX6UL))
 201                 mask = MXC_CCM_CCGR5_UART_MASK;
 202         else
 203                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
 204
 205         if (enable)
 206                 setbits_le32(&imx_ccm->CCGR5, mask);
 207         else
 208                 clrbits_le32(&imx_ccm->CCGR5, mask);
 209 }
 210 #endif
 211
 212 #ifdef CONFIG_MMC
 213 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
 214 {
 215         u32 mask;
 216
 217         if (bus_num > 3)
 218                 return -EINVAL;
 219
 220         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
 221         if (enable)
 222                 setbits_le32(&imx_ccm->CCGR6, mask);
 223         else
 224                 clrbits_le32(&imx_ccm->CCGR6, mask);
 225
 226         return 0;
 227 }
 228 #endif
 229
 230 #ifdef CONFIG_SYS_I2C_MXC
 231 /* i2c_num can be from 0 - 3 */
 232 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 233 {
 234         u32 reg;
 235         u32 mask;
 236         u32 *addr;
 237
 238         if (i2c_num > 3)
 239                 return -EINVAL;
 240         if (i2c_num < 3) {
 241                 mask = MXC_CCM_CCGR_CG_MASK
 242                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
 243                         + (i2c_num << 1));
 244                 reg = __raw_readl(&imx_ccm->CCGR2);
 245                 if (enable)
 246                         reg |= mask;
 247                 else
 248                         reg &= ~mask;
 249                 __raw_writel(reg, &imx_ccm->CCGR2);
 250         } else {
 251                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 252                         mask = MXC_CCM_CCGR6_I2C4_MASK;
 253                         addr = &imx_ccm->CCGR6;
 254                 } else {
 255                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
 256                         addr = &imx_ccm->CCGR1;
 257                 }
 258                 reg = __raw_readl(addr);
 259                 if (enable)
 260                         reg |= mask;
 261                 else
 262                         reg &= ~mask;
 263                 __raw_writel(reg, addr);
 264         }
 265         return 0;
 266 }
 267 #endif
 268
 269 /* spi_num can be from 0 - SPI_MAX_NUM */
 270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
 271 {
 272         u32 reg;
 273         u32 mask;
 274
 275         if (spi_num > SPI_MAX_NUM)
 276                 return -EINVAL;
 277
 278         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
 279         reg = __raw_readl(&imx_ccm->CCGR1);
 280         if (enable)
 281                 reg |= mask;
 282         else
 283                 reg &= ~mask;
 284         __raw_writel(reg, &imx_ccm->CCGR1);
 285         return 0;
 286 }
 287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 288 {
 289         u32 div;
 290
 291         switch (pll) {
 292         case PLL_ARM:
 293                 div = __raw_readl(&anatop->pll_arm);
 294                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
 295                         /* Assume the bypass clock is always derived from OSC */
 296                         return infreq;
 297                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
 298
 299                 return infreq * div / 2;
 300         case PLL_528:
 301                 div = __raw_readl(&anatop->pll_528);
 302                 if (div & BM_ANADIG_PLL_528_BYPASS)
 303                         return infreq;
 304                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
 305
 306                 return infreq * (20 + div * 2);
 307         case PLL_USBOTG:
 308                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
 309                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 310                         return infreq;
 311                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 312
 313                 return infreq * (20 + div * 2);
 314         case PLL_AUDIO:
 315                 div = __raw_readl(&anatop->pll_audio);
 316                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
 317                         return infreq;
 318                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
 319
 320                 return infreq * div;
 321         case PLL_VIDEO:
 322                 div = __raw_readl(&anatop->pll_video);
 323                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
 324                         return infreq;
 325                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 326
 327                 return infreq * div;
 328         case PLL_ENET:
 329                 div = __raw_readl(&anatop->pll_enet);
 330                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
 331                         return infreq;
 332                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 333
 334                 return 25000000 * (div + (div >> 1) + 1);
 335         case PLL_USB2:
 336                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
 337                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
 338                         return infreq;
 339                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
 340
 341                 return infreq * (20 + div * 2);
 342         case PLL_MLB:
 343                 div = __raw_readl(&anatop->pll_mlb);
 344                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
 345                         return infreq;
 346                 /* unknown external clock provided on MLB_CLK pin */
 347                 return 0;
 348         }
 349         return 0;
 350 }
 351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 352 {
 353         u32 div;
 354         u64 freq;
 355
 356         switch (pll) {
 357         case PLL_528:
 358                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
 359                         if (pfd_num == 3) {
 360                                 /* No PFD3 on PPL2 */
 361                                 return 0;
 362                         }
 363                 }
 364                 div = __raw_readl(&anatop->pfd_528);
 365                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
 366                 break;
 367         case PLL_USBOTG:
 368                 div = __raw_readl(&anatop->pfd_480);
 369                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
 370                 break;
 371         default:
 372                 /* No PFD on other PLL */
 373                 return 0;
 374         }
 375
 376         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
 377                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
 378 }
 379
 380 static u32 get_mcu_main_clk(void)
 381 {
 382         u32 reg, freq;
 383
 384         reg = __raw_readl(&imx_ccm->cacrr);
 385         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
 386         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
 387         freq = decode_pll(PLL_ARM, MXC_HCLK);
 388
 389         return freq / (reg + 1);
 390 }
 391
 392 u32 get_periph_clk(void)
 393 {
 394         u32 reg, div = 0, freq = 0;
 395
 396         reg = __raw_readl(&imx_ccm->cbcdr);
 397         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 398                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
 399                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
 400                 reg = __raw_readl(&imx_ccm->cbcmr);
 401                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 402                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
 403
 404                 switch (reg) {
 405                 case 0:
 406                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 407                         break;
 408                 case 1:
 409                 case 2:
 410                         freq = MXC_HCLK;
 411                         break;
 412                 }
 413         } else {
 414                 reg = __raw_readl(&imx_ccm->cbcmr);
 415                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 416                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 417
 418                 switch (reg) {
 419                 case 0:
 420                         freq = decode_pll(PLL_528, MXC_HCLK);
 421                         break;
 422                 case 1:
 423                         freq = mxc_get_pll_pfd(PLL_528, 2);
 424                         break;
 425                 case 2:
 426                         freq = mxc_get_pll_pfd(PLL_528, 0);
 427                         break;
 428                 case 3:
 429                         /* static / 2 divider */
 430                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
 431                         break;
 432                 }
 433         }
 434
 435         return freq / (div + 1);
 436 }
 437
 438 static u32 get_ipg_clk(void)
 439 {
 440         u32 reg, ipg_podf;
 441
 442         reg = __raw_readl(&imx_ccm->cbcdr);
 443         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
 444         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 445
 446         return get_ahb_clk() / (ipg_podf + 1);
 447 }
 448
 449 static u32 get_ipg_per_clk(void)
 450 {
 451         u32 reg, perclk_podf;
 452
 453         reg = __raw_readl(&imx_ccm->cscmr1);
 454         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 455             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 456                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 457                         return MXC_HCLK; /* OSC 24Mhz */
 458         }
 459
 460         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
 461
 462         return get_ipg_clk() / (perclk_podf + 1);
 463 }
 464
 465 static u32 get_uart_clk(void)
 466 {
 467         u32 reg, uart_podf;
 468         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 469         reg = __raw_readl(&imx_ccm->cscdr1);
 470
 471         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
 472             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
 473                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 474                         freq = MXC_HCLK;
 475         }
 476
 477         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
 478         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 479
 480         return freq / (uart_podf + 1);
 481 }
 482
 483 static u32 get_cspi_clk(void)
 484 {
 485         u32 reg, cspi_podf;
 486
 487         reg = __raw_readl(&imx_ccm->cscdr2);
 488         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 489                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 490
 491         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
 492             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
 493                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 494                         return MXC_HCLK / (cspi_podf + 1);
 495         }
 496
 497         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
 498 }
 499
 500 static u32 get_axi_clk(void)
 501 {
 502         u32 root_freq, axi_podf;
 503         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 504
 505         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
 506         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 507
 508         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
 509                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
 510                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 511                 else
 512                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
 513         } else {
 514                 root_freq = get_periph_clk();
 515         }
 516         return  root_freq / (axi_podf + 1);
 517 }
 518
 519 static u32 get_emi_slow_clk(void)
 520 {
 521         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 522
 523         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 524         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 525         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
 526         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
 527         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 528
 529         switch (emi_clk_sel) {
 530         case 0:
 531                 root_freq = get_axi_clk();
 532                 break;
 533         case 1:
 534                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 535                 break;
 536         case 2:
 537                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
 538                 break;
 539         case 3:
 540                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
 541                 break;
 542         }
 543
 544         return root_freq / (emi_slow_podf + 1);
 545 }
 546
 547 static u32 get_nfc_clk(void)
 548 {
 549         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 550         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 551         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 552         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
 553                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 554         u32 root_freq;
 555
 556         switch (nfc_clk_sel) {
 557         case 0:
 558                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 559                 break;
 560         case 1:
 561                 root_freq = decode_pll(PLL_528, MXC_HCLK);
 562                 break;
 563         case 2:
 564                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 565                 break;
 566         case 3:
 567                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 568                 break;
 569         default:
 570                 return 0;
 571         }
 572
 573         return root_freq / (pred + 1) / (podf + 1);
 574 }
 575
 576 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
 577                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
 578                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
 579
 580 static int set_nfc_clk(u32 ref, u32 freq_khz)
 581 {
 582         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
 583         u32 podf;
 584         u32 pred;
 585         int nfc_clk_sel;
 586         u32 root_freq;
 587         u32 min_err = ~0;
 588         u32 nfc_val = ~0;
 589         u32 freq = freq_khz * 1000;
 590
 591         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
 592                 u32 act_freq;
 593                 u32 err;
 594
 595                 if (ref < 4 && ref != nfc_clk_sel)
 596                         continue;
 597
 598                 switch (nfc_clk_sel) {
 599                 case 0:
 600                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
 601                         break;
 602                 case 1:
 603                         root_freq = decode_pll(PLL_528, MXC_HCLK);
 604                         break;
 605                 case 2:
 606                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 607                         break;
 608                 case 3:
 609                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
 610                         break;
 611                 }
 612                 if (root_freq < freq)
 613                         continue;
 614
 615                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
 616                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
 617                 act_freq = root_freq / pred / podf;
 618                 err = (freq - act_freq) * 100 / freq;
 619                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
 620                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
 621                 if (act_freq > freq)
 622                         continue;
 623                 if (err < min_err) {
 624                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
 625                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
 626                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
 627                         min_err = err;
 628                         if (err == 0)
 629                                 break;
 630                 }
 631         }
 632
 633         if (nfc_val == ~0 || min_err > 10)
 634                 return -EINVAL;
 635
 636         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
 637                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
 638                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
 639                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
 640                         &imx_ccm->cs2cdr);
 641         } else {
 642                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
 643         }
 644         return 0;
 645 }
 646
 647 static u32 get_mmdc_ch0_clk(void)
 648 {
 649         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 650         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
 651
 652         u32 freq, podf, per2_clk2_podf;
 653
 654         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
 655             is_cpu_type(MXC_CPU_MX6SL)) {
 656                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 657                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 658                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 659                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 660                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
 661                         if (is_cpu_type(MXC_CPU_MX6SL)) {
 662                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 663                                         freq = MXC_HCLK;
 664                                 else
 665                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 666                         } else {
 667                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 668                                         freq = decode_pll(PLL_528, MXC_HCLK);
 669                                 else
 670                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
 671                         }
 672                 } else {
 673                         per2_clk2_podf = 0;
 674                         switch ((cbcmr &
 675                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
 676                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
 677                         case 0:
 678                                 freq = decode_pll(PLL_528, MXC_HCLK);
 679                                 break;
 680                         case 1:
 681                                 freq = mxc_get_pll_pfd(PLL_528, 2);
 682                                 break;
 683                         case 2:
 684                                 freq = mxc_get_pll_pfd(PLL_528, 0);
 685                                 break;
 686                         case 3:
 687                                 /* static / 2 divider */
 688                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
 689                                 break;
 690                         }
 691                 }
 692                 return freq / (podf + 1) / (per2_clk2_podf + 1);
 693         } else {
 694                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
 695                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
 696                 return get_periph_clk() / (podf + 1);
 697         }
 698 }
 699
 700 #ifdef CONFIG_FSL_QSPI
 701 /* qspi_num can be from 0 - 1 */
 702 void enable_qspi_clk(int qspi_num)
 703 {
 704         u32 reg = 0;
 705         /* Enable QuadSPI clock */
 706         switch (qspi_num) {
 707         case 0:
 708                 /* disable the clock gate */
 709                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 710
 711                 /* set 50M  : (50 = 396 / 2 / 4) */
 712                 reg = readl(&imx_ccm->cscmr1);
 713                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 714                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 715                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 716                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 717                 writel(reg, &imx_ccm->cscmr1);
 718
 719                 /* enable the clock gate */
 720                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 721                 break;
 722         case 1:
 723                 /*
 724                  * disable the clock gate
 725                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 726                  * disable both of them.
 727                  */
 728                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 729                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 730
 731                 /* set 50M  : (50 = 396 / 2 / 4) */
 732                 reg = readl(&imx_ccm->cs2cdr);
 733                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 734                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 735                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 736                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 737                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 738                 writel(reg, &imx_ccm->cs2cdr);
 739
 740                 /*enable the clock gate*/
 741                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 742                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 743                 break;
 744         default:
 745                 break;
 746         }
 747 }
 748 #endif
 749
 750 #ifdef CONFIG_FEC_MXC
 751 int enable_fec_anatop_clock(enum enet_freq freq)
 752 {
 753         u32 reg = 0;
 754         s32 timeout = 100000;
 755
 756         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 757                 return -EINVAL;
 758
 759         reg = readl(&anatop->pll_enet);
 760         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
 761         reg |= freq;
 762
 763         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 764             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
 765                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 766                 writel(reg, &anatop->pll_enet);
 767                 while (timeout--) {
 768                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 769                                 break;
 770                 }
 771                 if (timeout < 0)
 772                         return -ETIMEDOUT;
 773         }
 774
 775         /* Enable FEC clock */
 776         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 777         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 778         writel(reg, &anatop->pll_enet);
 779
 780 #ifdef CONFIG_SOC_MX6SX
 781         /*
 782          * Set enet ahb clock to 200MHz
 783          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
 784          */
 785         reg = readl(&imx_ccm->chsccdr);
 786         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
 787                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
 788                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
 789         /* PLL2 PFD2 */
 790         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
 791         /* Div = 2*/
 792         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
 793         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
 794         writel(reg, &imx_ccm->chsccdr);
 795
 796         /* Enable enet system clock */
 797         reg = readl(&imx_ccm->CCGR3);
 798         reg |= MXC_CCM_CCGR3_ENET_MASK;
 799         writel(reg, &imx_ccm->CCGR3);
 800 #endif
 801         return 0;
 802 }
 803 #endif
 804
 805 static u32 get_usdhc_clk(u32 port)
 806 {
 807         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
 808         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
 809         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
 810
 811         switch (port) {
 812         case 0:
 813                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
 814                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
 815                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
 816
 817                 break;
 818         case 1:
 819                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
 820                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
 821                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
 822
 823                 break;
 824         case 2:
 825                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
 826                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
 827                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
 828
 829                 break;
 830         case 3:
 831                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
 832                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
 833                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
 834
 835                 break;
 836         default:
 837                 break;
 838         }
 839
 840         if (clk_sel)
 841                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
 842         else
 843                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
 844
 845         return root_freq / (usdhc_podf + 1);
 846 }
 847
 848 u32 imx_get_uartclk(void)
 849 {
 850         return get_uart_clk();
 851 }
 852
 853 u32 imx_get_fecclk(void)
 854 {
 855         return mxc_get_clock(MXC_IPG_CLK);
 856 }
 857
 858 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
 859 static int enable_enet_pll(uint32_t en)
 860 {
 861         u32 reg;
 862         s32 timeout = 100000;
 863
 864         /* Enable PLLs */
 865         reg = readl(&anatop->pll_enet);
 866         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
 867         writel(reg, &anatop->pll_enet);
 868         reg |= BM_ANADIG_PLL_ENET_ENABLE;
 869         while (timeout--) {
 870                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
 871                         break;
 872         }
 873         if (timeout <= 0)
 874                 return -EIO;
 875         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 876         writel(reg, &anatop->pll_enet);
 877         reg |= en;
 878         writel(reg, &anatop->pll_enet);
 879         return 0;
 880 }
 881 #endif
 882
 883 #ifdef CONFIG_CMD_SATA
 884 static void ungate_sata_clock(void)
 885 {
 886         /* Enable SATA clock. */
 887         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 888 }
 889
 890 int enable_sata_clock(void)
 891 {
 892         ungate_sata_clock();
 893         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
 894 }
 895
 896 void disable_sata_clock(void)
 897 {
 898         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
 899 }
 900 #endif
 901
 902 #ifdef CONFIG_PCIE_IMX
 903 static void ungate_pcie_clock(void)
 904 {
 905         /* Enable PCIe clock. */
 906         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 907 }
 908
 909 int enable_pcie_clock(void)
 910 {
 911         u32 lvds1_clk_sel;
 912
 913         /*
 914          * Here be dragons!
 915          *
 916          * The register ANATOP_MISC1 is not documented in the Freescale
 917          * MX6RM. The register that is mapped in the ANATOP space and
 918          * marked as ANATOP_MISC1 is actually documented in the PMU section
 919          * of the datasheet as PMU_MISC1.
 920          *
 921          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
 922          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
 923          * for PCI express link that is clocked from the i.MX6.
 924          */
 925 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
 926 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
 927 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
 928 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
 929 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
 930
 931         if (is_cpu_type(MXC_CPU_MX6SX))
 932                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 933         else
 934                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
 935
 936         clrsetbits_le32(&anatop_regs->ana_misc1,
 937                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
 938                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
 939                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
 940
 941         /* PCIe reference clock sourced from AXI. */
 942         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 943
 944         /* Party time! Ungate the clock to the PCIe. */
 945 #ifdef CONFIG_CMD_SATA
 946         ungate_sata_clock();
 947 #endif
 948         ungate_pcie_clock();
 949
 950         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
 951                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 952 }
 953 #endif
 954
 955 #ifdef CONFIG_SECURE_BOOT
 956 void hab_caam_clock_enable(unsigned char enable)
 957 {
 958         u32 reg;
 959
 960         /* CG4 ~ CG6, CAAM clocks */
 961         reg = __raw_readl(&imx_ccm->CCGR0);
 962         if (enable)
 963                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 964                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 965                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 966         else
 967                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 968                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 969                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 970         __raw_writel(reg, &imx_ccm->CCGR0);
 971
 972         /* EMI slow clk */
 973         reg = __raw_readl(&imx_ccm->CCGR6);
 974         if (enable)
 975                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
 976         else
 977                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
 978         __raw_writel(reg, &imx_ccm->CCGR6);
 979 }
 980 #endif
 981
 982 static void enable_pll3(void)
 983 {
 984         /* make sure pll3 is enabled */
 985         if ((readl(&anatop->usb1_pll_480_ctrl) &
 986                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
 987                 /* enable pll's power */
 988                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
 989                        &anatop->usb1_pll_480_ctrl_set);
 990                 writel(0x80, &anatop->ana_misc2_clr);
 991                 /* wait for pll lock */
 992                 while ((readl(&anatop->usb1_pll_480_ctrl) &
 993                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
 994                         ;
 995                 /* disable bypass */
 996                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
 997                        &anatop->usb1_pll_480_ctrl_clr);
 998                 /* enable pll output */
 999                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1000                        &anatop->usb1_pll_480_ctrl_set);
1001         }
1002 }
1003
1004 void enable_thermal_clk(void)
1005 {
1006         enable_pll3();
1007 }
1008
1009 void ipu_clk_enable(void)
1010 {
1011         u32 reg = readl(&imx_ccm->CCGR3);
1012         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1013         writel(reg, &imx_ccm->CCGR3);
1014 }
1015
1016 void ipu_clk_disable(void)
1017 {
1018         u32 reg = readl(&imx_ccm->CCGR3);
1019         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1020         writel(reg, &imx_ccm->CCGR3);
1021 }
1022
1023 void ipu_di_clk_enable(int di)
1024 {
1025         switch (di) {
1026         case 0:
1027                 setbits_le32(&imx_ccm->CCGR3,
1028                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1029                 break;
1030         case 1:
1031                 setbits_le32(&imx_ccm->CCGR3,
1032                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1033                 break;
1034         default:
1035                 printf("%s: Invalid DI index %d\n", __func__, di);
1036         }
1037 }
1038
1039 void ipu_di_clk_disable(int di)
1040 {
1041         switch (di) {
1042         case 0:
1043                 clrbits_le32(&imx_ccm->CCGR3,
1044                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1045                 break;
1046         case 1:
1047                 clrbits_le32(&imx_ccm->CCGR3,
1048                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1049                 break;
1050         default:
1051                 printf("%s: Invalid DI index %d\n", __func__, di);
1052         }
1053 }
1054
1055 void ldb_clk_enable(int ldb)
1056 {
1057         switch (ldb) {
1058         case 0:
1059                 setbits_le32(&imx_ccm->CCGR3,
1060                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1061                 break;
1062         case 1:
1063                 setbits_le32(&imx_ccm->CCGR3,
1064                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1065                 break;
1066         default:
1067                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1068         }
1069 }
1070
1071 void ldb_clk_disable(int ldb)
1072 {
1073         switch (ldb) {
1074         case 0:
1075                 clrbits_le32(&imx_ccm->CCGR3,
1076                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1077                 break;
1078         case 1:
1079                 clrbits_le32(&imx_ccm->CCGR3,
1080                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1081                 break;
1082         default:
1083                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1084         }
1085 }
1086
1087 unsigned int mxc_get_clock(enum mxc_clock clk)
1088 {
1089         switch (clk) {
1090         case MXC_ARM_CLK:
1091                 return get_mcu_main_clk();
1092         case MXC_PER_CLK:
1093                 return get_periph_clk();
1094         case MXC_AHB_CLK:
1095                 return get_ahb_clk();
1096         case MXC_IPG_CLK:
1097                 return get_ipg_clk();
1098         case MXC_IPG_PERCLK:
1099         case MXC_I2C_CLK:
1100                 return get_ipg_per_clk();
1101         case MXC_UART_CLK:
1102                 return get_uart_clk();
1103         case MXC_CSPI_CLK:
1104                 return get_cspi_clk();
1105         case MXC_AXI_CLK:
1106                 return get_axi_clk();
1107         case MXC_EMI_SLOW_CLK:
1108                 return get_emi_slow_clk();
1109         case MXC_DDR_CLK:
1110                 return get_mmdc_ch0_clk();
1111         case MXC_ESDHC_CLK:
1112                 return get_usdhc_clk(0);
1113         case MXC_ESDHC2_CLK:
1114                 return get_usdhc_clk(1);
1115         case MXC_ESDHC3_CLK:
1116                 return get_usdhc_clk(2);
1117         case MXC_ESDHC4_CLK:
1118                 return get_usdhc_clk(3);
1119         case MXC_SATA_CLK:
1120                 return get_ahb_clk();
1121         case MXC_NFC_CLK:
1122                 return get_nfc_clk();
1123         default:
1124                 printf("Unsupported MXC CLK: %d\n", clk);
1125         }
1126
1127         return 0;
1128 }
1129
1130 static inline int gcd(int m, int n)
1131 {
1132         int t;
1133         while (m > 0) {
1134                 if (n > m) {
1135                         t = m;
1136                         m = n;
1137                         n = t;
1138                 } /* swap */
1139                 m -= n;
1140         }
1141         return n;
1142 }
1143
1144 /* Config CPU clock */
1145 static int set_arm_clk(u32 ref, u32 freq_khz)
1146 {
1147         int d;
1148         int div = 0;
1149         int mul = 0;
1150         u32 min_err = ~0;
1151         u32 reg;
1152
1153         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1154                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1155                         freq_khz / 1000, freq_khz % 1000,
1156                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1157                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1158                 return -EINVAL;
1159         }
1160
1161         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1162                 int m = freq_khz * 2 * d / (ref / 1000);
1163                 u32 f;
1164                 u32 err;
1165
1166                 if (m > 108) {
1167                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1168                                 d, m);
1169                         break;
1170                 }
1171
1172                 f = ref * m / d / 2;
1173                 if (f > freq_khz * 1000) {
1174                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1175                                 d, m, f, freq_khz);
1176                         if (--m < 54)
1177                                 return -EINVAL;
1178                         f = ref * m / d / 2;
1179                 }
1180                 err = freq_khz * 1000 - f;
1181                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1182                         d, m, f, freq_khz, err);
1183                 if (err < min_err) {
1184                         mul = m;
1185                         div = d;
1186                         min_err = err;
1187                         if (err == 0)
1188                                 break;
1189                 }
1190         }
1191         if (min_err == ~0)
1192                 return -EINVAL;
1193         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1194                 mul, div, freq_khz / 1000, freq_khz % 1000,
1195                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1196
1197         reg = readl(&anatop->pll_arm);
1198         debug("anadig_pll_arm=%08x -> %08x\n",
1199                 reg, (reg & ~0x7f) | mul);
1200
1201         reg |= 1 << 16;
1202         writel(reg, &anatop->pll_arm); /* bypass PLL */
1203
1204         reg = (reg & ~0x7f) | mul;
1205         writel(reg, &anatop->pll_arm);
1206
1207         writel(div - 1, &imx_ccm->cacrr);
1208
1209         reg &= ~(1 << 16);
1210         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1211
1212         return 0;
1213 }
1214
1215 /*
1216  * This function assumes the expected core clock has to be changed by
1217  * modifying the PLL. This is NOT true always but for most of the times,
1218  * it is. So it assumes the PLL output freq is the same as the expected
1219  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1220  * In the latter case, it will try to increase the presc value until
1221  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1222  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1223  * on the targeted PLL and reference input clock to the PLL. Lastly,
1224  * it sets the register based on these values along with the dividers.
1225  * Note 1) There is no value checking for the passed-in divider values
1226  *         so the caller has to make sure those values are sensible.
1227  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1228  *         exceed NFC_CLK_MAX.
1229  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1230  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1231  *      4) This function should not have allowed diag_printf() calls since
1232  *         the serial driver has been stoped. But leave then here to allow
1233  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1234  */
1235 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1236 {
1237         int ret;
1238
1239         freq *= 1000;
1240
1241         switch (clk) {
1242         case MXC_ARM_CLK:
1243                 ret = set_arm_clk(ref, freq);
1244                 break;
1245
1246         case MXC_NFC_CLK:
1247                 ret = set_nfc_clk(ref, freq);
1248                 break;
1249
1250         default:
1251                 printf("Warning: Unsupported or invalid clock type: %d\n",
1252                         clk);
1253                 return -EINVAL;
1254         }
1255
1256         return ret;
1257 }
1258
1259 /*
1260  * Dump some core clocks.
1261  */
1262 #define print_pll(pll)  {                               \
1263         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1264         printf("%-12s %4d.%03d MHz\n", #pll,            \
1265                 __pll / 1000000, __pll / 1000 % 1000);  \
1266         }
1267
1268 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1269
1270 #define print_clk(clk)  {                               \
1271         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1272         printf("%-12s %4d.%03d MHz\n", #clk,            \
1273                 __clk / 1000000, __clk / 1000 % 1000);  \
1274         }
1275
1276 #define print_pfd(pll, pfd)     {                                       \
1277         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1278         if (__pfd & (0x80 << 8 * pfd)) {                                \
1279                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1280         } else {                                                        \
1281                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1282                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1283                         pll * 18 / __pfd,                               \
1284                         pll * 18 * 1000 / __pfd % 1000);                \
1285         }                                                               \
1286 }
1287
1288 static void do_mx6_showclocks(void)
1289 {
1290         print_pll(PLL_ARM);
1291         print_pll(PLL_528);
1292         print_pll(PLL_USBOTG);
1293         print_pll(PLL_AUDIO);
1294         print_pll(PLL_VIDEO);
1295         print_pll(PLL_ENET);
1296         print_pll(PLL_USB2);
1297         printf("\n");
1298
1299         print_pfd(480, 0);
1300         print_pfd(480, 1);
1301         print_pfd(480, 2);
1302         print_pfd(480, 3);
1303         print_pfd(528, 0);
1304         print_pfd(528, 1);
1305         print_pfd(528, 2);
1306         printf("\n");
1307
1308         print_clk(IPG);
1309         print_clk(UART);
1310         print_clk(CSPI);
1311         print_clk(AHB);
1312         print_clk(AXI);
1313         print_clk(DDR);
1314         print_clk(ESDHC);
1315         print_clk(ESDHC2);
1316         print_clk(ESDHC3);
1317         print_clk(ESDHC4);
1318         print_clk(EMI_SLOW);
1319         print_clk(NFC);
1320         print_clk(IPG_PER);
1321         print_clk(ARM);
1322 }
1323
1324 static struct clk_lookup {
1325         const char *name;
1326         unsigned int index;
1327 } mx6_clk_lookup[] = {
1328         { "arm", MXC_ARM_CLK, },
1329         { "nfc", MXC_NFC_CLK, },
1330 };
1331
1332 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1333 {
1334         int i;
1335         unsigned long freq;
1336         unsigned long ref = ~0UL;
1337
1338         if (argc < 2) {
1339                 do_mx6_showclocks();
1340                 return CMD_RET_SUCCESS;
1341         } else if (argc == 2 || argc > 4) {
1342                 return CMD_RET_USAGE;
1343         }
1344
1345         freq = simple_strtoul(argv[2], NULL, 0);
1346         if (freq == 0) {
1347                 printf("Invalid clock frequency %lu\n", freq);
1348                 return CMD_RET_FAILURE;
1349         }
1350         if (argc > 3) {
1351                 ref = simple_strtoul(argv[3], NULL, 0);
1352         }
1353         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1354                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1355                         switch (mx6_clk_lookup[i].index) {
1356                         case MXC_ARM_CLK:
1357                                 if (argc > 3)
1358                                         return CMD_RET_USAGE;
1359                                 ref = MXC_HCLK;
1360                                 break;
1361
1362                         case MXC_NFC_CLK:
1363                                 if (argc > 3 && ref > 3) {
1364                                         printf("Invalid clock selector value: %lu\n", ref);
1365                                         return CMD_RET_FAILURE;
1366                                 }
1367                                 break;
1368                         }
1369                         printf("Setting %s clock to %lu MHz\n",
1370                                 mx6_clk_lookup[i].name, freq);
1371                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1372                                 break;
1373                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1374                         printf("%s clock set to %lu.%03lu MHz\n",
1375                                 mx6_clk_lookup[i].name,
1376                                 freq / 1000000, freq / 1000 % 1000);
1377                         return CMD_RET_SUCCESS;
1378                 }
1379         }
1380         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1381                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1382                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1383                         printf("\t%s\n", mx6_clk_lookup[i].name);
1384                 }
1385         } else {
1386                 printf("Failed to set clock %s to %s MHz\n",
1387                         argv[1], argv[2]);
1388         }
1389         return CMD_RET_FAILURE;
1390 }
1391
1392 #ifndef CONFIG_SOC_MX6SX
1393 void enable_ipu_clock(void)
1394 {
1395         int reg = readl(&imx_ccm->CCGR3);
1396         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1397         writel(reg, &imx_ccm->CCGR3);
1398
1399         if (is_mx6dqp()) {
1400                 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1401                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1402         }
1403 }
1404 #endif
1405 /***************************************************/
1406
1407 U_BOOT_CMD(
1408         clocks, 4, 0, do_clocks,
1409         "display/set clocks",
1410         "                    - display clock settings\n"
1411         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1412 );