c9f604e3ab7f141e33eb058936e6cb848c7146c3
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17         PLL_ARM,        /* PLL1: ARM PLL */
18         PLL_528,        /* PLL2: System Bus PLL*/
19         PLL_USBOTG,     /* PLL3: OTG USB PLL */
20         PLL_AUDIO,      /* PLL4: Audio PLL */
21         PLL_VIDEO,      /* PLL5: Video PLL */
22         PLL_ENET,       /* PLL6: ENET PLL */
23         PLL_USB2,       /* PLL7: USB2 PLL */
24         PLL_MLB,        /* PLL8: MLB PLL */
25 };
26
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
29
30 int clk_enable(struct clk *clk)
31 {
32         int ret = 0;
33
34         if (!clk)
35                 return 0;
36         if (clk->usecount == 0) {
37                 debug("%s: Enabling %s clock\n", __func__, clk->name);
38                 ret = clk->enable(clk);
39                 if (ret)
40                         return ret;
41                 clk->usecount++;
42         }
43         assert(clk->usecount > 0);
44         return ret;
45 }
46
47 void clk_disable(struct clk *clk)
48 {
49         if (!clk)
50                 return;
51
52         assert(clk->usecount > 0);
53         if (!(--clk->usecount)) {
54                 if (clk->disable) {
55                         debug("%s: Disabling %s clock\n", __func__, clk->name);
56                         clk->disable(clk);
57                 }
58         }
59 }
60
61 int clk_get_usecount(struct clk *clk)
62 {
63         if (clk == NULL)
64                 return 0;
65
66         return clk->usecount;
67 }
68
69 u32 clk_get_rate(struct clk *clk)
70 {
71         if (!clk)
72                 return 0;
73
74         return clk->rate;
75 }
76
77 struct clk *clk_get_parent(struct clk *clk)
78 {
79         if (!clk)
80                 return 0;
81
82         return clk->parent;
83 }
84
85 int clk_set_rate(struct clk *clk, unsigned long rate)
86 {
87         if (clk && clk->set_rate)
88                 clk->set_rate(clk, rate);
89         return clk->rate;
90 }
91
92 long clk_round_rate(struct clk *clk, unsigned long rate)
93 {
94         if (clk == NULL || !clk->round_rate)
95                 return 0;
96
97         return clk->round_rate(clk, rate);
98 }
99
100 int clk_set_parent(struct clk *clk, struct clk *parent)
101 {
102         debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103                 clk ? clk->parent : NULL);
104
105         if (!clk || clk == parent)
106                 return 0;
107
108         if (clk->set_parent) {
109                 int ret;
110
111                 ret = clk->set_parent(clk, parent);
112                 if (ret)
113                         return ret;
114         }
115         clk->parent = parent;
116         return 0;
117 }
118
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
121 {
122         u32 reg;
123
124         reg = __raw_readl(&imx_ccm->CCGR2);
125         if (enable)
126                 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
127         else
128                 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129         __raw_writel(reg, &imx_ccm->CCGR2);
130 }
131 #endif
132
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
135 {
136         /* Disable clocks per ERR007177 from MX6 errata */
137         clrbits_le32(&imx_ccm->CCGR4,
138                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
143
144         clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
145
146         clrsetbits_le32(&imx_ccm->cs2cdr,
147                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
150                         cfg);
151
152         setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153         setbits_le32(&imx_ccm->CCGR4,
154                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
159 }
160 #endif
161
162 void enable_usboh3_clk(unsigned char enable)
163 {
164         u32 reg;
165
166         reg = __raw_readl(&imx_ccm->CCGR6);
167         if (enable)
168                 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
169         else
170                 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171         __raw_writel(reg, &imx_ccm->CCGR6);
172
173 }
174
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
177 {
178         u32 mask, *addr;
179
180         if (is_cpu_type(MXC_CPU_MX6UL)) {
181                 mask = MXC_CCM_CCGR3_ENET_MASK;
182                 addr = &imx_ccm->CCGR3;
183         } else {
184                 mask = MXC_CCM_CCGR1_ENET_MASK;
185                 addr = &imx_ccm->CCGR1;
186         }
187
188         if (enable)
189                 setbits_le32(addr, mask);
190         else
191                 clrbits_le32(addr, mask);
192 }
193 #endif
194
195 #ifdef CONFIG_MXC_UART
196 void enable_uart_clk(unsigned char enable)
197 {
198         u32 mask;
199
200         if (is_cpu_type(MXC_CPU_MX6UL))
201                 mask = MXC_CCM_CCGR5_UART_MASK;
202         else
203                 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
204
205         if (enable)
206                 setbits_le32(&imx_ccm->CCGR5, mask);
207         else
208                 clrbits_le32(&imx_ccm->CCGR5, mask);
209 }
210 #endif
211
212 #ifdef CONFIG_MMC
213 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
214 {
215         u32 mask;
216
217         if (bus_num > 3)
218                 return -EINVAL;
219
220         mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
221         if (enable)
222                 setbits_le32(&imx_ccm->CCGR6, mask);
223         else
224                 clrbits_le32(&imx_ccm->CCGR6, mask);
225
226         return 0;
227 }
228 #endif
229
230 #ifdef CONFIG_SYS_I2C_MXC
231 /* i2c_num can be from 0 - 3 */
232 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
233 {
234         u32 reg;
235         u32 mask;
236         u32 *addr;
237
238         if (i2c_num > 3)
239                 return -EINVAL;
240         if (i2c_num < 3) {
241                 mask = MXC_CCM_CCGR_CG_MASK
242                         << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
243                         + (i2c_num << 1));
244                 reg = __raw_readl(&imx_ccm->CCGR2);
245                 if (enable)
246                         reg |= mask;
247                 else
248                         reg &= ~mask;
249                 __raw_writel(reg, &imx_ccm->CCGR2);
250         } else {
251                 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
252                         mask = MXC_CCM_CCGR6_I2C4_MASK;
253                         addr = &imx_ccm->CCGR6;
254                 } else {
255                         mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
256                         addr = &imx_ccm->CCGR1;
257                 }
258                 reg = __raw_readl(addr);
259                 if (enable)
260                         reg |= mask;
261                 else
262                         reg &= ~mask;
263                 __raw_writel(reg, addr);
264         }
265         return 0;
266 }
267 #endif
268
269 /* spi_num can be from 0 - SPI_MAX_NUM */
270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
271 {
272         u32 reg;
273         u32 mask;
274
275         if (spi_num > SPI_MAX_NUM)
276                 return -EINVAL;
277
278         mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
279         reg = __raw_readl(&imx_ccm->CCGR1);
280         if (enable)
281                 reg |= mask;
282         else
283                 reg &= ~mask;
284         __raw_writel(reg, &imx_ccm->CCGR1);
285         return 0;
286 }
287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
288 {
289         u32 div;
290
291         switch (pll) {
292         case PLL_ARM:
293                 div = __raw_readl(&anatop->pll_arm);
294                 if (div & BM_ANADIG_PLL_ARM_BYPASS)
295                         /* Assume the bypass clock is always derived from OSC */
296                         return infreq;
297                 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
298
299                 return infreq * div / 2;
300         case PLL_528:
301                 div = __raw_readl(&anatop->pll_528);
302                 if (div & BM_ANADIG_PLL_528_BYPASS)
303                         return infreq;
304                 div &= BM_ANADIG_PLL_528_DIV_SELECT;
305
306                 return infreq * (20 + div * 2);
307         case PLL_USBOTG:
308                 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
309                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
310                         return infreq;
311                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
312
313                 return infreq * (20 + div * 2);
314         case PLL_AUDIO:
315                 div = __raw_readl(&anatop->pll_audio);
316                 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
317                         return infreq;
318                 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
319
320                 return infreq * div;
321         case PLL_VIDEO:
322                 div = __raw_readl(&anatop->pll_video);
323                 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
324                         return infreq;
325                 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
326
327                 return infreq * div;
328         case PLL_ENET:
329                 div = __raw_readl(&anatop->pll_enet);
330                 if (div & BM_ANADIG_PLL_ENET_BYPASS)
331                         return infreq;
332                 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
333
334                 return 25000000 * (div + (div >> 1) + 1);
335         case PLL_USB2:
336                 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
337                 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
338                         return infreq;
339                 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
340
341                 return infreq * (20 + div * 2);
342         case PLL_MLB:
343                 div = __raw_readl(&anatop->pll_mlb);
344                 if (div & BM_ANADIG_PLL_MLB_BYPASS)
345                         return infreq;
346                 /* unknown external clock provided on MLB_CLK pin */
347                 return 0;
348         }
349         return 0;
350 }
351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
352 {
353         u32 div;
354         u64 freq;
355         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
356
357         switch (pll) {
358         case PLL_528:
359                 if (!is_cpu_type(MXC_CPU_MX6UL)) {
360                         if (pfd_num == 3) {
361                                 /* No PFD3 on PPL2 */
362                                 return 0;
363                         }
364                 }
365                 div = __raw_readl(&anatop->pfd_528);
366                 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
367                 break;
368         case PLL_USBOTG:
369                 div = __raw_readl(&anatop->pfd_480);
370                 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
371                 break;
372         default:
373                 /* No PFD on other PLL */
374                 return 0;
375         }
376
377         return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
378                               ANATOP_PFD_FRAC_SHIFT(pfd_num));
379 }
380
381 static u32 get_mcu_main_clk(void)
382 {
383         u32 reg, freq;
384
385         reg = __raw_readl(&imx_ccm->cacrr);
386         reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
387         reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
388         freq = decode_pll(PLL_ARM, MXC_HCLK);
389
390         return freq / (reg + 1);
391 }
392
393 u32 get_periph_clk(void)
394 {
395         u32 reg, div = 0, freq = 0;
396
397         reg = __raw_readl(&imx_ccm->cbcdr);
398         if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
399                 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
400                        MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
401                 reg = __raw_readl(&imx_ccm->cbcmr);
402                 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
403                 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
404
405                 switch (reg) {
406                 case 0:
407                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
408                         break;
409                 case 1:
410                 case 2:
411                         freq = MXC_HCLK;
412                         break;
413                 }
414         } else {
415                 reg = __raw_readl(&imx_ccm->cbcmr);
416                 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
417                 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
418
419                 switch (reg) {
420                 case 0:
421                         freq = decode_pll(PLL_528, MXC_HCLK);
422                         break;
423                 case 1:
424                         freq = mxc_get_pll_pfd(PLL_528, 2);
425                         break;
426                 case 2:
427                         freq = mxc_get_pll_pfd(PLL_528, 0);
428                         break;
429                 case 3:
430                         /* static / 2 divider */
431                         freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
432                         break;
433                 }
434         }
435
436         return freq / (div + 1);
437 }
438
439 static u32 get_ipg_clk(void)
440 {
441         u32 reg, ipg_podf;
442
443         reg = __raw_readl(&imx_ccm->cbcdr);
444         reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
445         ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
446
447         return get_ahb_clk() / (ipg_podf + 1);
448 }
449
450 static u32 get_ipg_per_clk(void)
451 {
452         u32 reg, perclk_podf;
453
454         reg = __raw_readl(&imx_ccm->cscmr1);
455         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
456             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
457                 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
458                         return MXC_HCLK; /* OSC 24Mhz */
459         }
460
461         perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
462
463         return get_ipg_clk() / (perclk_podf + 1);
464 }
465
466 static u32 get_uart_clk(void)
467 {
468         u32 reg, uart_podf;
469         u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
470         reg = __raw_readl(&imx_ccm->cscdr1);
471
472         if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
473             is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
474                 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
475                         freq = MXC_HCLK;
476         }
477
478         reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
479         uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
480
481         return freq / (uart_podf + 1);
482 }
483
484 static u32 get_cspi_clk(void)
485 {
486         u32 reg, cspi_podf;
487
488         reg = __raw_readl(&imx_ccm->cscdr2);
489         cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
490                      MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
491
492         if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
493             is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
494                 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
495                         return MXC_HCLK / (cspi_podf + 1);
496         }
497
498         return  decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
499 }
500
501 static u32 get_axi_clk(void)
502 {
503         u32 root_freq, axi_podf;
504         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
505
506         axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
507         axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
508
509         if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
510                 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
511                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
512                 else
513                         root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
514         } else {
515                 root_freq = get_periph_clk();
516         }
517         return  root_freq / (axi_podf + 1);
518 }
519
520 static u32 get_emi_slow_clk(void)
521 {
522         u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
523
524         cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
525         emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
526         emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
527         emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
528         emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
529
530         switch (emi_clk_sel) {
531         case 0:
532                 root_freq = get_axi_clk();
533                 break;
534         case 1:
535                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
536                 break;
537         case 2:
538                 root_freq =  mxc_get_pll_pfd(PLL_528, 2);
539                 break;
540         case 3:
541                 root_freq =  mxc_get_pll_pfd(PLL_528, 0);
542                 break;
543         }
544
545         return root_freq / (emi_slow_podf + 1);
546 }
547
548 static u32 get_nfc_clk(void)
549 {
550         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
551         u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
552         u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
553         int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
554                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
555         u32 root_freq;
556
557         switch (nfc_clk_sel) {
558         case 0:
559                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
560                 break;
561         case 1:
562                 root_freq = decode_pll(PLL_528, MXC_HCLK);
563                 break;
564         case 2:
565                 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
566                 break;
567         case 3:
568                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
569                 break;
570         default:
571                 return 0;
572         }
573
574         return root_freq / (pred + 1) / (podf + 1);
575 }
576
577 #define CS2CDR_ENFC_MASK        (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |    \
578                                 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |     \
579                                 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
580
581 static int set_nfc_clk(u32 ref, u32 freq_khz)
582 {
583         u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
584         u32 podf;
585         u32 pred;
586         int nfc_clk_sel;
587         u32 root_freq;
588         u32 min_err = ~0;
589         u32 nfc_val = ~0;
590         u32 freq = freq_khz * 1000;
591
592         for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
593                 u32 act_freq;
594                 u32 err;
595
596                 if (ref < 4 && ref != nfc_clk_sel)
597                         continue;
598
599                 switch (nfc_clk_sel) {
600                 case 0:
601                         root_freq = mxc_get_pll_pfd(PLL_528, 0);
602                         break;
603                 case 1:
604                         root_freq = decode_pll(PLL_528, MXC_HCLK);
605                         break;
606                 case 2:
607                         root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
608                         break;
609                 case 3:
610                         root_freq = mxc_get_pll_pfd(PLL_528, 2);
611                         break;
612                 }
613                 if (root_freq < freq)
614                         continue;
615
616                 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
617                 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
618                 act_freq = root_freq / pred / podf;
619                 err = (freq - act_freq) * 100 / freq;
620                 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
621                         nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
622                 if (act_freq > freq)
623                         continue;
624                 if (err < min_err) {
625                         nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
626                         nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
627                         nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
628                         min_err = err;
629                         if (err == 0)
630                                 break;
631                 }
632         }
633
634         if (nfc_val == ~0 || min_err > 10)
635                 return -EINVAL;
636
637         if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
638                 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
639                         (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
640                 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
641                         &imx_ccm->cs2cdr);
642         } else {
643                 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
644         }
645         return 0;
646 }
647
648 static u32 get_mmdc_ch0_clk(void)
649 {
650         u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
651         u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
652
653         u32 freq, podf, per2_clk2_podf;
654
655         if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
656             is_cpu_type(MXC_CPU_MX6SL)) {
657                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
658                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
659                 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
660                         per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
661                                 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
662                         if (is_cpu_type(MXC_CPU_MX6SL)) {
663                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
664                                         freq = MXC_HCLK;
665                                 else
666                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
667                         } else {
668                                 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
669                                         freq = decode_pll(PLL_528, MXC_HCLK);
670                                 else
671                                         freq = decode_pll(PLL_USBOTG, MXC_HCLK);
672                         }
673                 } else {
674                         per2_clk2_podf = 0;
675                         switch ((cbcmr &
676                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
677                                 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
678                         case 0:
679                                 freq = decode_pll(PLL_528, MXC_HCLK);
680                                 break;
681                         case 1:
682                                 freq = mxc_get_pll_pfd(PLL_528, 2);
683                                 break;
684                         case 2:
685                                 freq = mxc_get_pll_pfd(PLL_528, 0);
686                                 break;
687                         case 3:
688                                 /* static / 2 divider */
689                                 freq =  mxc_get_pll_pfd(PLL_528, 2) / 2;
690                                 break;
691                         }
692                 }
693                 return freq / (podf + 1) / (per2_clk2_podf + 1);
694         } else {
695                 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
696                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
697                 return get_periph_clk() / (podf + 1);
698         }
699 }
700
701 #ifdef CONFIG_FSL_QSPI
702 /* qspi_num can be from 0 - 1 */
703 void enable_qspi_clk(int qspi_num)
704 {
705         u32 reg = 0;
706         /* Enable QuadSPI clock */
707         switch (qspi_num) {
708         case 0:
709                 /* disable the clock gate */
710                 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
711
712                 /* set 50M  : (50 = 396 / 2 / 4) */
713                 reg = readl(&imx_ccm->cscmr1);
714                 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
715                          MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
716                 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
717                         (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
718                 writel(reg, &imx_ccm->cscmr1);
719
720                 /* enable the clock gate */
721                 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
722                 break;
723         case 1:
724                 /*
725                  * disable the clock gate
726                  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
727                  * disable both of them.
728                  */
729                 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
730                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
731
732                 /* set 50M  : (50 = 396 / 2 / 4) */
733                 reg = readl(&imx_ccm->cs2cdr);
734                 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
735                          MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
736                          MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
737                 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
738                         MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
739                 writel(reg, &imx_ccm->cs2cdr);
740
741                 /*enable the clock gate*/
742                 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
743                              MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
744                 break;
745         default:
746                 break;
747         }
748 }
749 #endif
750
751 #ifdef CONFIG_FEC_MXC
752 int enable_fec_anatop_clock(enum enet_freq freq)
753 {
754         u32 reg = 0;
755         s32 timeout = 100000;
756
757         struct anatop_regs __iomem *anatop =
758                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
759
760         if (freq < ENET_25MHZ || freq > ENET_125MHZ)
761                 return -EINVAL;
762
763         reg = readl(&anatop->pll_enet);
764         reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
765         reg |= freq;
766
767         if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
768             (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
769                 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
770                 writel(reg, &anatop->pll_enet);
771                 while (timeout--) {
772                         if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
773                                 break;
774                 }
775                 if (timeout < 0)
776                         return -ETIMEDOUT;
777         }
778
779         /* Enable FEC clock */
780         reg |= BM_ANADIG_PLL_ENET_ENABLE;
781         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
782         writel(reg, &anatop->pll_enet);
783
784 #ifdef CONFIG_SOC_MX6SX
785         /*
786          * Set enet ahb clock to 200MHz
787          * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
788          */
789         reg = readl(&imx_ccm->chsccdr);
790         reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
791                  | MXC_CCM_CHSCCDR_ENET_PODF_MASK
792                  | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
793         /* PLL2 PFD2 */
794         reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
795         /* Div = 2*/
796         reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
797         reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
798         writel(reg, &imx_ccm->chsccdr);
799
800         /* Enable enet system clock */
801         reg = readl(&imx_ccm->CCGR3);
802         reg |= MXC_CCM_CCGR3_ENET_MASK;
803         writel(reg, &imx_ccm->CCGR3);
804 #endif
805         return 0;
806 }
807 #endif
808
809 static u32 get_usdhc_clk(u32 port)
810 {
811         u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
812         u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
813         u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
814
815         switch (port) {
816         case 0:
817                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
818                                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
819                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
820
821                 break;
822         case 1:
823                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
824                                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
825                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
826
827                 break;
828         case 2:
829                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
830                                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
831                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
832
833                 break;
834         case 3:
835                 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
836                                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
837                 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
838
839                 break;
840         default:
841                 break;
842         }
843
844         if (clk_sel)
845                 root_freq = mxc_get_pll_pfd(PLL_528, 0);
846         else
847                 root_freq = mxc_get_pll_pfd(PLL_528, 2);
848
849         return root_freq / (usdhc_podf + 1);
850 }
851
852 u32 imx_get_uartclk(void)
853 {
854         return get_uart_clk();
855 }
856
857 u32 imx_get_fecclk(void)
858 {
859         return mxc_get_clock(MXC_IPG_CLK);
860 }
861
862 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
863 static int enable_enet_pll(uint32_t en)
864 {
865         u32 reg;
866         s32 timeout = 100000;
867
868         /* Enable PLLs */
869         reg = readl(&anatop->pll_enet);
870         reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
871         writel(reg, &anatop->pll_enet);
872         reg |= BM_ANADIG_PLL_ENET_ENABLE;
873         while (timeout--) {
874                 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
875                         break;
876         }
877         if (timeout <= 0)
878                 return -EIO;
879         reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
880         writel(reg, &anatop->pll_enet);
881         reg |= en;
882         writel(reg, &anatop->pll_enet);
883         return 0;
884 }
885 #endif
886
887 #ifdef CONFIG_CMD_SATA
888 static void ungate_sata_clock(void)
889 {
890         struct mxc_ccm_reg *const imx_ccm =
891                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
892
893         /* Enable SATA clock. */
894         setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
895 }
896
897 int enable_sata_clock(void)
898 {
899         ungate_sata_clock();
900         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
901 }
902
903 void disable_sata_clock(void)
904 {
905         struct mxc_ccm_reg *const imx_ccm =
906                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
907
908         clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
909 }
910 #endif
911
912 #ifdef CONFIG_PCIE_IMX
913 static void ungate_pcie_clock(void)
914 {
915         struct mxc_ccm_reg *const imx_ccm =
916                 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
917
918         /* Enable PCIe clock. */
919         setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
920 }
921
922 int enable_pcie_clock(void)
923 {
924         struct anatop_regs *anatop_regs =
925                 (struct anatop_regs *)ANATOP_BASE_ADDR;
926         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
927         u32 lvds1_clk_sel;
928
929         /*
930          * Here be dragons!
931          *
932          * The register ANATOP_MISC1 is not documented in the Freescale
933          * MX6RM. The register that is mapped in the ANATOP space and
934          * marked as ANATOP_MISC1 is actually documented in the PMU section
935          * of the datasheet as PMU_MISC1.
936          *
937          * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
938          * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
939          * for PCI express link that is clocked from the i.MX6.
940          */
941 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN          (1 << 12)
942 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN          (1 << 10)
943 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK     0x0000001F
944 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
945 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
946
947         if (is_cpu_type(MXC_CPU_MX6SX))
948                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
949         else
950                 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
951
952         clrsetbits_le32(&anatop_regs->ana_misc1,
953                         ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
954                         ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
955                         ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
956
957         /* PCIe reference clock sourced from AXI. */
958         clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
959
960         /* Party time! Ungate the clock to the PCIe. */
961 #ifdef CONFIG_CMD_SATA
962         ungate_sata_clock();
963 #endif
964         ungate_pcie_clock();
965
966         return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
967                                BM_ANADIG_PLL_ENET_ENABLE_PCIE);
968 }
969 #endif
970
971 #ifdef CONFIG_SECURE_BOOT
972 void hab_caam_clock_enable(unsigned char enable)
973 {
974         u32 reg;
975
976         /* CG4 ~ CG6, CAAM clocks */
977         reg = __raw_readl(&imx_ccm->CCGR0);
978         if (enable)
979                 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
980                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
981                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
982         else
983                 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
984                         MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
985                         MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
986         __raw_writel(reg, &imx_ccm->CCGR0);
987
988         /* EMI slow clk */
989         reg = __raw_readl(&imx_ccm->CCGR6);
990         if (enable)
991                 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
992         else
993                 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
994         __raw_writel(reg, &imx_ccm->CCGR6);
995 }
996 #endif
997
998 static void enable_pll3(void)
999 {
1000         struct anatop_regs __iomem *anatop =
1001                 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
1002
1003         /* make sure pll3 is enabled */
1004         if ((readl(&anatop->usb1_pll_480_ctrl) &
1005                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
1006                 /* enable pll's power */
1007                 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
1008                        &anatop->usb1_pll_480_ctrl_set);
1009                 writel(0x80, &anatop->ana_misc2_clr);
1010                 /* wait for pll lock */
1011                 while ((readl(&anatop->usb1_pll_480_ctrl) &
1012                         BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
1013                         ;
1014                 /* disable bypass */
1015                 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
1016                        &anatop->usb1_pll_480_ctrl_clr);
1017                 /* enable pll output */
1018                 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1019                        &anatop->usb1_pll_480_ctrl_set);
1020         }
1021 }
1022
1023 void enable_thermal_clk(void)
1024 {
1025         enable_pll3();
1026 }
1027
1028 void ipu_clk_enable(void)
1029 {
1030         u32 reg = readl(&imx_ccm->CCGR3);
1031         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1032         writel(reg, &imx_ccm->CCGR3);
1033 }
1034
1035 void ipu_clk_disable(void)
1036 {
1037         u32 reg = readl(&imx_ccm->CCGR3);
1038         reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1039         writel(reg, &imx_ccm->CCGR3);
1040 }
1041
1042 void ipu_di_clk_enable(int di)
1043 {
1044         switch (di) {
1045         case 0:
1046                 setbits_le32(&imx_ccm->CCGR3,
1047                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1048                 break;
1049         case 1:
1050                 setbits_le32(&imx_ccm->CCGR3,
1051                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1052                 break;
1053         default:
1054                 printf("%s: Invalid DI index %d\n", __func__, di);
1055         }
1056 }
1057
1058 void ipu_di_clk_disable(int di)
1059 {
1060         switch (di) {
1061         case 0:
1062                 clrbits_le32(&imx_ccm->CCGR3,
1063                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1064                 break;
1065         case 1:
1066                 clrbits_le32(&imx_ccm->CCGR3,
1067                         MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1068                 break;
1069         default:
1070                 printf("%s: Invalid DI index %d\n", __func__, di);
1071         }
1072 }
1073
1074 void ldb_clk_enable(int ldb)
1075 {
1076         switch (ldb) {
1077         case 0:
1078                 setbits_le32(&imx_ccm->CCGR3,
1079                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1080                 break;
1081         case 1:
1082                 setbits_le32(&imx_ccm->CCGR3,
1083                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1084                 break;
1085         default:
1086                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1087         }
1088 }
1089
1090 void ldb_clk_disable(int ldb)
1091 {
1092         switch (ldb) {
1093         case 0:
1094                 clrbits_le32(&imx_ccm->CCGR3,
1095                         MXC_CCM_CCGR3_LDB_DI0_MASK);
1096                 break;
1097         case 1:
1098                 clrbits_le32(&imx_ccm->CCGR3,
1099                         MXC_CCM_CCGR3_LDB_DI1_MASK);
1100                 break;
1101         default:
1102                 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1103         }
1104 }
1105
1106 void ocotp_clk_enable(void)
1107 {
1108         u32 reg = readl(&imx_ccm->CCGR2);
1109         reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1110         writel(reg, &imx_ccm->CCGR2);
1111 }
1112
1113 void ocotp_clk_disable(void)
1114 {
1115         u32 reg = readl(&imx_ccm->CCGR2);
1116         reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1117         writel(reg, &imx_ccm->CCGR2);
1118 }
1119
1120 unsigned int mxc_get_clock(enum mxc_clock clk)
1121 {
1122         switch (clk) {
1123         case MXC_ARM_CLK:
1124                 return get_mcu_main_clk();
1125         case MXC_PER_CLK:
1126                 return get_periph_clk();
1127         case MXC_AHB_CLK:
1128                 return get_ahb_clk();
1129         case MXC_IPG_CLK:
1130                 return get_ipg_clk();
1131         case MXC_IPG_PERCLK:
1132         case MXC_I2C_CLK:
1133                 return get_ipg_per_clk();
1134         case MXC_UART_CLK:
1135                 return get_uart_clk();
1136         case MXC_CSPI_CLK:
1137                 return get_cspi_clk();
1138         case MXC_AXI_CLK:
1139                 return get_axi_clk();
1140         case MXC_EMI_SLOW_CLK:
1141                 return get_emi_slow_clk();
1142         case MXC_DDR_CLK:
1143                 return get_mmdc_ch0_clk();
1144         case MXC_ESDHC_CLK:
1145                 return get_usdhc_clk(0);
1146         case MXC_ESDHC2_CLK:
1147                 return get_usdhc_clk(1);
1148         case MXC_ESDHC3_CLK:
1149                 return get_usdhc_clk(2);
1150         case MXC_ESDHC4_CLK:
1151                 return get_usdhc_clk(3);
1152         case MXC_SATA_CLK:
1153                 return get_ahb_clk();
1154         case MXC_NFC_CLK:
1155                 return get_nfc_clk();
1156         default:
1157                 printf("Unsupported MXC CLK: %d\n", clk);
1158         }
1159
1160         return 0;
1161 }
1162
1163 static inline int gcd(int m, int n)
1164 {
1165         int t;
1166         while (m > 0) {
1167                 if (n > m) {
1168                         t = m;
1169                         m = n;
1170                         n = t;
1171                 } /* swap */
1172                 m -= n;
1173         }
1174         return n;
1175 }
1176
1177 /* Config CPU clock */
1178 static int set_arm_clk(u32 ref, u32 freq_khz)
1179 {
1180         int d;
1181         int div = 0;
1182         int mul = 0;
1183         u32 min_err = ~0;
1184         u32 reg;
1185
1186         if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1187                 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1188                         freq_khz / 1000, freq_khz % 1000,
1189                         54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1190                         108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1191                 return -EINVAL;
1192         }
1193
1194         for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1195                 int m = freq_khz * 2 * d / (ref / 1000);
1196                 u32 f;
1197                 u32 err;
1198
1199                 if (m > 108) {
1200                         debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1201                                 d, m);
1202                         break;
1203                 }
1204
1205                 f = ref * m / d / 2;
1206                 if (f > freq_khz * 1000) {
1207                         debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1208                                 d, m, f, freq_khz);
1209                         if (--m < 54)
1210                                 return -EINVAL;
1211                         f = ref * m / d / 2;
1212                 }
1213                 err = freq_khz * 1000 - f;
1214                 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1215                         d, m, f, freq_khz, err);
1216                 if (err < min_err) {
1217                         mul = m;
1218                         div = d;
1219                         min_err = err;
1220                         if (err == 0)
1221                                 break;
1222                 }
1223         }
1224         if (min_err == ~0)
1225                 return -EINVAL;
1226         debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1227                 mul, div, freq_khz / 1000, freq_khz % 1000,
1228                 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1229
1230         reg = readl(&anatop->pll_arm);
1231         debug("anadig_pll_arm=%08x -> %08x\n",
1232                 reg, (reg & ~0x7f) | mul);
1233
1234         reg |= 1 << 16;
1235         writel(reg, &anatop->pll_arm); /* bypass PLL */
1236
1237         reg = (reg & ~0x7f) | mul;
1238         writel(reg, &anatop->pll_arm);
1239
1240         writel(div - 1, &imx_ccm->cacrr);
1241
1242         reg &= ~(1 << 16);
1243         writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * This function assumes the expected core clock has to be changed by
1250  * modifying the PLL. This is NOT true always but for most of the times,
1251  * it is. So it assumes the PLL output freq is the same as the expected
1252  * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1253  * In the latter case, it will try to increase the presc value until
1254  * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1255  * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1256  * on the targeted PLL and reference input clock to the PLL. Lastly,
1257  * it sets the register based on these values along with the dividers.
1258  * Note 1) There is no value checking for the passed-in divider values
1259  *         so the caller has to make sure those values are sensible.
1260  *      2) Also adjust the NFC divider such that the NFC clock doesn't
1261  *         exceed NFC_CLK_MAX.
1262  *      3) IPU HSP clock is independent of AHB clock. Even it can go up to
1263  *         177MHz for higher voltage, this function fixes the max to 133MHz.
1264  *      4) This function should not have allowed diag_printf() calls since
1265  *         the serial driver has been stoped. But leave then here to allow
1266  *         easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1267  */
1268 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1269 {
1270         int ret;
1271
1272         freq *= 1000;
1273
1274         switch (clk) {
1275         case MXC_ARM_CLK:
1276                 ret = set_arm_clk(ref, freq);
1277                 break;
1278
1279         case MXC_NFC_CLK:
1280                 ret = set_nfc_clk(ref, freq);
1281                 break;
1282
1283         default:
1284                 printf("Warning: Unsupported or invalid clock type: %d\n",
1285                         clk);
1286                 return -EINVAL;
1287         }
1288
1289         return ret;
1290 }
1291
1292 /*
1293  * Dump some core clocks.
1294  */
1295 #define print_pll(pll)  {                               \
1296         u32 __pll = decode_pll(pll, MXC_HCLK);          \
1297         printf("%-12s %4d.%03d MHz\n", #pll,            \
1298                 __pll / 1000000, __pll / 1000 % 1000);  \
1299         }
1300
1301 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1302
1303 #define print_clk(clk)  {                               \
1304         u32 __clk = mxc_get_clock(MXC_##clk##_CLK);     \
1305         printf("%-12s %4d.%03d MHz\n", #clk,            \
1306                 __clk / 1000000, __clk / 1000 % 1000);  \
1307         }
1308
1309 #define print_pfd(pll, pfd)     {                                       \
1310         u32 __pfd = readl(&anatop->pfd_##pll);                          \
1311         if (__pfd & (0x80 << 8 * pfd)) {                                \
1312                 printf("PFD_%s[%d]      OFF\n", #pll, pfd);             \
1313         } else {                                                        \
1314                 __pfd = (__pfd >> 8 * pfd) & 0x3f;                      \
1315                 printf("PFD_%s[%d]   %4d.%03d MHz\n", #pll, pfd,        \
1316                         pll * 18 / __pfd,                               \
1317                         pll * 18 * 1000 / __pfd % 1000);                \
1318         }                                                               \
1319 }
1320
1321 static void do_mx6_showclocks(void)
1322 {
1323         print_pll(PLL_ARM);
1324         print_pll(PLL_528);
1325         print_pll(PLL_USBOTG);
1326         print_pll(PLL_AUDIO);
1327         print_pll(PLL_VIDEO);
1328         print_pll(PLL_ENET);
1329         print_pll(PLL_USB2);
1330         printf("\n");
1331
1332         print_pfd(480, 0);
1333         print_pfd(480, 1);
1334         print_pfd(480, 2);
1335         print_pfd(480, 3);
1336         print_pfd(528, 0);
1337         print_pfd(528, 1);
1338         print_pfd(528, 2);
1339         printf("\n");
1340
1341         print_clk(IPG);
1342         print_clk(UART);
1343         print_clk(CSPI);
1344         print_clk(AHB);
1345         print_clk(AXI);
1346         print_clk(DDR);
1347         print_clk(ESDHC);
1348         print_clk(ESDHC2);
1349         print_clk(ESDHC3);
1350         print_clk(ESDHC4);
1351         print_clk(EMI_SLOW);
1352         print_clk(NFC);
1353         print_clk(IPG_PER);
1354         print_clk(ARM);
1355 }
1356
1357 static struct clk_lookup {
1358         const char *name;
1359         unsigned int index;
1360 } mx6_clk_lookup[] = {
1361         { "arm", MXC_ARM_CLK, },
1362         { "nfc", MXC_NFC_CLK, },
1363 };
1364
1365 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1366 {
1367         int i;
1368         unsigned long freq;
1369         unsigned long ref = ~0UL;
1370
1371         if (argc < 2) {
1372                 do_mx6_showclocks();
1373                 return CMD_RET_SUCCESS;
1374         } else if (argc == 2 || argc > 4) {
1375                 return CMD_RET_USAGE;
1376         }
1377
1378         freq = simple_strtoul(argv[2], NULL, 0);
1379         if (freq == 0) {
1380                 printf("Invalid clock frequency %lu\n", freq);
1381                 return CMD_RET_FAILURE;
1382         }
1383         if (argc > 3) {
1384                 ref = simple_strtoul(argv[3], NULL, 0);
1385         }
1386         for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1387                 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1388                         switch (mx6_clk_lookup[i].index) {
1389                         case MXC_ARM_CLK:
1390                                 if (argc > 3)
1391                                         return CMD_RET_USAGE;
1392                                 ref = MXC_HCLK;
1393                                 break;
1394
1395                         case MXC_NFC_CLK:
1396                                 if (argc > 3 && ref > 3) {
1397                                         printf("Invalid clock selector value: %lu\n", ref);
1398                                         return CMD_RET_FAILURE;
1399                                 }
1400                                 break;
1401                         }
1402                         printf("Setting %s clock to %lu MHz\n",
1403                                 mx6_clk_lookup[i].name, freq);
1404                         if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1405                                 break;
1406                         freq = mxc_get_clock(mx6_clk_lookup[i].index);
1407                         printf("%s clock set to %lu.%03lu MHz\n",
1408                                 mx6_clk_lookup[i].name,
1409                                 freq / 1000000, freq / 1000 % 1000);
1410                         return CMD_RET_SUCCESS;
1411                 }
1412         }
1413         if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1414                 printf("clock %s not found; supported clocks are:\n", argv[1]);
1415                 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1416                         printf("\t%s\n", mx6_clk_lookup[i].name);
1417                 }
1418         } else {
1419                 printf("Failed to set clock %s to %s MHz\n",
1420                         argv[1], argv[2]);
1421         }
1422         return CMD_RET_FAILURE;
1423 }
1424
1425 #ifndef CONFIG_SOC_MX6SX
1426 void enable_ipu_clock(void)
1427 {
1428         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1429         int reg;
1430         reg = readl(&mxc_ccm->CCGR3);
1431         reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1432         writel(reg, &mxc_ccm->CCGR3);
1433
1434         if (is_mx6dqp()) {
1435                 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1436                 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1437         }
1438 }
1439 #endif
1440 /***************************************************/
1441
1442 U_BOOT_CMD(
1443         clocks, 4, 0, do_clocks,
1444         "display/set clocks",
1445         "                    - display clock settings\n"
1446         "clocks <clkname> <freq>    - set clock <clkname> to <freq> MHz"
1447 );