3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/regs-ocotp.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/imx-common/boot_mode.h>
19 #include <asm/imx-common/dma.h>
21 #ifdef CONFIG_VIDEO_IPUV3
25 DECLARE_GLOBAL_DATA_PTR;
27 #ifdef CONFIG_MX6_TEMPERATURE_MIN
28 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
30 #define TEMPERATURE_MIN (-40)
32 #ifdef CONFIG_MX6_TEMPERATURE_HOT
33 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
35 #define TEMPERATURE_HOT 80
37 #ifdef CONFIG_MX6_TEMPERATURE_MAX
38 #define TEMPERATURE_MAX CONFIG_MX6_TEMPERATURE_MAX
40 #define TEMPERATURE_MAX 125
42 #define TEMP_AVG_COUNT 5
43 #define TEMP_WARN_THRESHOLD 5
44 #define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40)
46 #define __data __attribute__((section(".data")))
56 #ifdef CONFIG_HW_WATCHDOG
57 #define wdog_base ((void *)WDOG1_BASE_ADDR)
59 #define WCR_WDE (1 << 2)
62 void hw_watchdog_reset(void)
64 if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
65 static u16 __data toggle = 0xaaaa;
66 static int __data first = 1;
69 printf("Watchdog active\n");
72 writew(toggle, wdog_base + WDOG_WSR);
80 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
81 u32 reg = readl(&anatop->digprog_sololite);
82 u32 type = ((reg >> 16) & 0xff);
84 if (type != MXC_CPU_MX6SL) {
85 reg = readl(&anatop->digprog);
86 type = ((reg >> 16) & 0xff);
87 if (type == MXC_CPU_MX6DL) {
88 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
89 u32 cfg = readl(&scu->config) & 3;
92 type = MXC_CPU_MX6SOLO;
95 reg &= 0xff; /* mx6 silicon revision */
96 return (type << 12) | (reg + 0x10);
99 #ifdef CONFIG_REVISION_TAG
100 u32 __weak get_board_rev(void)
102 u32 cpurev = get_cpu_rev();
103 u32 type = ((cpurev >> 12) & 0xff);
104 if (type == MXC_CPU_MX6SOLO)
105 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
113 struct aipstz_regs *aips1, *aips2;
115 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
116 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
119 * Set all MPROTx to be non-bufferable, trusted for R/W,
120 * not forced to user-mode.
122 writel(0x77777777, &aips1->mprot0);
123 writel(0x77777777, &aips1->mprot1);
124 writel(0x77777777, &aips2->mprot0);
125 writel(0x77777777, &aips2->mprot1);
128 * Set all OPACRx to be non-bufferable, not require
129 * supervisor privilege level for access,allow for
130 * write access and untrusted master access.
132 writel(0x00000000, &aips1->opacr0);
133 writel(0x00000000, &aips1->opacr1);
134 writel(0x00000000, &aips1->opacr2);
135 writel(0x00000000, &aips1->opacr3);
136 writel(0x00000000, &aips1->opacr4);
137 writel(0x00000000, &aips2->opacr0);
138 writel(0x00000000, &aips2->opacr1);
139 writel(0x00000000, &aips2->opacr2);
140 writel(0x00000000, &aips2->opacr3);
141 writel(0x00000000, &aips2->opacr4);
147 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
148 * them to the specified millivolt level.
149 * Possible values are from 0.725V to 1.450V in steps of
152 static void set_vddsoc(u32 mv)
154 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
155 u32 val, reg = readl(&anatop->reg_core);
158 val = 0x00; /* Power gated off */
160 val = 0x1F; /* Power FET switched full on. No regulation */
162 val = (mv - 700) / 25;
165 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
166 * and set them to the calculated value (0.7V + val * 0.25V)
168 reg = (reg & ~(0x1F << 18)) | (val << 18);
169 writel(reg, &anatop->reg_core);
172 static u32 __data thermal_calib;
174 int read_cpu_temperature(void)
176 unsigned int reg, tmp, i;
177 unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, ratio;
179 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
180 struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR;
182 if (!thermal_calib) {
184 writel(1, &ocotp_regs->hw_ocotp_read_ctrl);
185 thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1);
186 writel(0, &ocotp_regs->hw_ocotp_read_ctrl);
190 if (thermal_calib == 0 || thermal_calib == 0xffffffff)
191 return TEMPERATURE_MIN;
194 * [31:20] sensor value @ 25C
195 * [19:8] sensor value of hot
196 * [7:0] hot temperature value */
197 raw_25c = thermal_calib >> 20;
198 raw_hot = (thermal_calib & 0xfff00) >> 8;
199 hot_temp = thermal_calib & 0xff;
201 ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25);
202 raw_n40c = raw_25c + (13 * ratio) / 20;
204 /* now we only using single measure, every time we measure
205 * the temperature, we will power on/off the anadig module
207 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
208 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
210 /* write measure freq */
211 reg = readl(&anatop->tempsense1);
212 reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
214 writel(reg, &anatop->tempsense1);
216 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
217 writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
218 writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
221 /* read five times of temperature values to get average*/
222 for (i = 0; i < 5; i++) {
223 while ((readl(&anatop->tempsense0) &
224 BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
226 reg = readl(&anatop->tempsense0);
227 tmp += (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >>
228 BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
229 writel(BM_ANADIG_TEMPSENSE0_FINISHED,
230 &anatop->tempsense0_clr);
235 temperature = REG_VALUE_TO_CEL(ratio, tmp);
237 temperature = TEMPERATURE_MIN;
239 /* power down anatop thermal sensor */
240 writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
241 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
246 int check_cpu_temperature(int boot)
248 static int __data max_temp;
249 int boot_limit = getenv_ulong("max_boot_temp", 10, TEMPERATURE_HOT);
250 int tmp = read_cpu_temperature();
253 if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) {
254 printf("Temperature: can't get valid data!\n");
259 if (tmp > boot_limit) {
260 printf("CPU is %d C, too hot, resetting...\n", tmp);
264 if (tmp > max_temp) {
265 if (tmp > boot_limit - TEMP_WARN_THRESHOLD)
266 printf("WARNING: CPU temperature %d C\n", tmp);
270 printf("Temperature: %d C, calibration data 0x%x\n",
272 while (tmp >= boot_limit) {
274 printf("CPU is %d C, too hot to boot, waiting...\n",
281 tmp = read_cpu_temperature();
282 if (tmp > boot_limit - TEMP_WARN_THRESHOLD && tmp != max_temp)
283 printf("WARNING: CPU temperature %d C\n", tmp);
290 static void imx_set_wdog_powerdown(bool enable)
292 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
293 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
295 /* Write to the PDE (Power Down Enable) bit */
296 writew(enable, &wdog1->wmcr);
297 writew(enable, &wdog2->wmcr);
300 #ifdef CONFIG_ARCH_CPU_INIT
301 int arch_cpu_init(void)
305 set_vddsoc(1200); /* Set VDDSOC to 1.2V */
307 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
309 #ifdef CONFIG_VIDEO_IPUV3
310 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
312 #ifdef CONFIG_APBH_DMA
313 /* Timer is required for Initializing APBH DMA */
321 #ifndef CONFIG_SYS_DCACHE_OFF
322 void enable_caches(void)
324 /* Enable D-cache. I-cache is already enabled in start.S */
329 #if defined(CONFIG_FEC_MXC)
330 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
332 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
333 struct fuse_bank *bank = &ocotp->bank[4];
334 struct fuse_bank4_regs *fuse =
335 (struct fuse_bank4_regs *)bank->fuse_regs;
337 u32 value = readl(&fuse->mac_addr_high);
338 mac[0] = (value >> 8);
341 value = readl(&fuse->mac_addr_low);
342 mac[2] = value >> 24;
343 mac[3] = value >> 16;
349 void boot_mode_apply(unsigned cfg_val)
352 struct src *psrc = (struct src *)SRC_BASE_ADDR;
353 writel(cfg_val, &psrc->gpr9);
354 reg = readl(&psrc->gpr10);
359 writel(reg, &psrc->gpr10);
362 * cfg_val will be used for
363 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
364 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
365 * to SBMR1, which will determine the boot device.
367 const struct boot_mode soc_boot_modes[] = {
368 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
369 /* reserved value should start rom usb */
370 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
371 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
372 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
373 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
374 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
375 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
376 /* 4 bit bus width */
377 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
378 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
379 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
380 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},