3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/dma.h>
19 #include <asm/arch/mxc_hdmi.h>
20 #include <asm/arch/crm_regs.h>
32 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
33 u32 reg = readl(&anatop->digprog_sololite);
34 u32 type = ((reg >> 16) & 0xff);
36 if (type != MXC_CPU_MX6SL) {
37 reg = readl(&anatop->digprog);
38 type = ((reg >> 16) & 0xff);
39 if (type == MXC_CPU_MX6DL) {
40 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
41 u32 cfg = readl(&scu->config) & 3;
44 type = MXC_CPU_MX6SOLO;
47 reg &= 0xff; /* mx6 silicon revision */
48 return (type << 12) | (reg + 0x10);
51 #ifdef CONFIG_REVISION_TAG
52 u32 __weak get_board_rev(void)
54 u32 cpurev = get_cpu_rev();
55 u32 type = ((cpurev >> 12) & 0xff);
56 if (type == MXC_CPU_MX6SOLO)
57 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
65 struct aipstz_regs *aips1, *aips2;
67 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
68 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
71 * Set all MPROTx to be non-bufferable, trusted for R/W,
72 * not forced to user-mode.
74 writel(0x77777777, &aips1->mprot0);
75 writel(0x77777777, &aips1->mprot1);
76 writel(0x77777777, &aips2->mprot0);
77 writel(0x77777777, &aips2->mprot1);
80 * Set all OPACRx to be non-bufferable, not require
81 * supervisor privilege level for access,allow for
82 * write access and untrusted master access.
84 writel(0x00000000, &aips1->opacr0);
85 writel(0x00000000, &aips1->opacr1);
86 writel(0x00000000, &aips1->opacr2);
87 writel(0x00000000, &aips1->opacr3);
88 writel(0x00000000, &aips1->opacr4);
89 writel(0x00000000, &aips2->opacr0);
90 writel(0x00000000, &aips2->opacr1);
91 writel(0x00000000, &aips2->opacr2);
92 writel(0x00000000, &aips2->opacr3);
93 writel(0x00000000, &aips2->opacr4);
96 static void clear_ldo_ramp(void)
98 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
101 /* ROM may modify LDO ramp up time according to fuse setting, so in
102 * order to be in the safe side we neeed to reset these settings to
103 * match the reset value: 0'b00
105 reg = readl(&anatop->ana_misc2);
106 reg &= ~(0x3f << 24);
107 writel(reg, &anatop->ana_misc2);
113 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
114 * them to the specified millivolt level.
115 * Possible values are from 0.725V to 1.450V in steps of
118 static void set_vddsoc(u32 mv)
120 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
121 u32 val, reg = readl(&anatop->reg_core);
124 val = 0x00; /* Power gated off */
126 val = 0x1F; /* Power FET switched full on. No regulation */
128 val = (mv - 700) / 25;
133 * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
134 * and set them to the calculated value (0.7V + val * 0.25V)
136 reg = (reg & ~(0x1F << 18)) | (val << 18);
137 writel(reg, &anatop->reg_core);
140 static void imx_set_wdog_powerdown(bool enable)
142 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
143 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
145 /* Write to the PDE (Power Down Enable) bit */
146 writew(enable, &wdog1->wmcr);
147 writew(enable, &wdog2->wmcr);
150 int arch_cpu_init(void)
154 set_vddsoc(1175); /* Set VDDSOC to 1.175V */
156 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
158 #ifdef CONFIG_APBH_DMA
166 #ifndef CONFIG_SYS_DCACHE_OFF
167 void enable_caches(void)
169 /* Avoid random hang when download by usb */
170 invalidate_dcache_all();
171 /* Enable D-cache. I-cache is already enabled in start.S */
176 #if defined(CONFIG_FEC_MXC)
177 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
179 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
180 struct fuse_bank *bank = &ocotp->bank[4];
181 struct fuse_bank4_regs *fuse =
182 (struct fuse_bank4_regs *)bank->fuse_regs;
184 u32 value = readl(&fuse->mac_addr_high);
185 mac[0] = (value >> 8);
188 value = readl(&fuse->mac_addr_low);
189 mac[2] = value >> 24 ;
190 mac[3] = value >> 16 ;
191 mac[4] = value >> 8 ;
197 void boot_mode_apply(unsigned cfg_val)
200 struct src *psrc = (struct src *)SRC_BASE_ADDR;
201 writel(cfg_val, &psrc->gpr9);
202 reg = readl(&psrc->gpr10);
207 writel(reg, &psrc->gpr10);
210 * cfg_val will be used for
211 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
212 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
213 * to SBMR1, which will determine the boot device.
215 const struct boot_mode soc_boot_modes[] = {
216 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
217 /* reserved value should start rom usb */
218 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
219 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
220 {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
221 {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
222 {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
223 {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
224 /* 4 bit bus width */
225 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
226 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
227 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
228 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
234 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
235 int is_6q = is_cpu_type(MXC_CPU_MX6Q);
239 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
240 * to make sure PFD is working right, otherwise, PFDs may
241 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
242 * workaround in ROM code, as bus clock need it
245 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
246 ANATOP_PFD_CLKGATE_MASK(1) |
247 ANATOP_PFD_CLKGATE_MASK(2) |
248 ANATOP_PFD_CLKGATE_MASK(3);
249 mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
250 ANATOP_PFD_CLKGATE_MASK(1) |
251 ANATOP_PFD_CLKGATE_MASK(3);
254 * Don't reset PFD2 on DL/S
257 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
258 writel(mask480, &anatop->pfd_480_set);
259 writel(mask528, &anatop->pfd_528_set);
260 writel(mask480, &anatop->pfd_480_clr);
261 writel(mask528, &anatop->pfd_528_clr);
264 #ifdef CONFIG_IMX_HDMI
265 void imx_enable_hdmi_phy(void)
267 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
269 reg = readb(&hdmi->phy_conf0);
270 reg |= HDMI_PHY_CONF0_PDZ_MASK;
271 writeb(reg, &hdmi->phy_conf0);
273 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
274 writeb(reg, &hdmi->phy_conf0);
276 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
277 writeb(reg, &hdmi->phy_conf0);
278 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
281 void imx_setup_hdmi(void)
283 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
284 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
287 /* Turn on HDMI PHY clock */
288 reg = readl(&mxc_ccm->CCGR2);
289 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
290 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
291 writel(reg, &mxc_ccm->CCGR2);
292 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
293 reg = readl(&mxc_ccm->chsccdr);
294 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
295 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
296 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
297 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
298 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
299 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
300 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
301 writel(reg, &mxc_ccm->chsccdr);