arch/arm/cpu/armv7/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <asm/emif.h>
  30 #include <asm/arch/sys_proto.h>
  31
  32 /*
  33  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  34  * SDP and Panda. Since the parts used and geometry are identical for
  35  * SDP and Panda for a given OMAP4 revision, this information is kept
  36  * here instead of being in board directory. However the key functions
  37  * exported are weakly linked so that they can be over-ridden in the board
  38  * directory if there is a OMAP4 board in the future that uses a different
  39  * memory device or geometry.
  40  *
  41  * For any new board with different memory devices over-ride one or more
  42  * of the following functions as per the CONFIG flags you intend to enable:
  43  * - emif_get_reg_dump()
  44  * - emif_get_dmm_regs()
  45  * - emif_get_device_details()
  46  * - emif_get_device_timings()
  47  */
  48
  49 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  50
  51 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  52         .sdram_config_init              = 0x80000eb9,
  53         .sdram_config                   = 0x80001ab9,
  54         .ref_ctrl                       = 0x0000030c,
  55         .sdram_tim1                     = 0x08648311,
  56         .sdram_tim2                     = 0x101b06ca,
  57         .sdram_tim3                     = 0x0048a19f,
  58         .read_idle_ctrl                 = 0x000501ff,
  59         .zq_config                      = 0x500b3214,
  60         .temp_alert_config              = 0xd8016893,
  61         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  62         .emif_ddr_phy_ctlr_1            = 0x049ff808
  63 };
  64
  65 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  66         .sdram_config_init              = 0x80000eb1,
  67         .sdram_config                   = 0x80001ab1,
  68         .ref_ctrl                       = 0x000005cd,
  69         .sdram_tim1                     = 0x10cb0622,
  70         .sdram_tim2                     = 0x20350d52,
  71         .sdram_tim3                     = 0x00b1431f,
  72         .read_idle_ctrl                 = 0x000501ff,
  73         .zq_config                      = 0x500b3214,
  74         .temp_alert_config              = 0x58016893,
  75         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  76         .emif_ddr_phy_ctlr_1            = 0x049ff418
  77 };
  78
  79 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  80         .sdram_config_init              = 0x80000eb9,
  81         .sdram_config                   = 0x80001ab9,
  82         .ref_ctrl                       = 0x00000618,
  83         .sdram_tim1                     = 0x10eb0662,
  84         .sdram_tim2                     = 0x20370dd2,
  85         .sdram_tim3                     = 0x00b1c33f,
  86         .read_idle_ctrl                 = 0x000501ff,
  87         .zq_config                      = 0xd00b3214,
  88         .temp_alert_config              = 0xd8016893,
  89         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  90         .emif_ddr_phy_ctlr_1            = 0x049ff418
  91 };
  92 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  93         .dmm_lisa_map_0 = 0xFF020100,
  94         .dmm_lisa_map_1 = 0,
  95         .dmm_lisa_map_2 = 0,
  96         .dmm_lisa_map_3 = 0x80540300
  97 };
  98
  99 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 100         .dmm_lisa_map_0 = 0xFF020100,
 101         .dmm_lisa_map_1 = 0,
 102         .dmm_lisa_map_2 = 0,
 103         .dmm_lisa_map_3 = 0x80640300
 104 };
 105
 106 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 107 {
 108         u32 omap4_rev = omap_revision();
 109
 110         /* Same devices and geometry on both EMIFs */
 111         if (omap4_rev == OMAP4430_ES1_0)
 112                 *regs = &emif_regs_elpida_380_mhz_1cs;
 113         else if (omap4_rev == OMAP4430_ES2_0)
 114                 *regs = &emif_regs_elpida_200_mhz_2cs;
 115         else
 116                 *regs = &emif_regs_elpida_400_mhz_2cs;
 117 }
 118 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 119         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 120
 121 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 122                                                 **dmm_lisa_regs)
 123 {
 124         u32 omap_rev = omap_revision();
 125
 126         if (omap_rev == OMAP4430_ES1_0)
 127                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 128         else
 129                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 130 }
 131
 132 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 133         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 134
 135 #else
 136
 137 static const struct lpddr2_device_details elpida_2G_S4_details = {
 138         .type           = LPDDR2_TYPE_S4,
 139         .density        = LPDDR2_DENSITY_2Gb,
 140         .io_width       = LPDDR2_IO_WIDTH_32,
 141         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 142 };
 143
 144 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 145                         struct lpddr2_device_details *lpddr2_dev_details)
 146 {
 147         u32 omap_rev = omap_revision();
 148
 149         /* EMIF1 & EMIF2 have identical configuration */
 150         if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
 151                 /* Nothing connected on CS1 for ES1.0 */
 152                 return NULL;
 153         } else {
 154                 /* In all other cases Elpida 2G device */
 155                 *lpddr2_dev_details = elpida_2G_S4_details;
 156                 return lpddr2_dev_details;
 157         }
 158 }
 159
 160 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 161                         struct lpddr2_device_details *lpddr2_dev_details)
 162         __attribute__((weak, alias("emif_get_device_details_sdp")));
 163
 164 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 165
 166 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 167 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 168         .max_freq       = 400000000,
 169         .RL             = 6,
 170         .tRPab          = 21,
 171         .tRCD           = 18,
 172         .tWR            = 15,
 173         .tRASmin        = 42,
 174         .tRRD           = 10,
 175         .tWTRx2         = 15,
 176         .tXSR           = 140,
 177         .tXPx2          = 15,
 178         .tRFCab         = 130,
 179         .tRTPx2         = 15,
 180         .tCKE           = 3,
 181         .tCKESR         = 15,
 182         .tZQCS          = 90,
 183         .tZQCL          = 360,
 184         .tZQINIT        = 1000,
 185         .tDQSCKMAXx2    = 11,
 186         .tRASmax        = 70,
 187         .tFAW           = 50
 188 };
 189
 190 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 191         .max_freq       = 333000000,
 192         .RL             = 5,
 193         .tRPab          = 21,
 194         .tRCD           = 18,
 195         .tWR            = 15,
 196         .tRASmin        = 42,
 197         .tRRD           = 10,
 198         .tWTRx2         = 15,
 199         .tXSR           = 140,
 200         .tXPx2          = 15,
 201         .tRFCab         = 130,
 202         .tRTPx2         = 15,
 203         .tCKE           = 3,
 204         .tCKESR         = 15,
 205         .tZQCS          = 90,
 206         .tZQCL          = 360,
 207         .tZQINIT        = 1000,
 208         .tDQSCKMAXx2    = 11,
 209         .tRASmax        = 70,
 210         .tFAW           = 50
 211 };
 212
 213 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 214         .max_freq       = 200000000,
 215         .RL             = 3,
 216         .tRPab          = 21,
 217         .tRCD           = 18,
 218         .tWR            = 15,
 219         .tRASmin        = 42,
 220         .tRRD           = 10,
 221         .tWTRx2         = 20,
 222         .tXSR           = 140,
 223         .tXPx2          = 15,
 224         .tRFCab         = 130,
 225         .tRTPx2         = 15,
 226         .tCKE           = 3,
 227         .tCKESR         = 15,
 228         .tZQCS          = 90,
 229         .tZQCL          = 360,
 230         .tZQINIT        = 1000,
 231         .tDQSCKMAXx2    = 11,
 232         .tRASmax        = 70,
 233         .tFAW           = 50
 234 };
 235
 236 static const struct lpddr2_min_tck min_tck_elpida = {
 237         .tRL            = 3,
 238         .tRP_AB         = 3,
 239         .tRCD           = 3,
 240         .tWR            = 3,
 241         .tRAS_MIN       = 3,
 242         .tRRD           = 2,
 243         .tWTR           = 2,
 244         .tXP            = 2,
 245         .tRTP           = 2,
 246         .tCKE           = 3,
 247         .tCKESR         = 3,
 248         .tFAW           = 8
 249 };
 250
 251 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 252                 &timings_elpida_200_mhz,
 253                 &timings_elpida_333_mhz,
 254                 &timings_elpida_400_mhz
 255 };
 256
 257 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
 258         .ac_timings     = elpida_ac_timings,
 259         .min_tck        = &min_tck_elpida,
 260 };
 261
 262 void emif_get_device_timings_sdp(u32 emif_nr,
 263                 const struct lpddr2_device_timings **cs0_device_timings,
 264                 const struct lpddr2_device_timings **cs1_device_timings)
 265 {
 266         u32 omap_rev = omap_revision();
 267
 268         /* Identical devices on EMIF1 & EMIF2 */
 269         *cs0_device_timings = &elpida_2G_S4_timings;
 270
 271         if (omap_rev == OMAP4430_ES1_0)
 272                 *cs1_device_timings = NULL;
 273         else
 274                 *cs1_device_timings = &elpida_2G_S4_timings;
 275 }
 276
 277 void emif_get_device_timings(u32 emif_nr,
 278                 const struct lpddr2_device_timings **cs0_device_timings,
 279                 const struct lpddr2_device_timings **cs1_device_timings)
 280         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 281
 282 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */