arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <asm/emif.h>
  31 #include <asm/arch/sys_proto.h>
  32
  33 /*
  34  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  35  * EVM. Since the parts used and geometry are identical for
  36  * evm for a given OMAP5 revision, this information is kept
  37  * here instead of being in board directory. However the key functions
  38  * exported are weakly linked so that they can be over-ridden in the board
  39  * directory if there is a OMAP5 board in the future that uses a different
  40  * memory device or geometry.
  41  *
  42  * For any new board with different memory devices over-ride one or more
  43  * of the following functions as per the CONFIG flags you intend to enable:
  44  * - emif_get_reg_dump()
  45  * - emif_get_dmm_regs()
  46  * - emif_get_device_details()
  47  * - emif_get_device_timings()
  48  */
  49
  50 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  51 const struct emif_regs emif_regs_532_mhz_2cs = {
  52         .sdram_config_init              = 0x80800EBA,
  53         .sdram_config                   = 0x808022BA,
  54         .ref_ctrl                       = 0x0000081A,
  55         .sdram_tim1                     = 0x772F6873,
  56         .sdram_tim2                     = 0x304a129a,
  57         .sdram_tim3                     = 0x02f7e45f,
  58         .read_idle_ctrl                 = 0x00050000,
  59         .zq_config                      = 0x000b3215,
  60         .temp_alert_config              = 0x08000a05,
  61         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  62         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  63         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  64         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  65         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  66         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  67         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  68 };
  69
  70 const struct emif_regs emif_regs_266_mhz_2cs = {
  71         .sdram_config_init              = 0x80800EBA,
  72         .sdram_config                   = 0x808022BA,
  73         .ref_ctrl                       = 0x0000040D,
  74         .sdram_tim1                     = 0x2A86B419,
  75         .sdram_tim2                     = 0x1025094A,
  76         .sdram_tim3                     = 0x026BA22F,
  77         .read_idle_ctrl                 = 0x00050000,
  78         .zq_config                      = 0x000b3215,
  79         .temp_alert_config              = 0x08000a05,
  80         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  81         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  82         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  83         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  84         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  85         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  86         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  87 };
  88
  89 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  90         .sdram_config_init              = 0x61851B32,
  91         .sdram_config                   = 0x61851B32,
  92         .ref_ctrl                       = 0x00001035,
  93         .sdram_tim1                     = 0xCCCF36B3,
  94         .sdram_tim2                     = 0x308F7FDA,
  95         .sdram_tim3                     = 0x027F88A8,
  96         .read_idle_ctrl                 = 0x00050000,
  97         .zq_config                      = 0x0007190B,
  98         .temp_alert_config              = 0x00000000,
  99         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 100         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 101         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 102         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 103         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 104         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 105         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 106         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 107         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 108         .emif_rd_wr_lvl_ctl             = 0x00000000,
 109         .emif_rd_wr_exec_thresh         = 0x00000305
 110 };
 111
 112 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 113         .dmm_lisa_map_0 = 0x0,
 114         .dmm_lisa_map_1 = 0x0,
 115         .dmm_lisa_map_2 = 0x80740300,
 116         .dmm_lisa_map_3 = 0xFF020100
 117 };
 118
 119 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 120 {
 121         switch (omap_revision()) {
 122         case OMAP5430_ES1_0:
 123                 *regs = &emif_regs_532_mhz_2cs;
 124                 break;
 125         case OMAP5432_ES1_0:
 126                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 127                 break;
 128         default:
 129                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 130         }
 131 }
 132
 133 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 134         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 135
 136 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 137                                                 **dmm_lisa_regs)
 138 {
 139         *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 140 }
 141
 142 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 143         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 144 #else
 145
 146 static const struct lpddr2_device_details dev_4G_S4_details = {
 147         .type           = LPDDR2_TYPE_S4,
 148         .density        = LPDDR2_DENSITY_4Gb,
 149         .io_width       = LPDDR2_IO_WIDTH_32,
 150         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 151 };
 152
 153 static void emif_get_device_details_sdp(u32 emif_nr,
 154                 struct lpddr2_device_details *cs0_device_details,
 155                 struct lpddr2_device_details *cs1_device_details)
 156 {
 157         /* EMIF1 & EMIF2 have identical configuration */
 158         *cs0_device_details = dev_4G_S4_details;
 159         *cs1_device_details = dev_4G_S4_details;
 160 }
 161
 162 void emif_get_device_details(u32 emif_nr,
 163                 struct lpddr2_device_details *cs0_device_details,
 164                 struct lpddr2_device_details *cs1_device_details)
 165         __attribute__((weak, alias("emif_get_device_details_sdp")));
 166
 167 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 168
 169 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 170         0x01004010,
 171         0x00001004,
 172         0x04010040,
 173         0x01004010,
 174         0x00001004,
 175         0x00000000,
 176         0x00000000,
 177         0x00000000,
 178         0x80080080,
 179         0x00800800,
 180         0x08102040,
 181         0x00000001,
 182         0x540A8150,
 183         0xA81502a0,
 184         0x002A0540,
 185         0x00000000,
 186         0x00000000,
 187         0x00000000,
 188         0x00000077
 189 };
 190
 191 const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 192         0x01004010,
 193         0x00001004,
 194         0x04010040,
 195         0x01004010,
 196         0x00001004,
 197         0x00000000,
 198         0x00000000,
 199         0x00000000,
 200         0x80080080,
 201         0x00800800,
 202         0x08102040,
 203         0x00000002,
 204         0x0,
 205         0x0,
 206         0x0,
 207         0x00000000,
 208         0x00000000,
 209         0x00000000,
 210         0x00000057
 211 };
 212
 213 const struct lpddr2_mr_regs mr_regs = {
 214         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 215         .mr2    = 0x6,
 216         .mr3    = 0x1,
 217         .mr10   = MR10_ZQ_ZQINIT,
 218         .mr16   = MR16_REF_FULL_ARRAY
 219 };
 220
 221 static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
 222 {
 223         switch (omap_revision()) {
 224         case OMAP5430_ES1_0:
 225                 *regs = ext_phy_ctrl_const_base;
 226                 break;
 227         case OMAP5432_ES1_0:
 228                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 229                 break;
 230         default:
 231                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 232         }
 233 }
 234
 235 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 236 {
 237         *regs = &mr_regs;
 238 }
 239
 240 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 241 {
 242         u32 *ext_phy_ctrl_base = 0;
 243         u32 *emif_ext_phy_ctrl_base = 0;
 244         const u32 *ext_phy_ctrl_const_regs;
 245         u32 i = 0;
 246
 247         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 248
 249         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 250         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 251
 252         /* Configure external phy control timing registers */
 253         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 254                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 255                 /* Update shadow registers */
 256                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 257         }
 258
 259         /*
 260          * external phy 6-24 registers do not change with
 261          * ddr frequency
 262          */
 263         emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
 264         for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
 265                 writel(ext_phy_ctrl_const_regs[i],
 266                        emif_ext_phy_ctrl_base++);
 267                 /* Update shadow registers */
 268                 writel(ext_phy_ctrl_const_regs[i],
 269                        emif_ext_phy_ctrl_base++);
 270         }
 271 }
 272
 273 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 274 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 275         .max_freq       = 532000000,
 276         .RL             = 8,
 277         .tRPab          = 21,
 278         .tRCD           = 18,
 279         .tWR            = 15,
 280         .tRASmin        = 42,
 281         .tRRD           = 10,
 282         .tWTRx2         = 15,
 283         .tXSR           = 140,
 284         .tXPx2          = 15,
 285         .tRFCab         = 130,
 286         .tRTPx2         = 15,
 287         .tCKE           = 3,
 288         .tCKESR         = 15,
 289         .tZQCS          = 90,
 290         .tZQCL          = 360,
 291         .tZQINIT        = 1000,
 292         .tDQSCKMAXx2    = 11,
 293         .tRASmax        = 70,
 294         .tFAW           = 50
 295 };
 296
 297 static const struct lpddr2_min_tck min_tck = {
 298         .tRL            = 3,
 299         .tRP_AB         = 3,
 300         .tRCD           = 3,
 301         .tWR            = 3,
 302         .tRAS_MIN       = 3,
 303         .tRRD           = 2,
 304         .tWTR           = 2,
 305         .tXP            = 2,
 306         .tRTP           = 2,
 307         .tCKE           = 3,
 308         .tCKESR         = 3,
 309         .tFAW           = 8
 310 };
 311
 312 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 313         &timings_jedec_532_mhz
 314 };
 315
 316 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 317         .ac_timings     = ac_timings,
 318         .min_tck        = &min_tck,
 319 };
 320
 321 void emif_get_device_timings_sdp(u32 emif_nr,
 322                 const struct lpddr2_device_timings **cs0_device_timings,
 323                 const struct lpddr2_device_timings **cs1_device_timings)
 324 {
 325         /* Identical devices on EMIF1 & EMIF2 */
 326         *cs0_device_timings = &dev_4G_S4_timings;
 327         *cs1_device_timings = &dev_4G_S4_timings;
 328 }
 329
 330 void emif_get_device_timings(u32 emif_nr,
 331                 const struct lpddr2_device_timings **cs0_device_timings,
 332                 const struct lpddr2_device_timings **cs1_device_timings)
 333         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 334
 335 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */