arch/arm/cpu/armv7/socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/u-boot.h>
  10 #include <asm/utils.h>
  11 #include <version.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 #define MAIN_VCO_BASE (                                 \
  23         (CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<             \
  24                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |   \
  25         (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<             \
  26                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)     \
  27         )
  28
  29 #define PERI_VCO_BASE (                                 \
  30         (CONFIG_HPS_PERPLLGRP_VCO_PSRC <<               \
  31                 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |     \
  32         (CONFIG_HPS_PERPLLGRP_VCO_DENOM <<              \
  33                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |    \
  34         (CONFIG_HPS_PERPLLGRP_VCO_NUMER <<              \
  35                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)      \
  36         )
  37
  38 #define SDR_VCO_BASE (                                  \
  39         (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<               \
  40                 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |     \
  41         (CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<              \
  42                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |    \
  43         (CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<              \
  44                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)      \
  45         )
  46
  47 u32 spl_boot_device(void)
  48 {
  49         return BOOT_DEVICE_RAM;
  50 }
  51
  52 /*
  53  * Board initialization after bss clearance
  54  */
  55 void spl_board_init(void)
  56 {
  57 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  58         cm_config_t cm_default_cfg = {
  59                 /* main group */
  60                 MAIN_VCO_BASE,
  61                 (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  62                         CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  63                 (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  64                         CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  65                 (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  66                         CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  67                 (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  68                         CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  69                 (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
  70                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
  71                 (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
  72                         CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
  73                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
  74                         CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
  75                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
  76                         CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
  77                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
  78                         CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
  79                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
  80                         CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
  81                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
  82                         CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
  83                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
  84                         CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
  85                 (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
  86                         CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
  87                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
  88                         CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
  89                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
  90                         CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
  91
  92                 /* peripheral group */
  93                 PERI_VCO_BASE,
  94                 (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
  95                         CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
  96                 (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
  97                         CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
  98                 (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
  99                         CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
 100                 (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
 101                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
 102                 (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
 103                         CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
 104                 (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
 105                         CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
 106                 (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
 107                         CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
 108                 (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
 109                         CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
 110                 (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
 111                         CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
 112                 (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
 113                         CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
 114                 (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
 115                         CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
 116                 (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
 117                         CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
 118                 (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
 119                         CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
 120                 (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
 121                         CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 122
 123                 /* sdram pll group */
 124                 SDR_VCO_BASE,
 125                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
 126                         CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
 127                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
 128                         CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
 129                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
 130                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
 131                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
 132                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
 133                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
 134                         CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
 135                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
 136                         CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
 137                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
 138                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
 139                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
 140                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 141
 142         };
 143
 144         debug("Freezing all I/O banks\n");
 145         /* freeze all IO banks */
 146         sys_mgr_frzctrl_freeze_req();
 147
 148         debug("Reconfigure Clock Manager\n");
 149         /* reconfigure the PLLs */
 150         cm_basic_init(&cm_default_cfg);
 151
 152         /* configure the IOCSR / IO buffer settings */
 153         if (scan_mgr_configure_iocsr())
 154                 hang();
 155
 156         /* configure the pin muxing through system manager */
 157         sysmgr_pinmux_init();
 158 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 159
 160         /* de-assert reset for peripherals and bridges based on handoff */
 161         reset_deassert_peripherals_handoff();
 162
 163         debug("Unfreezing/Thaw all I/O banks\n");
 164         /* unfreeze / thaw all IO banks */
 165         sys_mgr_frzctrl_thaw_req();
 166
 167         /* enable console uart printing */
 168         preloader_console_init();
 169 }