arch/arm/cpu/armv7/socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static struct pl310_regs *const pl310 =
  24         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  25
  26 #define MAIN_VCO_BASE (                                 \
  27         (CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<             \
  28                 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |   \
  29         (CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<             \
  30                 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)     \
  31         )
  32
  33 #define PERI_VCO_BASE (                                 \
  34         (CONFIG_HPS_PERPLLGRP_VCO_PSRC <<               \
  35                 CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |     \
  36         (CONFIG_HPS_PERPLLGRP_VCO_DENOM <<              \
  37                 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |    \
  38         (CONFIG_HPS_PERPLLGRP_VCO_NUMER <<              \
  39                 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)      \
  40         )
  41
  42 #define SDR_VCO_BASE (                                  \
  43         (CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<               \
  44                 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |     \
  45         (CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<              \
  46                 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |    \
  47         (CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<              \
  48                 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)      \
  49         )
  50
  51 void board_init_f(ulong dummy)
  52 {
  53         struct socfpga_system_manager *sysmgr_regs =
  54                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  55         unsigned long reg;
  56         /*
  57          * First C code to run. Clear fake OCRAM ECC first as SBE
  58          * and DBE might triggered during power on
  59          */
  60         reg = readl(&sysmgr_regs->eccgrp_ocram);
  61         if (reg & SYSMGR_ECC_OCRAM_SERR)
  62                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  63                        &sysmgr_regs->eccgrp_ocram);
  64         if (reg & SYSMGR_ECC_OCRAM_DERR)
  65                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  66                        &sysmgr_regs->eccgrp_ocram);
  67
  68         memset(__bss_start, 0, __bss_end - __bss_start);
  69
  70         /* Remap SDRAM to 0x0 */
  71         writel(0x1, &pl310->pl310_addr_filter_start);
  72
  73         board_init_r(NULL, 0);
  74 }
  75
  76 u32 spl_boot_device(void)
  77 {
  78         return BOOT_DEVICE_RAM;
  79 }
  80
  81 /*
  82  * Board initialization after bss clearance
  83  */
  84 void spl_board_init(void)
  85 {
  86         unsigned long sdram_size;
  87 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  88         cm_config_t cm_default_cfg = {
  89                 /* main group */
  90                 MAIN_VCO_BASE,
  91                 (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
  92                         CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
  93                 (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
  94                         CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
  95                 (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
  96                         CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
  97                 (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
  98                         CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
  99                 (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
 100                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
 101                 (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
 102                         CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
 103                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
 104                         CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
 105                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
 106                         CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
 107                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
 108                         CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
 109                 (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
 110                         CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
 111                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
 112                         CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
 113                 (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
 114                         CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
 115                 (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
 116                         CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
 117                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
 118                         CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
 119                 (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
 120                         CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
 121
 122                 /* peripheral group */
 123                 PERI_VCO_BASE,
 124                 (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
 125                         CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
 126                 (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
 127                         CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
 128                 (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
 129                         CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
 130                 (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
 131                         CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
 132                 (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
 133                         CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
 134                 (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
 135                         CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
 136                 (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
 137                         CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
 138                 (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
 139                         CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
 140                 (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
 141                         CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
 142                 (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
 143                         CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
 144                 (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
 145                         CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
 146                 (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
 147                         CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
 148                 (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
 149                         CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
 150                 (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
 151                         CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
 152
 153                 /* sdram pll group */
 154                 SDR_VCO_BASE,
 155                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
 156                         CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
 157                 (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
 158                         CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
 159                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
 160                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
 161                 (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
 162                         CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
 163                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
 164                         CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
 165                 (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
 166                         CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
 167                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
 168                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
 169                 (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
 170                         CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
 171
 172         };
 173
 174         debug("Freezing all I/O banks\n");
 175         /* freeze all IO banks */
 176         sys_mgr_frzctrl_freeze_req();
 177
 178         socfpga_sdram_enable();
 179         socfpga_uart0_enable();
 180         socfpga_osc1timer_enable();
 181
 182         timer_init();
 183
 184         debug("Reconfigure Clock Manager\n");
 185         /* reconfigure the PLLs */
 186         cm_basic_init(&cm_default_cfg);
 187
 188         /* Enable bootrom to configure IOs. */
 189         sysmgr_enable_warmrstcfgio();
 190
 191         /* configure the IOCSR / IO buffer settings */
 192         if (scan_mgr_configure_iocsr())
 193                 hang();
 194
 195         /* configure the pin muxing through system manager */
 196         sysmgr_pinmux_init();
 197 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 198
 199         /* de-assert reset for peripherals and bridges based on handoff */
 200         reset_deassert_peripherals_handoff();
 201
 202         debug("Unfreezing/Thaw all I/O banks\n");
 203         /* unfreeze / thaw all IO banks */
 204         sys_mgr_frzctrl_thaw_req();
 205
 206         /* enable console uart printing */
 207         preloader_console_init();
 208
 209         if (sdram_mmr_init_full(0xffffffff) != 0) {
 210                 puts("SDRAM init failed.\n");
 211                 hang();
 212         }
 213
 214         debug("SDRAM: Calibrating PHY\n");
 215         /* SDRAM calibration */
 216         if (sdram_calibration_full() == 0) {
 217                 puts("SDRAM calibration failed.\n");
 218                 hang();
 219         }
 220
 221         sdram_size = sdram_calculate_size();
 222         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 223
 224         /* Sanity check ensure correct SDRAM size specified */
 225         if (get_ram_size(0, sdram_size) != sdram_size) {
 226                 puts("SDRAM size check failed!\n");
 227                 hang();
 228         }
 229 }