sunxi: add sun7i clocks and timer support.
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun4i.c
1 /*
2  * sun4i, sun5i and sun7i specific clock code
3  *
4  * (C) Copyright 2007-2012
5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6  * Tom Cubie <tangliang@allwinnertech.com>
7  *
8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 #include <common.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/sys_proto.h>
18
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
21 {
22         struct sunxi_ccm_reg * const ccm =
23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24
25         /* Set safe defaults until PMU is configured */
26         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
27                AHB_DIV_2 << AHB_DIV_SHIFT |
28                APB0_DIV_1 << APB0_DIV_SHIFT |
29                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
30                &ccm->cpu_ahb_apb0_cfg);
31         writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
32         sdelay(200);
33         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
34                AHB_DIV_2 << AHB_DIV_SHIFT |
35                APB0_DIV_1 << APB0_DIV_SHIFT |
36                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
37                &ccm->cpu_ahb_apb0_cfg);
38 #ifdef CONFIG_SUN7I
39         writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
40                &ccm->ahb_gate0);
41 #endif
42         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
43 }
44 #endif
45
46 void clock_init_uart(void)
47 {
48         struct sunxi_ccm_reg *const ccm =
49                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
50
51         /* uart clock source is apb1 */
52         writel(APB1_CLK_SRC_OSC24M|
53                APB1_CLK_RATE_N_1|
54                APB1_CLK_RATE_M(1),
55                &ccm->apb1_clk_div_cfg);
56
57         /* open the clock for uart */
58         setbits_le32(&ccm->apb1_gate,
59                 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
60 }
61
62 int clock_twi_onoff(int port, int state)
63 {
64         struct sunxi_ccm_reg *const ccm =
65                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
66
67         if (port > 2)
68                 return -1;
69
70         /* set the apb clock gate for twi */
71         if (state)
72                 setbits_le32(&ccm->apb1_gate,
73                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
74         else
75                 clrbits_le32(&ccm->apb1_gate,
76                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
77
78         return 0;
79 }
80
81 #ifdef CONFIG_SPL_BUILD
82 #define PLL1_CFG(N, K, M, P)    ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
83                                   0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
84                                   8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
85                                   0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
86                                  16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
87                                  (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
88                                   2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
89                                  (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
90                                  (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
91                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
92                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
93                                  (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
94
95 static struct {
96         u32 pll1_cfg;
97         unsigned int freq;
98 } pll1_para[] = {
99         /* This array must be ordered by frequency. */
100         { PLL1_CFG(16, 0, 0, 0), 384000000 },
101         { PLL1_CFG(16, 1, 0, 0), 768000000 },
102         { PLL1_CFG(20, 1, 0, 0), 960000000 },
103         { PLL1_CFG(21, 1, 0, 0), 1008000000},
104         { PLL1_CFG(22, 1, 0, 0), 1056000000},
105         { PLL1_CFG(23, 1, 0, 0), 1104000000},
106         { PLL1_CFG(24, 1, 0, 0), 1152000000},
107         { PLL1_CFG(25, 1, 0, 0), 1200000000},
108         { PLL1_CFG(26, 1, 0, 0), 1248000000},
109         { PLL1_CFG(27, 1, 0, 0), 1296000000},
110         { PLL1_CFG(28, 1, 0, 0), 1344000000},
111         { PLL1_CFG(29, 1, 0, 0), 1392000000},
112         { PLL1_CFG(30, 1, 0, 0), 1440000000},
113         { PLL1_CFG(31, 1, 0, 0), 1488000000},
114         /* Final catchall entry */
115         { PLL1_CFG(31, 1, 0, 0), ~0},
116 };
117
118 void clock_set_pll1(unsigned int hz)
119 {
120         int i = 0;
121         int axi, ahb, apb0;
122         struct sunxi_ccm_reg * const ccm =
123                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
124
125         /* Find target frequency */
126         while (pll1_para[i].freq < hz)
127                 i++;
128
129         hz = pll1_para[i].freq;
130
131         /* Calculate system clock divisors */
132         axi = DIV_ROUND_UP(hz, 432000000);      /* Max 450MHz */
133         ahb = DIV_ROUND_UP(hz/axi, 204000000);  /* Max 250MHz */
134         apb0 = 2;                               /* Max 150MHz */
135
136         printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
137
138         /* Map divisors to register values */
139         axi = axi - 1;
140         if (ahb > 4)
141                 ahb = 3;
142         else if (ahb > 2)
143                 ahb = 2;
144         else if (ahb > 1)
145                 ahb = 1;
146         else
147                 ahb = 0;
148
149         apb0 = apb0 - 1;
150
151         /* Switch to 24MHz clock while changing PLL1 */
152         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
153                AHB_DIV_2 << AHB_DIV_SHIFT |
154                APB0_DIV_1 << APB0_DIV_SHIFT |
155                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
156                &ccm->cpu_ahb_apb0_cfg);
157         sdelay(20);
158
159         /* Configure sys clock divisors */
160         writel(axi << AXI_DIV_SHIFT |
161                ahb << AHB_DIV_SHIFT |
162                apb0 << APB0_DIV_SHIFT |
163                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
164                &ccm->cpu_ahb_apb0_cfg);
165
166         /* Configure PLL1 at the desired frequency */
167         writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
168         sdelay(200);
169
170         /* Switch CPU to PLL1 */
171         writel(axi << AXI_DIV_SHIFT |
172                ahb << AHB_DIV_SHIFT |
173                apb0 << APB0_DIV_SHIFT |
174                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
175                &ccm->cpu_ahb_apb0_cfg);
176         sdelay(20);
177 }
178 #endif
179
180 unsigned int clock_get_pll6(void)
181 {
182         struct sunxi_ccm_reg *const ccm =
183                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
184         uint32_t rval = readl(&ccm->pll6_cfg);
185         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
186         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
187         return 24000000 * n * k / 2;
188 }