2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sbc-regs.h>
11 #include <asm/arch/sg-regs.h>
17 /* system bus output enable */
22 #if !defined(CONFIG_SPL_BUILD)
24 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
25 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
26 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
27 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
29 /* XECS1 : boot memory (always boot swap = on) */
30 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
31 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
32 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
33 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
35 /* XECS4 : sub memory */
36 writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
37 writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
38 writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
39 writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
41 /* XECS5 : peripherals */
42 writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
43 writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
44 writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
45 writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
47 /* base address regsiters */
48 writel(0x0000bc01, SBBASE0); /* boot memory */
49 writel(0x0900bfff, SBBASE1); /* dummy */
50 writel(0x0400bc01, SBBASE4); /* sub memory */
51 writel(0x0800bf01, SBBASE5); /* peripherals */
53 sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
54 sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
56 /* dummy read to assure write process */
57 readl(SG_PINCTRL(33));